4-BIT SINGLE CHIP MICROCOMPUTERS GMS34XXXT SERIES USER`S MANUAL • GMS34004T • GMS34112T • GMS34140T Revision 1.0 Published by MCU Application Team in Hyundai Electronics Industrial Co., Ltd. " Hyundai Electronics Industrial Co., Ltd. 1996 All Right Reserved. Editor's E-Mail : [email protected] [email protected] [email protected] Additional information of this manual may be served by Hyundai Electronics Industrial Offices in Korea or Distributors and Representative listed at address directory. Hyundai Electronics Industrial reserves the right to make changes to any Information here in at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, Hyundai Electronics Industrial Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Table of Contents Table of Contents Chapter 1 Introduction ............................................................................................1-1 Outline of Characteristics .................................................................1-1 Characteristics ..................................................................................1-1 Block Diagram ..................................................................................1-2 Pin Assignment and Terminal ..........................................................1-3 Pin Dimension ..................................................................................1-4 Pin Description and Circuit .................................................................1-7 I/O circuit types and options .............................................................1-8 Electrical Characteristics ................................................................1-10 Chapter 2 Architecture ...........................................................................................2-1 Block Description .............................................................................2-1 Program Memory (ROM) ..................................................................2-1 EPROM Address Register ................................................................2-2 Data Memory (RAM) ........................................................................2-3 X-Register (X) ...................................................................................2-3 Y-Register (Y) ...................................................................................2-4 Accumulator (Acc) ............................................................................2-4 Arithmetic and Logic Unit (ALU) .......................................................2-4 State Counter (SC) ...........................................................................2-5 Clock Generator ...............................................................................2-6 Pulse Generator ...............................................................................2-7 Initial Reset Circuit ............................................................................2-8 Watch Dog Timer (WDT) .................................................................2-8 Stop Function ....................................................................................2-9 Port Operation ..................................................................................2-9 Chapter 3 Instruction ........................................................................................3-1 Table of Contents Chapter 4 EPROM .................................................................................................4-1 GMS34004TK/34112TK/34140TK .........................................................4-1 Mode Define .....................................................................................4-1 Port Define .......................................................................................4-2 Programming Data ...........................................................................4-2 Write/Read Data Conversion ............................................................4-3 Checksum .........................................................................................4-3 Programming Control ........................................................................4-3 Programming DC Specification .........................................................4-3 EPROM read mode(1/2) ...................................................................4-4 EPROM read mode (2/2) ..................................................................4-4 EPROM write mode (1/2) ..................................................................4-5 EPROM write mode (2/2) ..................................................................4-5 Lock bit write mode (1/2) ..................................................................4-6 Lock bit write mode (2/2) ..................................................................4-6 Lock bit read mode (1/2) ..................................................................4-7 Lock bit read mode (2/2) ..................................................................4-7 GMS34004T/112T/140T (Pin assignment & Package) .....................4-8 EPROM (KHz) mode .........................................................................4-9 EPROM write only mode ..................................................................4-9 GMS34004TK/34112TK/34140TK .............................................................4-10 Mode Define .....................................................................................4-10 Port Define ........................................................................................4-11 Programming Data ...........................................................................4-11 Write/Read Data Conversion ............................................................4-12 Checksum ........................................................................................4-12 Programming Control ......................................................................4-12 Programming DC Specification ........................................................4-12 EPROM read mode(1/2) ...................................................................4-13 EPROM read mode (2/2) ...................................................................4-13 EPROM write mode (1/4) ..................................................................4-14 EPROM write mode (2/4) ..................................................................4-14 EPROM write mode (3/4) ..................................................................4-15 EPROM write mode (4/4) ..................................................................4-15 Lock bit write mode (1/3) ..................................................................4-16 Lock bit write mode (2/3) ..................................................................4-16 Lock bit write mode (3/3) ..................................................................4-16 Lock bit read mode (1/2) ..................................................................4-18 Lock bit read mode (2/2) ..................................................................4-18 INTRODUCTION 1 ARCHITECTURE 2 INSTRUCTION 3 EPROM 4 Chapter 1. Introduction CHAPTER 1. Introduction OUTLINE OF CHARACTERISTICS The GMS340 series are remote control transmitter which uses CMOS technology, and the EPROM version of GMS34XXX series. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS340 series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipments, Toys, Games etc. Characteristics • • • • • • • • • • • • • Program memory : 512bytes for GMS34004T 1,024 bytes for GMS34112T/140T Data memory : 32 ¡¿ 4 bits 43 types of instruction set 3 levels of subroutine nesting 1 bit output port for a large current (REMOUT signal) Operating frequency :300KHz~500KHz at KHz version 2.4MHz~4MHz at MHz version 300KHz~4.2MHz at WIDE version Instruction cycle : f OSC/6 at KHz and WIDE version f OSC/48 at MHz version CMOS process (3.0V or 5.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in capacitor for ceramic oscillation circuit at KHz version Built in a watch dog timer (WDT) Low operating voltage : 2.2~4.5V (at KHz and MHz version) Normal operating voltage: 4.0~5.0V (at WIDE version) Series Program memory Data memory I/O ports Input ports Output ports Package KHz version GMS34004T GMS34112T GMS34140T 512 1,024 ¡ç 32 ¡¿ 4 ¡ç ¡ç - 4 ¡ç 4 6 D0 ~ D5 ¡ç ¡ç ¡ç 10 D0 ~ D9 16DIP 20DIP/SOP/SSOP 24DIP/SOP GMS34004TK GMS34112TK GMS34140TK ¡ç MHz version GMS34004TM GMS34112TM GMS34140TM WIDE version GMS34004TW GMS34112TW GMS34140TW Table 1-1 GMS34XXXT series members 1- 1 Chapter 1. Introduction Block Diagram RESET/Vpp VDD GND 1 24 2 Reset ROM 64word ¡¿ 16page ¡¿8bit 8 10 Program counter Watchdog timer Stack 10 4 4 8 4 MUX Instruction Decoder 4 ALU MUX 4 4 Control Signal 2 RAM 16word x 2page x 4bit X-Reg 16 RAM Word Selector Y-Reg ST 4 ACC 4 23 22 4 D-Latch Pulse Generator 4 OSC1 OSC2 10 R-Latch OSC 7 8 9 K0 ~ K3 4 10 10 4 3 4 5 6 11 12 R0 ~ R3 13 14 15 16 17 18 19 D0 ~ D9 Fig 1-1 Block Diagram (In case of GMS34140T) 1- 2 20 21 REMOUT Chapter 1. Introduction Pin Assignment and terminals Pin Assignment RESET/Vpp 1 16 VDD GND 2 15 OSC1 K0 3 14 OSC2 K1 4 13 REMOUT K2 5 12 K3 6 D0 D1 K0 1 20 R3 K1 2 19 R2 K2 3 18 R1 K3 4 17 R0 D5 D0 5 16 GND 11 D4 D1 6 15 RESET/Vpp 7 10 D3 D2 7 14 VDD 8 9 D2 D3 8 13 OSC1 D4 9 12 OSC2 D5 10 11 REMOUT Fig 1-2 GMS34004T Pin Assignment (16PDIP) Fig 1-3 GMS34112T Pin Assignment (20DIP/SOP) GND 1 20 RESET/Vpp R0 2 19 VDD RESET/Vpp 1 24 VDD GND 2 23 R1 3 18 OSC1 OSC1 R0 3 22 R2 4 OSC2 17 OSC2 R1 4 21 R3 REMOUT 5 16 REMOUT R2 5 20 D7 K0 6 15 D5 R3 6 19 D6 K1 7 14 D4 K0 7 18 D5 K2 8 13 D3 K1 8 17 D4 K3 9 12 D2 K2 9 16 D3 D0 10 11 D1 K3 10 15 D2 D0 11 14 D1 D8 12 13 D9 Fig 1-4 GMS34112T Pin Assignment (20SSOP only) Fig 1-5 GMS34140T Pin Assignment (24DIP/SOP) 1- 3 Chapter 1. Introduction 0.135MAX 0.125MIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 0.300BSC 0.260MAX 0.240MIN 0.140MAX 0.120MIN 0.785MAX 0.745MIN 0.015MIN 0.065MAX 0.050MIN 0.100BSC ¡æ 0.022MAX 0.015MIN 0.014MAX ¡ç0.008MIN ¡æ ¡ç 0~15¡Ç 0.040MAX Outline (Unit:Inch) 0.020MIN Fig 1-6 16PDIP Pin Dimension 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.3TYP 0.270MAX 0.250MIN 0.1TYP 0.065MAX 0.022MAX 0.055MIN 0.015MIN 0.135MAX 0.125MIN 0.015MIN 0.984MAX 0.968MIN 0.170MAX 0.170MAX Pin Dimension ¡æ Outline (Unit : Inch) Fig 1-7 20PDIP Pin Dimension 1- 4 0.012MAX ¡ç0.008MIN ¡æ ¡ç 0~15¡Ç 20 19 1 8 17 1 2 3 4 16 15 14 13 12 11 5 6 7 8 9 10 0.093MIN 0.104MAX Chapter 1. Introduction 0.419MAX 0.398MIN 0.299MAX 0.292MIN 0.5118MAX 0.4961MIN ¡æ ¡ç 0.0118MAX 0.004MIN 0.020MAX 0.014MIN 0.042MAX ¡æ ¡ç0.016MIN ¡æ ¡ç 0.032MAX 0.0125MAX 0.0091MIN 0.05TYP Outline (Unit : Inch) Fig 1-8 20SOP Pin Dimension 19 1 8 17 1 2 3 15 14 13 12 11 5 6 7 8 9 10 0.066MAX 0.057MIN 4 16 0.244MAX 0.234MIN 0.157MAX 0.150MIN 0.344MAX 0.337MIN ¡æ ¡ç 0.010MAX 0.007MIN 20 0-8¢ª ¡é 0.010MAX 0.004MIN ¡è 0.012MAX 0.008MIN 0.025BSC 0.022MIN Outline (Unit : Inch) Fig 1-9 20SSOP Pin Dimension 1- 5 0.170MAX Chapter 1. Introduction 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.3TYP 0.270MAX 0.250MIN 0.135MAX 0.125MIN 0.015MIN 1.255MAX 1.245MIN 0.1TYP 0.065MAX 0.022MAX 0.055MIN 0.015MIN ¡æ 0.012MAX ¡ç0.008MIN ¡æ ¡ç 0~15¢ª Outline (Unit : Inch) 0.104MAX 0.093MIN Fig 1-10 24Skinny DIP Pin Dimension 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.419MAX 0.398MIN 0.299MAX 0.292MIN 0.616MAX 0.595MIN ¡æ ¡ç 0.05TYP 0.020MAX 0.018MAX 0.004MIN 0.0125MAX 0.0091MIN 0.014MIN Outline (Unit : Inch) Fig 1-11 24SOP Pin Dimension 1- 6 ¡æ 0.042MAX ¡ç0.016MIN Chapter 1. Introduction Pin Description and Circuit Pin Description Pin I/O Function VDD - Connected to 2.2~4.5V power supply at KHz and MHz version or 4.0 ~ 5.5V power supply at WIDE version. GND - Connected to 0V power supply. RESET Input Used to input a manual reset. When the pin goes "L", the D-output ports and REMOUT-output port are initialized to "L", and ROM address is set to address 0 on page 0. For programming, this pin receives 12.5V programming voltage. K0~K3 Input 4-bit input port. STOP mode is released by "L" input of each pin. D0~D9 Output R0~R3 I/O REMOUT Output OSC1 Input OSC2 Output The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. High current output port. The output is in the form of C-MOS. The state of large current on is "H". Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at KHz version. A feedback resistor is connected between this pin and OSC2. Connect a resonator between this pin and OSC1. 1- 7 Chapter 1. Introduction I/O circuit types and options Pin I/O circuit I/O Note ¡æ Reset/Vpp ¡ç I ¡æ Hysteresis Input Type. Built in pull-up-resistor, Typical 800§Ú ¡ç ¡ç R0~R3 pull-up ¡æ I/O ¡ç ¡æ ¡æ K0~K3 pull-up ¡æ I ¡ç D0~D9 O ¡ç ¡æ REMOUT CMOS output. "H" output at reset. Built in MOS Tr for pull-up about 120§Ú. O ¡ç 1- 8 Built in MOS Tr for pull-up About 120§Ú. Open drain output. "L" output at reset. CMOS output. "L" output at reset. High current output source. Chapter 1. Introduction Pin I/O circuit I/O Note Built in feedback-resistor about 1§Û STOP OSC2 O ¡æ OSC1 ¡ç Rd ¡æ ¡ç OSC1 I ¡è C1 ¡è C2 Rf OSC2 Built in damping-resistor Rd = 4§Ú [No resistor in MHz operation] Built in resonance Capacitor at KHz version C1=C2 = 100pF ¡¾15% [C1,C2 are not available for MHz and WIDE version] Frequency Resonator Maker Part Name Load Capacitor 320KHz CQ ZTB320D C1=C2=Open 500KHz CQ ZTB500E C1=C2=Open CQ recommend 430KHz~500KHz resonator 3.43MHz CQ ZTA3.43MG C1=C2=30pF 3.52MHz TDK FCR3.52M5 C1=C2=33pF CQ ZTA3.64MG C1=C2=30pF TDK FCR3.64M5 C1=C2=33pF CQ ZTA3.84MG C1=C2=30pF TDK FCR3.84M5 C1=C2=33pF CQ ZTA4.00MG C1=C2=30pF 3.64MHz 3.84MHz 4.00MHz 1- 9 Chapter 1. Introduction Electrical Characteristics Absolute maximum ratings (Ta = 25¡É) Symbol Max. rating Unit Supply Voltage VDD -0.3 ~ 7.0 V Programming Voltage VPP -0.3 ~ 13.5 V Power dissipation PD 700 * mW Tstg -55 ~ 125 ¡É VIN -0.3 ~ VDD+0.3 V VOUT -0.3 ~ VDD+0.3 V Parameter Storage temperature range Input voltage Output voltage * Thermal derating above 25¡É : 6mW per degree ¡É rise in temperature. Recommended operation condition Parameter Supply Voltage Operating temperature Symbol VDD Condition Rating 300 ~ 500KHz 2.2 ~ 4.5 2.4 ~ 4MHz 2.2 ~ 4.5 300KHz ~ 4.2MHz 4.0 ~ 5.5 - -20 ~ +70 Topr 1 - 10 Unit V ¡É Chapter 1. Introduction Electrical characteristics for low voltage products (Ta=25¡É, VDD=3V) Limits Parameter Unit Symbol Min. Typ. Max. Condition Input H current IIH - - 1 uA VI=VDD RESET input L current IIL2 -2 -7.5 -16 uA VI=GND K, R input L current IIL1 -9 -25 -50 uA VI=GND, Output off, Pull-Up resistor provided. K, R input H voltage VIH1 2.1 - - V - K, R input L voltage VIL1 - - 0.9 V - RESET input H voltage VIH2 2.25 - - V - RESET input L voltage VIL2 - - 0.75 V V D. R output L voltage VOL2 - 0.15 0.4 V IOL=1mA REMOUT output L voltage VOL1 - 0.15 0.4 V IOL=100uA REMOUT output H voltage VOH1 2.1 2.5 - V IOH=-8mA OSC2 output L voltage VOL3 - 0.4 0.9 V IOL=70uA OSC2 output H voltage VOH3 2.1 2.5 - V IOH=70uA IOL - - 1 uA V0UT=VDD, Output off Current on STOP mode ISTOP - - 1 uA At STOP mode Operating supply current 1 IDD1 * - 0.3 4.0 mA fOSC=455KHz Operating supply current 2 IDD2 * - 0.5 4.0 mA fOSC=4MHz fOSC/6 fOSC 300 - 500 KHz KHz version fOSC/48 fOSC 2.4 - 4 MHz MHz version D, R output leakage current System clock frequency * IDD1, IDD2, is measured at RESET mode. 1 - 11 Chapter 1. Introduction Electrical characteristics (Ta=25¡É, VDD=5V) Limits Parameter Unit Condition Symb ol Min. Typ. Max. Input H current IIH - - 5 uA VI=VDD RESET input L current IIL2 -2 - -20 uA VI=GND K, R input L current IIL1 -9 - -150 uA VI=GND, Output off, Pull-Up resistor provided. K, R input H voltage VIH1 0.7*VDD - - V - K, R input L voltage VIL1 - - 0.3*VDD V - RESET input H voltage VIH2 0.75*VDD - - V - RESET input L voltage VIL2 - - 0.25*VDD V V D. R output L voltage VOL2 - - 0.4 V IOL=2mA REMOUT output L voltage VOL1 - - 0.4 V IOL=100uA REMOUT output H voltage VOH1 VDD-1.0 - - V IOH=-8mA OSC2 output L voltage VOL3 - - 0.9 V IOL=70uA OSC2 output H voltage VOH3 VDD-1.0 - - V IOH=-70uA IOL - - 5 uA V0UT=VDD, Output off Current on STOP mode ISTOP - - 10 uA At STOP mode Operating supply current IDD - - 10 mA At RESET mode System clock frequency fOSC 0.3 - 4.2 MHz WIDE version D, R output leakage current fOSC/6 1 - 12 INTRODUCTION 1 ARCHITECTURE 2 INSTRUCTION 3 EPROM 4 Chapter 2. Architecture CHAPTER 2. Architecture BLOCK DESCRIPTION Program Memory (EPROM) The GMS34XXXT series can incorporate maximum 1,024 words (64 words¡¿16 pages¡¿8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below. Program capacity (pages) 01 8 2 3 4 5 6 7 Page 0 Page 1 Page 2 Page 15 63 0 1 2 15 A0~A5 A6~A9 Program counter (PC) Page address register (PA) 6 4 4 Stack register (Level "1") (Level "2") (SR) (PSR) (Level "3") Fig 2-1 Configuration of Program Memory 2- 1 Page buffer (PB) Chapter 2. Architecture EPROM Address Register The following registers are used to address the EPROM. • Page address register (PA) : Holds EPROM's page number (0~Fh) to be addressed. • Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL). • Program counter (PC) : Available for addressing word on each page. • Stack register (SR) : Stores returned-word address in the subroutine call mode. (1) Page address register and page buffer register : Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL, because instruction code is of eight bits so that page and word can not be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) Program counter : This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to "0". Then the program counter specifies the next EPROM address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1. (3) Stack register : This stack register provides two stages each for the program counter (6 bits) and the page address register (4bits) so that subroutine nesting can be made on two levels. 2- 2 Chapter 2. Architecture Data memory (RAM) Up to 32 nibbles (16 words ¡¿ 2pages ¡¿ 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the configuration. D0 D9 R0 R3 REMOUT Output port Data memory page (0~1) 0 1 2 3 Page 0 Page 1 15 4 A0~A3 0 1 Y-register (Y) X-register (X) 4 2 Fig 2-2 Composition of Data Memory X-register (X) X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only used for selecting of D8~D9 with value of Y-register X1=0 X1=1 Y=0 D0 D8 Y=1 D1 D9 Table 2-1 Mapping table between X and Y register 2- 3 Chapter 2. Architecture Y-register (Y) Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies and address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program. Accumulator (ACC) The 4-bit register for holding data and calculation results. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) Operation circuit (ALU) : The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1) (2) Status logic : This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. 2- 4 Chapter 2. Architecture State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequentially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Fetch cycle N Execute cycle N Execute cycle N-1 Fetch cycle N-1 Machine Cycle Machine Cycle Phase¥° Phase¥± Phase¥² Fig. 2-3 Fundamental timing chart 2- 5 Chapter 2. Architecture Clock Generator The GMS34XXXT series has an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Internal capacitors are available at KHz version. Oscillator circuit is able to organize by connecting ceramic resonator to outside. * It is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturer`s resonator matching guide. OSC1 OSC2 OSC1 OSC2 23 23 22 C1 C2 <Circuit 1> Version KHz 22 <Circuit 2> Operating Frequency 300KHz ~ 500KHz Oscillation Circuit Internal capacitor Circuit 2 No Internal capacitor Circuit 1 MHz 2.4MHz ~ 4MHz No Internal capacitor Circuit 1 WIDE 300KHz ~ 4.2MHz No Internal capacitor Circuit 1 2- 6 Chapter 2. Architecture Pulse generator The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program. T T1 PMR REMOUT signal 0 T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/2 1 T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/3 2 T=1/fPUL = 8/fOSC [64/fOSC], T1/T = 1/2 3 T=1/fPUL = 8/fOSC [64/fOSC], T1/T = 1/4 4 T=1/fPUL = 11/fOSC [88/fOSC], T1/T = 4/11 5 No Pulse (same to D0~D9) 6 T=1/fPUL = 12/fOSC [96/fOSC], 7 No pulse (same to D0 ~ D9) T1/T = 1/4 * Default value is "0" * [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version Table 2-2 PMR selection table 2- 7 Chapter 2. Architecture Initial Reset Circuit RESET pin must be down to "L" more than 4 machine cycle by outside capacitor or other for power on reset. The mean of 1 machine cycle is 6/fOSC or 48/fOSC, however, operating voltage must be in recommended operating conditions, and clock oscillating stability. * It is required to adjust C value depending on rising time of power supply. (Example shows the case of rising time shorter than 10ms.) 1 RESET 0.1uF Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 6¡¿2 13/fOSC (108.026ms at fOSC=455KHz.) 8¡¿6¡¿213/fOSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR) or / and REMOUT port HIGH(Y-reg=8, So instruction execution). * It is constantly reset in STOP mode. When STOP is released, counting is restarted. (Refer to 2-9 STOP function>) fOSC/6 or fOSC/48 Binary counter (14 steps) RESET (edge-trigger) Reset by instruction REMOUT output 2- 8 CPU reset Chapter 2. Architecture STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D8~D9 output and REMOUT output are "L". 3. Part other than WDT, D8~D9 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D7 output and REMOUT output is return to state of before stop mode is achieved. 2. After 1,024¡¿8 enable clocks for stable oscillating, First instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. Port Operation Value of X-reg Value of X-reg Operation 0 or 1 0~7 0 or 1 8 REMOUT port repeats "H" and "L" in pulse frequency. (When PMR = 5, it is fixed at "H") S0 : REMOUT(PMR) ¡ç 1 R0 : REMOUT(PMR) ¡ç 0 0 or 1 9 S0 : D0 ~ D9 ¡ç 1 (High-Z) R0 : D0 ~ D9 ¡ç 0 0 or 1 A~D S0 : R(Y-Ah) ¡ç 1 R0 : R(Y-Ah) ¡ç 0 0 or 1 E S0 : R0 ~ R3 ¡ç 1 R0 : R0 ~ R3 ¡ç 0 0 or 1 F S0 : D0 ~ D9 ¡ç 1, R0 ~ R3 ¡ç 1 R0 : D0 ~ D9 ¡ç 0, R0 ~ R3 ¡ç 0 2 or 3 0 S0 : D(8) ¡ç 1 R0 : D(8) ¡ç 0 2 or 3 1 S0 : D(9) ¡ç 1 R0 : D(9) ¡ç 0 S0 : D(Y) ¡ç 1, 2- 9 R0 : D(Y) ¡ç 0 INTRODUCTION 1 ARCHITECTURE 2 INSTRUCTION 3 EPROM 4 Chapter 3. Instruction CHAPTER 3. Instruction Instruction Table The GMS34XXXT series provides the following 43 basic instructions. Category Mnemonic Function ST*1 LAY A ¡ç Y S LYA Y ¡ç A S 3 LAZ A ¡ç 0 S 4 LMA M(X,Y) ¡ç A S 5 LMAIY M(X,Y) ¡ç A, Y ¡ç Y+1 S LYM Y ¡ç M(X,Y) S 7 LAM A ¡ç M(X,Y) S 8 XMA A ¡ê M(X,Y) S 9 LYI i Y ¡ç i S M(X,Y) ¡ç i, Y ¡ç Y+1 S X ¡ç n S SEM n M(n) ¡ç 1 S REM n M(n) ¡ç 0 S 1 2 6 10 Register to Register RAM to Register Immediate 11 LXI n 12 13 LMIIY i RAM Bit Manipulation 14 TM n TEST M(n) = 1 E 15 BR a if ST = 1 then Branch S CAL a if ST = 1 then Subroutine call S Return from Subroutine S PB ¡ç i S 16 17 ROM Address RTN 18 LPBI i 19 AM A ¡ç A + M(X,Y) C 20 SM A ¡ç M(X,Y) - A B 21 IM A ¡ç M(X,Y) + 1 C DM A ¡ç M(X,Y) - 1 B 22 Arithmetic 23 IA A ¡ç A + 1 S 24 IY Y ¡ç Y + 1 C 25 DA A ¡ç A - 1 B 3- 1 Chapter 3. Instruction Category Mnemonic Function ST*1 Y ¡ç Y - 1 B EORM A ¡ç A + M (X,Y) S 28 NEGA A ¡ç A + 1 Z 29 ALEM TEST A ¡Â M(X,Y) E 30 ALEI i TEST A ¡Â i E 31 MNEZ TEST M(X,Y) ¡Á 0 N YNEA TEST Y ¡Á A N 33 YNEI i TEST Y ¡Á i N 34 KNEZ TEST K ¡Á 0 N 35 RNEZ TEST R ¡Á 0 N 36 LAK A ¡ç K S LAR A ¡ç R S SO Output(Y) ¡ç 1*2 S 39 RO Output(Y) ¡ç 0*2 S 40 WDTR Watch Dog Timer Reset S STOP Stop operation S 26 27 32 37 38 DY Arithmetic Comparison Input / Output 41 Control 42 LPY PMR ¡ç Y S 43 NOP No operation S Note) i = 0~f, n = 0~3, a = 6bit PC Address *1 Column ST indicates conditions for changing status. Symbols have the following meanings S : On executing an instruction, status is unconditionally set. C : Status is only set when carry or borrow has occurred in operation. B : Status is only set when borrow has not occurred in operation. E : Status is only set when equality is found in comparison. N : Status is only set when equality is not found in comparison. Z : Status is only set when the result is zero. *2 Operation is settled by a value of Y-register. 3- 2 INTRODUCTION 1 ARCHITECTURE 2 INSTRUCTION 3 EPROM 4 Chapter 4. EPROM CHAPTER 4. EPROM GMS34004TK / 34112TK / 34140TK Mode define Item Device operation User mode Exact User pgm EPROM read mode EPROM Program mode Lock bit Program mode Address in, Data out 1Byte PGM Write Address in, Data in 2Byte PGM Write Address in, Data in Program verify Address in, Data out Lock bit Write Lock bit write(set D5 to 1) Lock bit Read Lock bit out 4- 1 Mode setting RESETB = 0 ~ 3V RESETB =12.5V K3~0=0110 Vcc=3V Vcc=6.0V K3~0=0110 RESETB =12.5V K3~0=0111 Vcc=6.0V - RESETB =12.5V K3~0=0100 K3~0=0101 Vcc=6.0V, Lock bit is D5. (Default : unlock) Chapter 4. EPROM Port define Port Name User Mode EPROM Mode VDD 3.0V 6.0V RESETB Reset (0, 3.0V) Vpp (0, 12.5V) OSC1 Clock input Clock input K0 K0(Input) K1 K1(Input) K2 K2(Input) K3 K3(Input) D0 D0(Output) A0 A5 Da0 Da4 D1 D1(Output) A1 A6 Da1 Da5 D2 D2(Output) A2 A7 Da2 Da6 D3 D3(Output) A3 A8 Da3 Da7 D4 D4(Output) A4 A9 - - D5 D5(Output) Lock bit output GND 0V Read / Write Control Address / Data Control NMOS open drain I/O in EPROM mode * Undefined ports in this table are N.C (No Connection) Programming data Device Name ROM Size Blank data Lock bit Device address (HEX) File address GMS34004TK 512bytes FF Yes 0000 ~ 01FF 0000 ~ 01FF GMS34112TK 1,024bytes FF Yes 0000 ~ 03FF 0000 ~ 03FF GMS34140TK 1,024bytes FF Yes 0000 ~ 03FF 0000 ~ 03FF - If lock bit is set, the EPROM of the device can not be read, because output is always FF. - Input file : Intel Hexa format ( *.RHX ) 4- 2 Chapter 4. EPROM Write / Read data conversion - You must change MSB ~ LSB ¡ê LSB ~ MSB. - Example File / buffer data Hex Device (D3 ~ D0) Binary (MSB~LSB) Hex Binary (MSB~LSB) 34 0011 0100 27 0010 0111 B1 1011 0001 Write 2C 0010 1100 E4 1110 0100 8D 1000 1101 Read Checksum - It is calculated from the Buffer of the programmer. - Address range is the same as device address. - Calculate method is the same as normal EPROM devices (ex:27C128, 256 etc) Programming control - OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state. - K ports control the internal state of the OTP device(ex: Read, Write...). - D5~D0 ports are NMOS open drain I/O in EPROM mode. It must be pulled up by resistors (about 4.7~ 47K ohm). - The frequency rate of the OSC1 clock is 10KHz ~ 500KHz. You can hold OSC1 HIGH or LOW state when you need. Programming DC specification Item Range VCC 0 ~ 6.0V ¡¾ 0.25V RESETB 0 ~ 12.5V ¡¾ 0.5V K-port 0 ~ 0.2VCC(Low) D-port 0.8VCC ~ VCC (High) 4- 3 Chapter 4. EPROM EPROM read mode (1/2) For device verify or read. If you set Lock bit, output data is always FF. 14.5clocks ¨ç ¨è 2us at 500KHz ¨ô ¨õ OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 6V 0V 12.5V 0110 D4 ~ D0 AH 0000 1101 AL OH OL AH 0000 1101 AL OH Addr. 0 1 AH : High Address (A9~5) Input Latch AL : Low Address (A4~0) Input Latch OL AH 0000 1101 AL OH Addr. 1 2 OL Addr. 2 3 OH : High Data (D7~4) Output OL : Low Data (D3~0) Output * Note : 1. AH, AL, DH, DL Inputs released at 100~200nS after OSC rising edge and width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ). EPROM read mode (2/2) START ¨ç Reset (Set EPROM read mode) Address=First address ¨è Set address ¨é Read data Address ++ Address > Last address RESETB=0V VCC=0V END 4- 4 AH 0000 1101 AL OH Addr. 3 OL Chapter 4. EPROM EPROM write mode (1/2) 14.5clocks ¨ç ¨è 2us at 500KHz ¨ô ¨õ OSC CK1 CK2 CK3 VCC RESETB 6V 0V 9.5V 12.5V PGM Write ( 0110 ) K3 ~ K0 0000 D4 ~ D0 AH AL 1000 DH 1110 1101 DL 10times Repeat 12us X 10 = 120us 1 2 AH : High bit Address Input Latch AL : Low bit Address Input Latch 0000 OH OL AH Verify 3 1000 AL DH DL Next Write 4 DH : High bit Data Input Latch DL : Low bit Data Input Latch OH : High bit Data Output OL : Low bit Data Output * Note : 1. AH, AL, DH, DL Inputs are released at 100~200nS after OSC rising edge and width is 1OSC cycle ( if OSC is 500KHz, width is 2uS ). EPROM write mode (2/2) START ¨é EPROM write (Write one more time) ¨ç Reset (Set EPROM write mode) Address ++ Address=First address No ¨è Address > Last address Yes Set address & data RESETB=0V VCC=0V Count=0 ¨é EPROM write Repeat until near 100uS. When 500KHz OSC1, repeat 10 times (12uS*10=120uS) EPROM read mode Verify all Fail Pass Device fail Device OK Count ++ ¨ê Verify Pass RESETB=0V VCC=0V Yes END Fail No Count=25? 4- 5 Chapter 4. EPROM Lock bit write mode (1/2) 14.5clocks ¨ç ¨è 2us at 500KHz ¨ô ¨õ OSC CK1 CK2 CK3 VCC RESETB K3 ~ K0 6V 0V 12.5V Lock Write ( 0100 ) 0000 1110 10 times Repeat 12us X 10 = 120us Lock bit write 1 2 3 Lock bit write mode (2/2) START ¨ç Reset (Set Lock bit write mode) ¨è Wait cycle Count=0 ¨é Write cycle *1 Count++ No Count=10? Yes RESETB=0V VCC=0V END 4- 6 *1 Repeat until near 100uS. When 500KHz OSC1, repeat 10times (12uS * 10 = 120uS) Chapter 4. EPROM Lock bit read mode (1/2) 14.5clocks ¨ç ¨è 2us at 500KHz ¨ô ¨õ OSC1 VCC 6V 0V 12.5V Lock Read ( 0101 ) Lock bit output 1 2 Lock bit read mode (2/2) START ¨ç Reset (Set Lock bit read mode) ¨è Read Lock bit (D5) RESETB=0V VCC=0V END 4- 7 Chapter 4. EPROM GMS34004T/112T/140T (Pin assignment & Package) RESETB 1 GND 2 16 VDD - Width 300mil - Pin to pin 100mil K0 3 14 - K1 4 13 - K2 5 12 D5 K3 6 11 D4 D0 7 10 D3 D1 8 9 K0 1 20 - K1 2 19 - K2 3 18 - K3 4 17 - D0 5 16 GND D1 6 15 RESETB D2 7 14 VDD D3 8 13 OSC1 D4 9 12 - D5 10 11 - RESETB 1 GND 2 D2 20DIP (Standard TTL DIP Size) - Width 300mil - Pin to pin 100mil 24 VDD 20SOP (Standard TTL SOP Size) 24DIP (Skinny DIP Size) 23 OSC1 - 3 22 - - 4 21 - - 5 20 - - 6 19 - K0 7 18 D5 K1 8 17 D4 K2 9 16 D3 K3 10 15 D2 D0 11 14 D1 - 12 16DIP (Standard TTL DIP Size) 15 OSC1 - Width 300mil - Pin to pin 100mil 24SOP (Standard SOP Size) 13 - 4- 8 Chapter 4. EPROM EPROM(KHz) mode EPROM write only mode 14.5clocks ¨ç ¨è 2us at 500KHz ¨ô ¨õ OSC CK1 CK2 CK3 VCC 6V RESETB 0V K3 ~ K0 D4 ~ D0 12.5V PGM Write ( 0110 ) 0000 1000 AH DL AL DH 1110 AH 10times Repeat 12us X 10 = 120us 5times Repeat EPROM write 4- 9 0000 AL 1000 DH DL Next Write 1110 Chapter 4. EPROM GMS34004TM / 34112TM / 34140TM Mode define Item Device operation User mode Execute User pgm EPROM read mode EPROM Program mode Lock bit Program mode Address in, Data out 1Byte PGM Write Address in, Data in 2Byte PGM Write Address in, Data in Program verify Address in, Data out Lock bit Write Lock bit write(set D5 to 1) Lock bit Read Lock bit out 4 - 10 Mode setting RESETB = 0 ~ 3V RESETB =12.5V K3~0=0010 Vcc=3V Vcc=6.0V K3~0=0110 RESETB =12.5V K3~0=0111 Vcc=6.0V - RESETB =12.5V K3~0=0100 K3~0=0101 Vcc=6.0V, Lock bit is D5. (Default : unlock) Chapter 4. EPROM Port define Port Name User Mode EPROM Mode VDD 3.0V 6.0V RESETB Reset (0, 3.0V) Vpp (0, 12.5V) OSC1 Clock input Clock input K0 K0(Input) K1 K1(Input) K2 K2(Input) K3 K3(Input) D0 D0(Output) A0 A5 Da0 Da4 D1 D1(Output) A1 A6 Da1 Da5 D2 D2(Output) A2 A7 Da2 Da6 D3 D3(Output) A3 A8 Da3 Da7 D4 D4(Output) A4 A9 - - D5 D5(Output) Lock bit output GND 0V Read / Write Control Address / Data Control NMOS open drain I/O in EPROM mode * Undefined ports in this table are N.C (No Connection) Programming data Device Name ROM Size Blank data Lock bit Device address (HEX) File address GMS34004TK 512bytes FF Yes 0000 ~ 01FF 0000 ~ 01FF GMS34112TK 1,024bytes FF Yes 0000 ~ 03FF 0000 ~ 03FF GMS34140TK 1,024bytes FF Yes 0000 ~ 03FF 0000 ~ 03FF - If lock bit is set, the EPROM of the device can not be read, because output is always FF. - Input file : Intel Hexa format ( *.RHX ) 4 - 11 Chapter 4. EPROM Write / Read data conversion - You must change MSB ~ LSB ¡ê LSB ~ MSB. - Example File / buffer data Hex Device (D3 ~ D0) Binary (MSB~LSB) Hex Binary (MSB~LSB) 34 0011 0100 27 0010 0111 B1 1011 0001 Write 2C 0010 1100 E4 1110 0100 8D 1000 1101 Read Checksum - It is calculated from the Buffer of the programmer. - Address range is the same as device address. - Calculate mathod is the same as normal EPROM devices (ex:27C128, 256 etc) Programming control - OSC1 & RESETB control OTP device, so you must count OSC1 clocks in every state. - K ports control the internal state of the OTP device(ex: Read, Write...). - D5~D0 ports are NMOS open drain I/O in EPROM mode. It must be pulled up by resistors (about 4.7~ 47K ohm). - The frequency rate of the OSC1 clock is 10KHz ~ 500KHz. You can hold OSC1 HIGH or LOW state when you need. Programming DC specification Item Range VCC 0 ~ 6.0V ¡¾ 0.25V RESETB 0 ~ 12.5V ¡¾ 0.5V K-port 0 ~ 0.2VCC(Low) D-port 0.8VCC ~ VCC (High) 4 - 12 Chapter 4. EPROM EPROM read mode (1/2) For device verify or read. If you set Lock bit, output data is all 'FF’ 12Clock 8Clock OSC1 Address setting 1 VCC RESETB K3 ~ K0 Data read 2 3 Data Strobe point 5Clock Data Strobe point 5Clock 6V 0V 12.5V ROM Dump Mode ( 0010 ) D4 ~ D0 A9~A5 D5 A4~A0 D7~D4 D3~D0 Port Operation K Port Latch High bit Address Latch Low bit Address Latch Sense AMP. Operation Repeat EPROM read mode (2/2) START ¨ç Reset (Set EPROM read mode) Address=First address ¨è Set address ¨é Read data Address ++ Address > Last address RESETB=0V VCC=0V END 4 - 13 High bit Instruction Output Low bit Instruction Output Chapter 4. EPROM EPROM write mode (1/4) 12Clock 8Clock OSC1 1 2 6V VCC RESETB K3 ~ K0 2 12.5V 0V PGM Write ( 0110 (1B)) 0000 D4 ~ D0 A9~A5 K Port Latch High bit Address Latch A4~A0 Low bit Address Latch First Address Input 1000 D7~D4 High bit Instruction Latch D3~D0 Low bit Instruction Latch First Data Input EPROM write mode (2/4) OSC1 VCC RESETB K3 ~ K0 3 3 4 1110 1110 1101 6V 12.5V D4 ~ D0 Verify EPROM write time 4 - 14 Chapter 4. EPROM EPROM write mode (3/4) OSC1 4 2 Data Strobe point 5Clock VCC 2 Data Strobe point 5Clock 6V Verify RESETB 12.5V K3 ~ K0 1101 D4 ~ D0 D7~D4 High bit Instruction Output 0000 D3~D0 Low bit Instruction Output A9~A5 High bit Address Latch 1000 A4~A0 D7~D4 Low bit Address Latch D3~D0 High bit Instruction Latch Next Address Input Low bit Instruction Latch Next Data Input EPROM write mode (4/4) START ¨é EPROM write (Write one more time) ¨ç Reset (Set EPROM write mode) Address ++ Address=First address No ¨è Address > Last address Yes Set address & data RESETB=0V VCC=0V Count=0 ¨é EPROM write Repeat until near 100uS. When 4MHz OSC1, repeat 10 times (12uS*10=120uS) EPROM read mode Verify all Fail Pass Device fail Device OK Count ++ ¨ê Verify Pass RESETB=0V VCC=0V Yes END Fail No Count=25? 4 - 15 Chapter 4. EPROM Lock bit write mode (1/3) 12Clock 8Clock OSC1 1 VCC RESETB K3 ~ K0 2 2 0000 0000 6V 0V 12.5V EPROM Mode Lock Write ( 0100 ) K Port Latch Lock bit write mode (2/3) OSC1 3 VCC RESETB K3 ~ K0 4 6V 12.5V 1110 1100 Write cycle Repeat 2 times Repeat 10 times Lock bit Write 4 - 16 Chapter 4. EPROM Lock bit write mode (3/3) START ¨ç Reset (Set Lock bit write mode) ¨è Wait cycle Count=0 ¨é *1 Repeat until near 100uS. When 4MHz OSC1, repeat 10 times (12uS * 10 = 120uS) Write cycle *1 ¨ê Delay cycle (Repeat 2 times) Count++ No Count=10 Yes RESETB=0V VCC=0V END 4 - 17 Chapter 4. EPROM Lock bit read mode (1/2) 12Clock 8Clock OSC1 1 2 3 You can strobe at any time from here VCC RESETB K3 ~ K0 6V 0V 12.5V Lock Read Mode ( 0101 ) 1101 D5 Lock bit output K Port Latch Lock bit read mode (2/2) START ¨ç Reset (Set Lock bit read mode) ¨è ¨é Wait cycle Read Lock bit (D5) RESETB=0V VCC=0V END 4 - 18 1101