ON NCP1028 High-voltage switcher for medium power offline smps featuring low standby power Datasheet

NCP1028
High-Voltage Switcher
for Medium Power Offline
SMPS Featuring Low
Standby Power
The NCP1028 offers a new solution targeting output power levels
from a few watts up to 15 W in a universal mains flyback application.
Our proprietary high−voltage technology lets us include a power
MOSFET together with a startup current source, all directly
connected to the bulk capacitor. To prevent lethal runaway in low
input voltage conditions, an adjustable brown−out circuitry blocks
the activity until sufficient input level is reached.
Current−mode operation together with an adjustable ramp
compensation offers superior performance in universal mains
applications. Furthermore, an Over Power Protection pin brings the
ability to precisely compensate all internal delays in high input voltage
conditions and optimize the maximum output current capability.
Protection wise, a timer detects an overload or a short−circuit and
stops all operations, ensuring a safe auto−recovery, low duty cycle burst
operation.
Finally, a great RDS(on) figure makes the circuit an excellent choice
for standby/auxiliary offline power supplies or applications requiring
higher output power levels.
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MARKING
DIAGRAM
8−LEAD PDIP
P SUFFIX
CASE 626A
xxx
A
WL
YY
WW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Built−in 700 V MOSFET with Typical RDS(on) of 5.8 W, TJ = 25°C
Current−Mode Fixed Frequency Operation: 65 kHz and 100 kHz
Fixed Peak Current of 800 mA
Skip−Cycle Operation at Low Peak Currents
Internal Current Source for Clean and Lossless Startup Sequence
Auto−Recovery Output Short Circuit Protection with Timer−Based
Detection
Programmable Brown−Out Input for Low Input Voltage Detection
Programmable Over Power Protection
Input to Permanently Latchoff the Part
Internal Frequency Jittering for Improved EMI Signature
Extended Duty Cycle Operation to 80% Typical
No−Load Input Standby Power of 85 mW @ 265 Vac
500 mW Loaded, Input Power of 715 mW @ 230 Vac
These Devices are Pb−Free and are RoHS Compliant*
Typical Applications
• Medium Power AC−DC Adapters for Chargers
• Auxiliary/Standby Power Supplies for ATX and TVS Power Supplies
Reference
230 VAC
90−265 VAC
NCP1028 − 5.8 W
25 W*
15 W*
P1028Pxxx
AWL
YYWWG
= 65 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VCC
GND
Ramp Comp.
OPP
Brown−Out
FB
Drain
(Top View)
ORDERING INFORMATION
Device
Package
Shipping*
NCP1028P065G
PDIP−8
(Pb−Free)
50 Units / Rail
NCP1028P100G
PDIP−8
(Pb−Free)
50 Units / Rail
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
*Typical values, open−frame, 65 kHz version, RqJA < 75°C/W, TA = 50°C.
**For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 3
1
Publication Order Number:
NCP1028/D
NCP1028
Vout
+
OPP*
NCP1028
+
85−265 VAC
BO
1
8
2
7
3
+
4
+
5
GND
Ramp
Comp.*
*Optional component
Figure 1. Typical Application
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
1
VCC
Powers the Internal
Circuitry
2
Ramp Comp.
Ramp Compensation
in CCM
3
Brown−Out
Brown−Out and
Latchoff Input
4
FB
Feedback Signal Input
5
Drain
Drain Connection
−
−
−
7
OPP
Over Power Protection
8
GND
The IC Ground
Description
This pin is connected to an external capacitor of typically 22 mF.
To extend the duty cycle operation in Continuous Conduction Mode (CCM),
pin 3 offers the ability to inject ramp compensation in the controller. If unused,
short this pin to VCC.
By monitoring the bulk level via a resistive network, the circuit protects itself
from low mains conditions. If an external event brings this pin above 4.0 V,
the part fully latches off.
By connecting an optocoupler to this pin, the peak current setpoint is adjusted
accordingly to the output power demand.
The internal drain power switch circuit connection.
This unconnected pin ensures adequate creepage distance.
Driving this pin reduces the power supply capability in high line conditions. If
no Over Power Protection is needed, short this pin to ground.
−
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2
NCP1028
IC1
VCC
GND
Vclamp
20 ms RC
+
+
Vlatch
UVLOs
4 V rst
VDD
VCC
Mngt
Fault
S
LEB
Q
Q
R
VCC < 4 V
Reset
IBO
BO
+
-
Timer
65 kHz or
100 kHz
CLOCK
Ip Flag
OPP
+
VBO
Jittering
Vcc
S
V
Icomp dd
Q
Q
R
Ramp
Comp.
+
25%
of lp
+
-
Vdd
Skip
- +
RFB
Soft−Start
UVLO
Drain
FB
+
-
Max Ip Selection
Over Power
Protection Input
Ip Flag
Ramp Compensation
Figure 2. Internal Block Diagram
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NCP1028
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
−0.3 to 10
V
Drain Voltage
BVdss
−0.3 to 700
V
Drain Current Peak During Transformer Saturation
IDS(pk)
1.8
A
Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp
I_VCC
15
mA
Thermal Resistance, Junction−to−Air – PDIP7
RqJA
100
°C/W
Power Supply Voltage on all Pins, Except Pin 5 (Drain)
Thermal Resistance, Junction−to−Air – PDIP7 with 1.0 cm@ of 35 m Copper Area
RqJA
75
°C/W
TJMAX
150
°C
Storage Temperature Range
−
−60 to +150
°C
ESD Capability, Human Body Model (HBM) (All Pins Except HV)
−
2.0
kV
ESD Capability, Machine Model (MM)
−
200
V
Maximum Junction Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC JESD22−A114−F.
Machine Model Method 200 V per JEDEC JESD22−A115−A.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC = 8.0 V, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Switcher Starts to Operate
1
VCCON
7.9
8.5
8.9
V
VCC Decreasing Level at which the Switcher Stops Operation
1
VCC(min)
6.7
7.2
7.9
V
Hysteresis between VCCON and VCC(min)
−
VCChyste
−
1.2
−
V
Offset Voltage above VCCON at which the Internal Clamp Activates
1
VCCclamp
140
200
300
mV
VCC Voltage at which the Internal Latch is Reset
1
VCCreset
−
4.0
−
V
1
ICC1
−
1.4
1.9
mA
Power Switch Circuit On−State Resistance
NCP1028 (Id = 100 mA)
TJ = 25°C
TJ = 125°C
5
RDS(on)
Power Switch Circuit and Startup Breakdown Voltage
(ID(off) = 120 mA, TJ = 25°C)
5
SUPPLY SECTION AND VCC MANAGEMENT
Internal IC Consumption, MOSFET Switching at
65 kHz or 100 kHz
POWER SWITCH CIRCUIT
W
−
−
Power Switch and Startup Breakdown Voltage Off−State
Leakage Current
TJ = 25°C (Vds = 700 V)
TJ = 125°C (Vds = 700 V)
BVdss
700
5.8
9.8
7.0
11
−
−
mA
Idss(OFF)
−
−
5
5
Switching Characteristics (RL = 50 W, Vds Set for
Idrain = 0.7 x Ilim)
Turn−on Time (90%−10%)
Turn−off Time (10%−90%)
V
−
−
50
30
−
−
−
−
ns
ns
6.0
8.0
mA
650
900
mA
−
V
35
35
5
5
ton
toff
High−Voltage Current Source, VCC = VCCON – 200 mV
1
IC1
3.5
High−Voltage Current Source, VCC = 0
1
IC2
350
VCC Transition Level for IC1 to IC2 Toggling Point
1
VCCTh
−
1.3
INTERNAL STARTUP CURRENT SOURCE
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NCP1028
ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C,
Max TJ = 150°C, VCC = 8.0 V, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Maximum Internal Current Setpoint, Pin 4 Open, TJ = 25°C,
FSW = 65 kHz (Note 3)
−
Ipeak_27_CS_
65 k
720
800
880
mA
Final Switch Current with a Primary Slope of 200 mA/ms,
FSW = 65 kHz (Note 4)
−
Ipeak_27_SW_
65 k
−
820
−
mA
Maximum Internal Current Setpoint, Pin 4 Open, TJ = 25°C,
FSW = 100 kHz (Note 3)
−
Ipeak_27_CS_
100 k
720
800
880
mA
Final Switch Current with a Primary Slope of 200 mA/ms,
FSW = 100 kHz (Note 4)
−
Ipeak_27_SW_
100 k
−
820
−
mA
Setpoint Decrease for a Pin 7 Injected Current of 40 mA, TJ = 25°C
7
IOPP
−
23
−
%
Voltage Level in Pin 7 at which OPP Starts to Operate
7
IOPPtripV
−
1.5
−
V
Soft−Start Duration
−
TSS
−
1.0
−
ms
Propagation Delay from Current Detection to Drain OFF State
−
Tprop
−
100
−
ns
Leading Edge Blanking Duration
−
TLEB
−
200
−
ns
Oscillation Frequency (Note 5)
65 kHz Version, TJ = 25°C
−
fOSC
58.5
65
71.5
Oscillation Frequency (Note 5)
100 kHz Version, TJ = 25°C
−
90
100
110
Frequency Jittering in Percentage of fOSC
−
fJitter
−
"6.0
−
%
Jittering Swing Frequency
−
fswing
−
300
−
Hz
Maximum Duty Cycle
−
Dmax
74
80
87
%
CURRENT COMPARATOR
INTERNAL OSCILLATOR
kHz
fOSC
kHz
FEEDBACK SECTION
Internal Pullup Resistor
4
Rupp
−
16
−
kW
Ramp Compensation Level on Pin 1 – Rramp = 100 kW
2
Rlevel
−
2.75
−
V
−
Iskip
−
25
−
%
Brown−Out Level
3
VBO
510
570
620
mV
Brown−Out Hysteresis Current, TJ = 25°C (Note 3)
3
IBOhyste
10
11.5
13
mA
Brown−Out Hysteresis Current, TJ = 0°C to 125°C
3
IBOhyste
−
10
−
mA
Fault Validation further to Error Flag Assertion
−
TimerON
40
55
−
ms
OFF Phase in Fault Mode
−
TimerOFF
−
440
−
ms
Latching Voltage on Brown−Out Pin
3
Vlatch
3.15
3.5
3.85
V
Latch Input Integrating Filter Time Constant
3
TdelBOL
−
20
−
ms
Temperature Shutdown
−
TSD
160
−
−
°C
Hysteresis in Shutdown
−
−
−
40
−
°C
SKIP CYCLE GENERATION
Internal Skip Mode Level, in Percentage of Maximum Peak Current
PROTECTIONS
TEMPERATURE MANAGEMENT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. See characterization curves for full temperature span evolution.
4. The final switch current is: Ipeak_2X_CS + Tprop x Vin / Lp, with Vin the input voltage and Lp the primary inductor in a flyback.
5. Oscillator frequency is measured with disabled jittering.
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NCP1028
TYPICAL CHARACTERISTICS
8.9
8.8
8.7
VCCON (V)
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
−20
0
20
40
60
80
100
120
0
20
140
TEMPERATURE (°C)
7.9
7.8
0.24
7.7
7.6
0.22
7.5
7.4
VCCClamp (V)
VCCMIN (V)
Figure 3.
7.3
7.2
7.1
7.0
6.9
6.8
6.7
−20
0.20
0.18
0.16
0
20
40
60
80
100
120
0.14
140
−20
TEMPERATURE (°C)
40
60
80
100
TEMPERATURE (°C)
Figure 4.
120
140
120
140
Figure 5.
1.8
900
850
800
750
700
IC2 (mA)
ICC1 (mA)
1.6
1.4
650
600
550
500
1.2
450
400
1.0
−20
0
20
40
60
80
100
120
350
−20
140
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6.
Figure 7.
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6
100
NCP1028
TYPICAL CHARACTERISTICS
8.0
71.0
7.5
70.0
69.0
7.0
68.0
67.0
Fosc (kHz)
IC1 (mA)
6.5
6.0
5.5
5.0
66.0
65.0
64.0
63.0
62.0
61.0
4.5
4.0
60.0
59.0
−20
3.5
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
0
20
40
120
87.0
100
85.0
80
83.0
60
79.0
20
77.0
20
40
60
80
100
75.0
120 140
−20
0
20
TEMPERATURE (°C)
120
140
40
60
80
100
120
140
100
120
140
TEMPERATURE (°C)
Figure 10.
Figure 11.
610
13.0
600
12.5
IBO HYSTERESIS (mA)
590
580
VBO (mV)
100
81.0
40
0
80
Figure 9.
Dmax (%)
Fosc (kHz)
Figure 8.
0
−40 −20
60
TEMPERATURE (°C)
570
560
550
540
530
12.0
11.5
11.0
10.5
10.0
9.5
520
510
−20
0
20
40
60
80
100
120
140
9.0
−20
TEMPERATURE (°C)
0
20
40
60
80
TEMPERATURE (°C)
Figure 13.
Figure 12.
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NCP1028
TYPICAL CHARACTERISTICS
11
880
10
RDS(on) @ ID = 100 mA (W)
860
Ipeak (mA)
840
820
800
780
760
8
7
6
5
4
3
740
720
−20
2
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
−20
40
60
80
TEMPERATURE (°C)
Figure 14.
Figure 15.
3.8
30
3.7
28
0
20
100
120
140
100
120
140
100
120
140
26
Iopp (%)
3.6
Vlatch (V)
9
3.5
24
22
3.4
20
3.3
18
3.2
−20
0
20
40
60
80
100
120
16
−20
140
20
40
60
80
TEMPERATURE (°C)
Figure 16.
Figure 17.
2.8
RAMP COMPENSATION LEVEL (V)
380
Tleb + Tpropdelay (ns)
0
TEMPERATURE (°C)
400
360
340
320
300
280
260
240
220
200
Ipin 7 = 40 mA
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
2.7
2.6
2.5
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 18.
Figure 19.
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8
NCP1028
100
68
90
66
80
64
70
Idss OFF (mA)
70
62
60
58
56
50
40
20
52
50
−20
60
30
54
10
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 21.
Figure 20.
85°C
100%
125°C
90%
IPEAK REDUCTION (%)
TimerON (ms)
TYPICAL CHARACTERISTICS
140°C
80%
−40°C
70%
0°C
25°C
60%
−20°C
50%
40%
30%
20%
10%
0%
0
50
100
150
IOPP (mA)
200
250
Figure 22. Ipeak Reduction = F(lopp, @ temperature)
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100
120
140
NCP1028
APPLICATION INFORMATION
• Over Power Protection: A possibility exists to reduce
Introduction
The NCP1028 offers a complete current−mode control
solution and enhances the NCP101X series. The
component integrates everything needed to build a rugged
and low−cost Switch−Mode Power Supply (SMPS)
featuring low standby power.
• Current−Mode Operation: The controller uses a
current−mode control architecture, which, together
with an adjustable ramp compensation circuitry,
ensures efficient and stable continuous or
discontinuous conduction designs.
• 700 V–5.8 W Power Switch Circuit: Due to
ON Semiconductor Very High Voltage Integrated
Circuit technology, the circuit hosts a high−voltage
power switch circuit featuring a 5.8 W RDS(on) – TJ =
25°C. This value lets the designer build a 15 W
power supply operated on universal mains as
long as sufficient copper area exists to lower the
junction−to−ambient thermal resistance. An internal
current source delivers the startup current, necessary
to crank the power supply.
• Short−Circuit Protection: By permanently
monitoring the feedback line activity, the circuit is
able to detect the presence of a short−circuit,
immediately reducing the output power for a total
system protection. A 55 ms timer is started as soon as
the feedback pin asks for the maximum peak current.
At the end of this timer, if the fault is still present,
then the device enters a safe, auto−recovery burst
mode, affected by a fixed 440 ms recurrence. Once the
short has disappeared, the controller resumes and goes
back to normal operation. The timer duration is fully
independent from the VCC capacitor value.
•
•
•
•
•
the maximum output power capability in high line
conditions. A simple two resistor network wired to the
bulk capacitor will program the maximum current
reduction for a given input voltage (down to 20% of
the maximum peak current).
Brown−Out Input: A fraction of the input voltage
appears on pin 3, due to a resistive divider. If the
mains drops below a level adjusted by this resistive
divider, the circuit does not switch. As soon as the
mains goes back within its normal range, the device
resumes operation and operates normally. By adjusting
the bridge resistors, it becomes possible to set the
brown−out levels (on and off) independently.
Latchoff: Pin 3 also welcomes a comparator who
offers a way to fully latch the controller. If an external
event (e.g. an overtemperature) brings the brown−out
pin above 3.5 V, the circuit stays permanently off
until the user cycles its VCC down, for instance by
unplugging the converter from the mains outlet.
Frequency Jittering: The internal clock receives a
low frequency modulation which helps smoothing the
power supply EMI signature.
Soft−Start: A 1.0 ms soft−start ensures a smooth
startup sequence, reducing output overshoots.
Skip Cycle: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less
efficient when the output power demand diminishes.
By skipping unneeded switching cycles, the NCP1028
drastically reduces the power wasted during light load
conditions. Experiments carried over the 5.0 V/2.0 A
demonstration board reveal a standby power at
no−load and 265 Vac of 85 mW and an efficiency for
500 mW output power of 64% at 230 Vac.
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NCP1028
Startup Sequence
The NCP1028 includes a high−voltage startup circuitry,
directly deriving current from the bulk line to charge the
VCC capacitor. Figure 23 details the simplified internal
arrangement.
Vbulk
+
I1
RVCC
1
I2
5
IC1
←
ICC1
Iclamp
- +
+
VCCon
VCCoff
CVCC
Vz = 8.7 V
+
8
Figure 23. Internal Arrangement of the Startup Circuitry
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
the VCC capacitor. When the voltage on this VCC capacitor
reaches the VCCON level (typically 8.5 V), the current
source turns off, reducing the amount of power being
dissipated. At this time, the VCC capacitor only supplies the
controller, and the auxiliary supply should take over before
VCC collapses below VCC(min). This VCC capacitor, CVCC,
must therefore be calculated to hold enough energy so that
VCC stays above VCC(min) (7.3 V typical) until the
auxiliary voltage fully takes over.
An auxiliary winding is needed to maintain the VCC in
order to self−supply the switcher. The VCC capacitor has
only a supply role and its value does not impact other
parameters such as fault duration or the frequency sweep
period for instance. As one can see in Figure 23, an internal
active Zener diode, protects the switcher against lethal VCC
runaways. This situation can occur if the feedback loop
optocoupler fails, for instance, and you would like to
protect the converter against an over voltage event.
The VCC capacitor can be calculated knowing a) the
amount of energy that needs to be stored; b) the time it
takes for the auxiliary voltage to appear, and; c) the current
consumed by the controller at that time. For a better
understanding, Figure 24 shows how the voltage evolves
on the VCC capacitor upon startup.
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NCP1028
Figure 24. A typical startup sequence showing the VCC capacitor
voltage evolution versus time.
Suppose our power supply takes 10 ms (tstartup) to bring
the output voltage to its target value. We know that the
switcher consumption is around 2.0 mA (ICC1). Therefore,
we can calculate the amount of capacitance we need, to
hold VCC above 7.5 V at least for 10 ms while delivering
2.0 mA:
ICC1tstartup
or, by replacing with the above values,
DVCC
2m · 10 m
Cw
w 20 mF then select a 33 mF for the VCC
1
Cw
capacitor.
Fault Condition – Short−Circuit on VCC
In some fault situations, a short−circuit can purposely
occur between VCC and GND. In high line conditions
(VHV = 370 VDC) the current delivered by the startup
device will seriously increase the junction temperature. For
instance, since IC1 equals 3.0 mA (the min corresponds to
the highest TJ), the device would dissipate 370
3m=
1.1 W. To avoid this situation, the controller includes a
novel circuitry made of two startup levels, IC1 and IC2. At
powerup, as long as VCC is below a 1.3 V level, the source
delivers IC1 (around 650 mA typical), then, when VCC
reaches 1.3 V, the source smoothly transitions to IC2 and
delivers its nominal value. As a result, in case of
short−circuit between VCC and GND, the power dissipation
will drop to 370
650 m = 240 mW. Figure 25 portrays
this particular behavior.
Figure 25. The startup source now features a
dual−level startup current.
The first startup period is calculated by the formula
C V = I t, which implies a 33 m 1.3/650 m = 66 ms
startup time for the first sequence (t1). The second
sequence (t2) is obtained by toggling the source to 4.0 mA
with a delta V of VCCON – VCCth = 8.5 – 1.5 = 7.0 V,
which finally leads to a second startup time of
7
33 m/6.0 m = 39 ms. The total startup time becomes
66 m + 39 m = 105 ms as a typical value. Please note that
this calculation is approximated by the presence of the knee
in the vicinity of the transition.
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NCP1028
Fault Condition – Output Short−Circuit
As soon as VCC reaches VCCON, drive pulses are
internally enabled. If everything is correct, the auxiliary
winding increases the voltage on the VCC pin as the output
voltage rises. During the start−sequence, the controller
smoothly ramps up the peak current to Imax setting, e.g.
Ipeak_HI, which is reached after a typical period of 1.0 ms.
As soon as the peak current setpoint reaches its maximum
(during the startup period but also anytime an overload
occurs), an internal error flag is asserted, Ipflag, indicating
that the system has reached its maximum current limit set
point (Ip = Ip max). The assertion of this flag triggers a
55 ms counter. If at counter completion Ipflag remains
asserted, all driving pulses are stopped and the part stays off
during eight periods of 55 ms (440 ms). A new attempt to
restart occurs and will last 55 ms providing the fault is still
present. If the fault still affects the output, a safe burst mode
is entered, affected by a low duty−cycle operation (11%).
When the fault disappears, the power supply quickly
resumes operation. Figure 26 depicts this particular mode.
Figure 26. In case of short−circuit or overload, the NCP1028 protects itself and the power supply via a low
frequency burst mode. The VCC is maintained by the current source and self−supplies the controller.
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13
NCP1028
In Figure 26, one can see that the VCC is still alive,
testifying for a badly coupled power secondary and
primary auxiliary windings. Some situations exist where an
output short−circuit make the auxiliary winding collapse
before the timer completion. In this particular case, the
Undervoltage Lock Out (UVLO) circuitry has the priority
and safely cuts off all driving pulses. Figure 27 describes
this variation.
Figure 27. The auxiliary winding collapses in presence of a short−circuit. Pulses are immediately stopped
as VCC crosses the minimum operating voltage, VCC(min).
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NCP1028
Fault Condition – Output Too Low
This particular mode of operation occurs when the
feedback is ensured by a two−loop control imposing either
constant output voltage (CV) or constant output current
(CC), for instance in a battery charger. In CC mode, the
output voltage falls down below the original target but the
feedback loop is kept closed by the CC controller. For that
reason, the controller becomes un−able to detect a real
output short−circuit since Ipflag will never be asserted.
Due to a good winding coupling, the primary side auxiliary
collapsing will ensure a proper fault detection via the
UVLO internal circuit. Figure 28 depicts this operating
way.
Figure 28. In this particular case, the output goes low but the timer is not started since the FB pin is still held
by the optocoupler. Due to the UVLO circuit, the controller safely stops operation at VCC = VCC(min).
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15
NCP1028
Fault Condition – Low Input Voltage
The NCP1028 includes a brown−out circuitry able to
protect the power supply in case of low input voltage
conditions. Figure 29 shows how internally the NCP1028
monitors the voltage image of the bulk capacitor. Below a
given level, the controller blocks the driving pulses, above
it, it authorizes them. The internal circuitry, depicted by
1
16.0
Figure 29a, offers a way to observe the high−voltage (HV)
rail. A resistive divider made of Rupper and Rlower , brings
a portion of the HV rail on pin 3. Below the turn−on level,
the 10 mA current source IBO is off. Therefore, the turn−on
level solely depends on the division ratio brought by the
resistive divider.
vin
vcmp
2
160
Vbulk = 70 V
Vbulk = 100 V
IBO
BO
Rlower
Plot1
Vcmp Volts
Rupper
VDD
←
Vbulk
ON/OFF
+
-
8.00
120
Vin in Volts
12.0
80.0
4.00
40.0
0
0
BO
+
VBO
2
1
20.0u
Figure 29a. The internal brown−out
configuration with an offset current source.
60.0u
100u
Time in Seconds
140u
180u
Figure 29b. Simulation results for 100/70 ON/OFF levels.
Figure 29.
To the contrary, when the internal BO signal is high, the IBO source is activated and creates an hysteresis. As a result,
it becomes possible to select the turn−on and turn−off levels via a few lines of algebra.
IBO is Off
V()) + Vbulk1
Rlower
Rlower ) Rupper
IBO is On
V()) + Vbulk2
Rlower
) IBO
Rlower ) Rupper
Rupper
ǒRRlower
Ǔ
lower ) Rupper
(eq. 1)
(eq. 2)
We can now extract Rlower from Equation 1 and plug it into Equation 2, then solve for Rupper :
Rupper + Rlower
Rlower + VBO
Vbulk1−VBO
VBO
Vbulk1−Vbulk2
IBO (Vbulk1−VBO)
If we decide to turn−on our converter for Vbulk1 equals 100 V and turn it off for Vbulk2 equals 70 V, then we obtain:
Rupper = 3.0 MW
Rlower = 18 kW
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16
NCP1028
The bridge power dissipation is 3302/3.018 Meg =
36 mW in nominal high−line operation. Figure 29b
simulation result confirms our calculations.
Figure 30 describes signal variations during a brown−out
condition. Please note that output pulses only reappear
when VCC reaches VCC(ON), ensuring a clean startup
sequence. As in fault mode conditions, the startup source
is activated on and off and self−supplies the controller in a
Dynamic Self−Supply (DSS) mode.
Figure 30. Signal Evolution During a Brown−Out Condition
Depending on input surge tests, it might be necessary to
wire a filtering capacitor between BO and GND (close to
the circuit) to avoid adversely triggering the internal latch
(unless this is a wanted feature) when the pulse train
appears.
presence of a secondary overvoltage (the feedback loop is
drifting) or when an overtemperature is detected.
Secondary monitoring is usually implemented when the
coupling between auxiliary and power windings does not
lead to a precise primary detection. Due to the addition of
a comparator on the BO pin, a simple external circuit can
lift up this pin above VLATCH and permanently disable
pulses. The VCC needs to be cycled down below 3.5 V
typically to reset the controller.
Latchoff Protection
There are some situations where the converter shall be
fully turned−off and stay latched. This can happen in the
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17
NCP1028
VCC
20 ms
RC
Vbulk
+
-
Vout
Q1
+
Vlatch
Rupper
IBO
←
BO
NTC
To permanent
latch
+
-
VDD
BO
Rlower
+
VBO
Figure 31. Adding a comparator on the BO pin offers a way to latch−off the controller.
In Figure 31, Q1 is blocked and does not bother the BO
measurement as long as the NTC and the optocoupler are
not activated. As soon as the secondary optocoupler senses
an OVP condition, or the NTC reacts to a high ambient
temperature, Q1 base is brought to ground and the BO pin
goes up, permanently latching off the controller. Figure 32
depicts the converter behavior in case of total latch−off.
Figure 32. If the BO pin is lifted up to VLATCH, the controller permanently latches off.
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NCP1028
Designing the Auxiliary Winding
A NCP1028 internal arrangement clamps the voltage
applied on the VCC pin. It uses an active shunt circuitry as
shown on Figure 33. Care must be taken to avoid injecting
too much current when the clamp is activated. The
insertion of a resistor (Rlimit ) between the auxiliary dc level
and the VCC pin is thus mandatory not to damage the
internal 8.7 V zener diode during an overshoot for instance
(absolute maximum current is 15 mA. Please note that
there cannot be bad interaction between the clamping
voltage of the internal zener and VCCON since this
clamping voltage is actually built on top of VCCON with a
fixed amount of offset (200 mV typical). Rlimit should be
carefully selected to avoid disturbing the VCC in low / light
load conditions. The below lines detail how to evaluate the
Rlimit value.
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a
SMPS operated at nominal load can deliver an auxiliary
voltage of an arbitrary 16 V (Vnom), this voltage can drop
below 10 V (Vstby) when entering standby. This is because
the recurrence of the switching pulses expands so much that
the low frequency re−fueling rate of the VCC capacitor is
not enough to keep a proper auxiliary voltage. Figure 34
portrays a typical scope shot of a SMPS entering deep
standby (output un−loaded). Thus, care must be taken when
calculating Rlimit not to drop too much voltage over it when
entering standby. Otherwise, the converter will enter burst
mode as it will sense an UVLO condition. Based on these
recommendations, we are able to bound Rlimit between two
equations:
Vstby−VCCON
Vnom−Vclamp
v Rlimit v
ICC1
ICCmax
(eq. 3)
Where:
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.
ICCmax is the maximum current you can inject in the pin
without damaging the controller (15 mA).
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part
in standby does almost not switch. It is around 1.0 mA for
the 65 kHz version and 1.4 mA for the 100 kHz one.
VCC(min) is the level above which the auxiliary voltage
must be maintained to keep the controller away from the
UVLO trip point. It is good to obtain around 8.0 V in order
to offer an adequate design margin, e.g. to not reactivate the
startup source (which is not a problem in itself if low
standby power does not matter).
Drain
VCCON = 8.5 V
VCC(min) = 7.5 V
Startup
Source
←
+
+
VCC
D1
Rlimit
+
-
+
Vclamp = 8.7 V Typ.
+
CVCC
+
CAUX
Laux
I > 6 mA
Ground
Figure 33. A more detailed view of the NCP1028 offers better
insight on how to properly wire an auxiliary winding.
Plugging the values in Equation 3 gives the limits within
which Rlimit shall be selected:
Since Rlimit shall not bother the controller in standby, e.g.
keep Vauxiliary to around 8.0 V (as selected above), we
purposely select a Vnom well above this value. As explained
before, experience shows that a 40% decrease can be seen
on auxiliary windings from nominal operation down to
standby mode. Let’s select a nominal auxiliary winding of
20 V to offer sufficient margin regarding 8.0 V when in
standby (Rlimit also drops voltage in standby…).
20−8.7 v R
12−8
limit v 1 m , that is to say : 1.3 kW t Rlimit
10 m
t 4 kW.
We purposely limited the injected current to 10 mA in
order to include a safety margin.
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NCP1028
As the internal logic takes some time to react, the switch
gate shutdown does not immediately occur when the
maximum power limit is detected (just before activating
the overload protection circuit). Clearly speaking, it can
take up to 100 ns for the NCP1028 current sense
comparator to propagate through the various logical gates
before reaching the power switch and finally shutting it off.
This is the well−known propagation delay noted tprop .
Unfortunately, during this time, the current keeps growing
as Figure 35 depicts. The peak current will therefore be
troubled by this propagation delay. The formula to obtain
the final value is simply:
> 30 ms
V
Ipeak, final + in t prop ) Ipeak, max
Lp
Figure 34. The burst frequency becomes so low
that it is difficult to keep an adequate level on the
auxiliary VCC.
At low line, Son is relatively low and does not bother the
final peak value. The situation differs at high line and
induces a higher peak current. Therefore, the power supply
output power capability increases with the input voltage.
Let us a take a look at a simple example. Suppose the peak
current is 700 mA:
Lp = 1.0 mH
Vin lowline = 100 Vdc
Over Power Compensation
Over Power Compensation or Protection (OPP)
represents a way to limit the effects of the propagation
delay when the converter is supplied from its highest input
voltage. The propagation delay naturally extends the
power capability of any current−limited converter.
Figure 35 explains why. The main parameter is the on
slope, that is to say, the pace at which the inductor current
grows−up when the power switch closes. For a flyback
controller, the slope is given by:
V
Son + in
Lp
(eq. 5)
Vin highline = 350 Vdc
Ipeak,max = 700 mA
tprop = 100 ns
Pout + 1 I2
F
L h
2 peak, final SW p
(eq. 6)
Where: Fsw is the switching frequency and h the efficiency.
Usually h is bigger in high line conditions than in low line
conditions. This formula is valid for a Discontinuous
Conduction Mode flyback.
From Equation 5, we can calculate the final peak current
in both conditions:
Ipeak,final = (100/1m) x 100n + 700m = 710 mA at low line.
(eq. 4)
where Lp is the transformer magnetizing/primary
inductance and Vin , the input voltage.
Ipeak,final = (350/1m) x 100n + 700m = 735 mA at high line.
From Equation 6, we can have an idea of the maximum
output power capability again, in both conditions with
respective low and high line efficiency numbers of 78%
and 82% for instance:
Pout,lowline = 0.5
0.712
1m
65k
0.78 = 12.8 W
Pout,highline = 0.5 0.7352 1m 65k 0.82 = 14.4 W
Figure 35. Internal logic blocks take a certain
amount of time before shutting off the driving
pulses in presence of an overcurrent event.
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NCP1028
This difference might not be seen as a problem, but some
design specifications impose stringent conditions on the
maximum output current capability, regardless the line
input. Hence the need for an OPP input…
Since we want to limit the power to 12.8 W at high line,
let us calculate the needed peak current:
From equation 6: Ipeak +
10 kW and ROPPU made of a series string of 4
1.0 MW
resistors plus a 10−turn 1.0 MW potentiometer set at its
maximum value. An amp−meter is inserted in series with
pin 7 and a volt−meter monitors its voltage with respect to
ground. Once the power supply is powered, slowly rotate
the potentiometer and observe both voltage and current
going up at pin 7. At a certain time, as voltage and current
increase, the controller will shut down the power supply.
The current at this time is the one we are looking for.
Suppose these experiments lead to 80 mA with a pin 7
activation voltage of 2.45 V. Final resistor equations are:
VbulkH = 375 Vdc ; the maximum voltage at which OPP
must shut down the controller
VbulkL = 200 Vdc ; the minimum voltage below which
OPP is not activated
IOPP = 80 mA
; the current in pin 7
Vf = 2.45 V
; the voltage of pin 7 at the above
condition
out = 693 mA to
ǸF2P
SWLph
deliver 12.8 W at high line.
Compared to our 735 mA, we need to decrease the
setpoint by 6% roughly when Vin equals 350 Vdc.
The NCP1028 hosts a special circuitry looking at the
couple voltage/current present on pin 7. Figure 36 shows
how to arrange components around the controller to obtain
Over Power Protection.
Bulk
ROPPU
Current
Setpoint
Over Power
Protection
OPP
V
−V
ROPPL + bulkH bulkL Vf + 27 kW
IOPP(VbulkL−Vf)
(eq. 7)
V
−V
ROPPH + ROPPL bulkL f + 2.2 MW
Vf
(eq. 8)
If the OPP feature is not needed for some designs, it is
possible to ground it via a copper wire to the adjacent
ground pin. This can help to develop a larger copper area
in an application where the thermal resistance is an
important parameter.
ROPPL
GND
Figure 36. A resistive network reduces the
power capability in high−line conditions.
Ramp Compensation
When operating in Continuous Conduction Mode
(CCM), current−mode power supplies can exhibit
so−called sub−harmonic oscillations. To cure this problem,
the designer must inject ramp compensation. The ramp can
either be added to the current sense information or directly
subtracted from the feedback signal. Figure 37 details the
internal arrangement of the ramp compensation circuitry.
First, you need to know the required injected current and
the voltage across pin 7 to start activating OPP.
Experiments consist in wiring Figure 36 circuit and
running the power supply in conditions where it must shut
down (e.g. highest input voltage and maximum output
current per specification). For this, ROPPL can be put to
VDD
Gate Reset
IRR
Ramp
Control
Vp
RR
Figure 37. The Internal Feedback Chain and the Ramp Compensation Network
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21
NCP1028
Np:Ns = 1:N = 1:0.052 transformer turn ratio
Lp = 3.8 mH
primary inductance
We can calculate the off slope, the one actually needed
to evaluate Sa , by reflecting the output voltage over the
primary inductance. The slope is projected over a complete
switching period. Here, we use a 65 kHz part.
The principle consists in selecting the RR resistor,
connected from pin 2 to ground, to impose a current IRR in
the transistor collector.
) Vf
V
6 15u
Soff + out
TSW +
+ 455 mAń15 ms
0.052 3.8m
NLp
(eq. 10)
Due to the internal sense arrangement, this current slope
will become a voltage slope having a value of:
SȀoff + 455m
0.375 + 170 mVń15 ms (eq. 11)
If we chose 50% of this downslope, then the final
compensation ramp will present a slope of:
Sa + 170m + 85 mVń15 ms
2
(eq. 12)
We then have:
Figure 38. Maximum Peak Current Setpoint
Variations versus Ramp Compensation
RR +
Vp2.75 k
Sa@TSW
(eq. 13)
In the above calculations, the internal ESD resistor has
purposely been omitted to avoid bringing in another
variable. In case no ramp compensation is required, pin 2
must be tied to VCC, the adjacent pin.
The equation to get the right compensation level is the
following:
RR +
Vp2.75 k
+ 2.75 2.75k + 89 kW
85m
Sa@TSW
(eq. 9)
Soft−Start
The NCP1028 features a 1.0 ms soft−start, which
reduces the power−on stress, but also contributes to lower
the output overshoot. Figure 39 shows a typical operating
waveform. The NCP1028 features a novel patented
structure which offers a better soft−start ramp, almost
ignoring the startup pedestal inherent to traditional
current−mode supplies.
where Vp, the total voltage swing, equals 2.75 V.
Application example:
Suppose we have the following flyback specifications:
Vout = 5.0 V
output voltage
Vf = 1.0 V
secondary diode forward drop
@ Iout nominal
Figure 39. 1.0 ms Soft−Start Sequence
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NCP1028
Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP1028 offers a "6%
deviation of the nominal switching frequency. The sweep
sawtooth is internally generated and modulates the clock
up and down with a fixed frequency of 300 Hz. Figure 40
shows the relationship between the jitter ramp and the
frequency deviation. It is not possible to externally disable
the jitter.
Jitter ramp
68.9kHz
65kHz
Internal
61.1kHz
sawtooth
adjustable
Figure 40. Modulation Effects on the Clock Signal by the
Jittering Sawtooth
Skip−Cycle
Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads.
However, the recurrent frequency in skip often enters the
audible range and a high peak current obviously generates
acoustic noise in the transformer. The noise takes its origins
in the resonance of the transformer mechanical structure
which is excited by the skipping pulses. A possible
solution, successfully implemented in the NCP1200 series,
also authorizes skip cycle but only when the power demand
as dropped below a given level. This is what Figure 41
shows, as implemented on the NCP1028.
Nominal peak
current
Skip cycle
current limit
0
Figure 41. Low Peak Current Skip Cycle Guarantees Noise−Free Operation
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NCP1028
5.0 V/3.0 A Universal Mains Power Supply
Due to its low RDS(on), the NCP1028 can be used in
universal mains SMPS up to 15 W of continuous power,
provided that the chip power dissipation is well under
control. That is to say that average power calculations and
measurements have been carried and correlated. The
design of an SMPS around a monolithic device does not
differ from that of a standard circuit using a controller and
a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us
follow the steps:
Vin min = 120 Vdc
Vin max = 375 Vdc
Vout = 5.0 V
Vout = 15 W
Operating mode is CCM
h = 0.8
1. The lateral MOSFET body−diode shall never be
forward biased, either during startup (because of a
large leakage inductance) or in normal operation
as shown by Figure 42. This condition sets the
maximum voltage that can be reflected during toff .
350
250
150
50.0
> 0 !!
50.0
−
1.004M
1.011M
1.018M
1.025M
1.032M
Figure 42. The reflected voltage shall always be greater
than the minimum input voltage to avoid the forward
biasing of the MOSFET body−diode.
Figure 43. Primary Inductance Current
Evolution in CCM
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N(Vout ) Vf) t Vin, min t Vin min (eq. 14) . In our case,
since we operate from a 120 V DC rail while delivering
5.0 V, we can select a reflected voltage of 110 V
DC maximum: 120−110 > 0. Therefore, the turn ratio
Np:Ns must be smaller than
turn ratio, Vout the output voltage, Vf the
secondary diode forward drop and finally, Ipeak
the maximum peak current. Worse case occurs
when the SMPS is very close to regulation, e.g.
the Vout target is almost reached and Ipeak is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at
Vin = 375 Vdc). This voltage is given by the RCD
clamp installed from the drain to the bulk
voltage. We will see how to calculate it later on.
3. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
Vin
+ 110 + 18.3 or
5)1
Vout ) Vf
Np : Ns t 19. We will see later on how it affects the
calculation.
2. Lateral MOSFETs have a poorly doped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD
clamping network shall thus be installed to
protect the MOSFET. In some low power
applications, a simple capacitor can also be used
since Vdrain max + Vin ) N (Vout ) Vf)
) Ipeak
ǸCLtotf
(eq. 15)
d max +
NVout
1
+
+ 0.49
Vin,min
NVout ) Vin, min
1 ) NV
(eq. 16)
out
4. To obtain the primary inductance, we have the
choice between two equations:
L+
, where Lf is the leakage
•
inductance, Ctot the total capacitance at the drain
node (which is increased by the capacitor you
will wire between drain and source), N the Np:Ns
(eq. 17)
, where K +
DIL
and
I1
defines the amount of ripple we want in CCM
(see Figure 43).
Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
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24
(Vind)2
fSWKPin
NCP1028
• Large K: approaching BCM where the rms losses are
If we take the maximum RDS(on) for a 120°C junction
temperature, i.e. 11 W, then conduction losses worse case
are:
the worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 16, a K factor of 0.8 (40% ripple), gives
an inductance of:
Pcond + I2d, rms Rds(on) + 571 mW
6. Off−time and on−time switching losses can be
estimated based on the following calculations:
(120 0.49)2
L+
+ 3.8 mH
60k 0.8 18.75
V d
DIL + in + 120
3.8m
LFSW
Poff +
0.49 + 258 mA peak * to * peak
60k
(eq. 18)
IpeakN(Vout ) Vf)ton
6TSW
+ 0.447 114 40n + 22 mW
6 15u
The peak current can be evaluated to be:
Pon +
Iavg DIL
DI
Ipeak +
)
+ Ipeak + 156m ) L + 447 mA
0.49
2
2
d
In Figure 43, I1 can also be calculated:
5. Based on the above numbers, we can now
evaluate the conduction losses:
Ǹ1 ) 13 ǒDI2I1LǓ2 + 0.318
0.7
Power Switch Circuit Protection
As in any Flyback design, it is important to limit the drain
excursion to a safe value, e.g. below the power switch
circuit BVdss which is 700 V. Figures 44a, b, c present
possible implementations:
Ǹ1 ) 13 ǒ2 0.258
Ǔ2 + 228 mA rms
0.318
HV
HV
HV
Rclamp
Cclamp
Dz
D
CVCC +
D
1
8
1
8
1
8
2
7
2
7
2
7
3
6
3
6
3
6
4
5
4
5
4
5
CVCC +
(eq. 19)
The theoretical total power is then 0.571 + 0.13 + 0.022
= 723 mW.
7. The ramp compensation will be calculated as
suggested by Equation 13 giving a resistor of
78 kW or 82 kW for the normalized value.
DI
I1 + Ipeak− L + 0.447−0.129 + 318 mA
2
Id, rms + I1 Ǹd
IpeakVdstoff
+ 0.447 650 40n + 130 mW
6 15u
6TSW
CVCC +
C
a.
b.
c.
Figure 44. Different Options to Clamp the Leakage Spike
Figure 44a: The simple capacitor limits the voltage
according to Equation 14. This option is only valid for low
power applications, e.g. below 5.0 W, otherwise chances
exist to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with Equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses…
Figure 44b: The most standard circuitry called the RCD
network. You calculate Rclamp and Cclamp using the
following formulae:
Rclamp +
2Vclamp(Vclamp−(Vout ) Vf) N)
LpeakI2peak FSW
Vclamp
Cclamp +
VrippleFSWRclamp
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25
(eq. 20)
(eq. 21)
NCP1028
Power Dissipation and Heatsinking
The NCP1028 hosting a power switch circuit and a
controller, it is mandatory to properly manage the heat
generated by losses. If no precaution is taken, risks exist to
trigger the internal thermal shutdown (TSD). To help
dissipating the heat, the PCB designer must foresee large
copper areas around the PDI7 package. When surrounded
by a surface greater than 1.0 cm@ of 35 mm copper, it
becomes possible to drop the thermal resistance
junction−to−ambient, RqJA down to 75°C/W and thus
dissipate more power. The maximum power the device can
clamp is usually selected 50−80 V above the reflected
value N (Vout + Vf). The diode needs to be a fast one and
an MUR160 represents a good choice. One major
drawback of the RCD network lies in its dependency upon
the peak current. Worse case occurs when Ipeak and Vin are
maximum and Vout is close to reach the steady−state value.
Figure 44c: This option is probably the most expensive
of all three but it offers the best protection degree. If you
need a very precise clamping level, you must implement a
Zener diode or a TVS. There are little technology
differences behind a standard Zener diode and a TVS.
However, the die area is far bigger for a transient suppressor
than that of Zener. A 5.0 W Zener diode, like the 1N5388B,
will accept 180 W peak power if it lasts less than 8.3 ms.
If the peak current in the worse case (e.g. when the PWM
circuit maximum current limit works) multiplied by the
nominal Zener voltage exceeds these 180 W, then the diode
will be destroyed when the supply experiences overloads.
A transient suppressor like the P6KE200 still dissipates
5.0 W of continuous power, but is able to accept surges up
to 600 W @ 1.0 ms. Select the Zener or TVS clamping
level between 40 to 80 V above the reflected output voltage
when the supply is heavily loaded.
thus evacuate is: P max +
Tj max −Tamb max
(eq. 22)
RqJA
which gives around 930 mW for an ambient of 50°C and a
maximum junction of 120°C. The losses inherent to the
switch circuit RDS(on) can be theoretically evaluated, but
the final prototype evaluation must include board
measurements to confirm that the junction temperature
stays within safe limits. Figure 45 gives a possible layout
to help dropping the thermal resistance. When measured on
a 70 mm (2 oz.) copper thickness PCB, we obtained a
thermal resistance of 75°C/W.
Figure 45. A possible PCB arrangement to reduce the thermal resistance
junction−to−ambient.
When routing the printed circuit, it is important to keep
high impedance line very short, like the brown−out signal
and the OPP input if used.
to remove unwanted spikes, although less problematic than
in DCM operation. On the primary side, a resistive network
senses the input bulk voltage and prevents the controller
from turning on for input voltages below 100 Vdc. The
auxiliary winding delivers 20 V nominal and thus offers
comfortable margin when the converter enters standby. As
we do not use any OPP, pin 7 goes to ground and offers
extended possibility to layout more copper area.
Application Diagram
Figure 46 displays the final application schematic. The
output uses a TLV431 whose low bias current represents an
advantage for low standby power switch mode supplies.
The secondary side features an additional LC filter needed
www.onsemi.com
26
C13
220 nF
85−265 VAC
Type = X2
27
+
www.onsemi.com
R3
18 k
C4
47 mF/
400 V
R10
200 k
R1
2.8 M
Figure 46. 5.0 V−3.0 A Universal Mains Power Supply
CVCC
47 mF
C1
R2
10 n 78 k
+
R9
5.6 k
20 V
+ C11
1 mF
D2
1N4637
5
7
8
C10
2.2 nF
Type = Y1
D5
1N4637
C7
10 nF
Type = 400 V
U2
NCP1028
C12
100 p
4
3
2
1
R5
150 k
Type = 1W
+
+
U1
TL431
+
C5 C8 C9
D1 470 470 470
MBRD640CTT4 mF mF mF
Np:Ns = 1:0.062
Np:Naux = 1:0.208
Lp = 3.8 mH
R4
100
C2
100 nF
R11
1k
L2
2.2 mH
R7
10 k
R6
10 k
C3
100 mF
+
Vout
5V@
3A
NCP1028
NCP1028
Transformer Specifications:
Vout = 5.0 V/3.0 A
Vaux = 20 V/10 mA
Lp = 3.8 mH
Ip, rms = 280 mA
Ip, max = 800 mA
Isec, rms = 5.0 A
Fsw = 65 kHz
Np:Nsec = 1 : 0.052
Np:Naux = 1 : 0.208
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28
NCP1028
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE B
D
A
E
H
8
5
E1
1
4
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
TOP VIEW
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
M
D1
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT
TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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NCP1028/D