Mitel MT8920BP Iso-cmos st-busâ ¢ family st-bus parallel access circuit Datasheet

ISO-CMOS ST-BUS FAMILY MT8920B
ST-BUS Parallel Access Circuit

Features
•
•
•
•
•
•
•
•
ISSUE 7
High speed parallel access to the serial ST-BUS
Parallel bus optimized for 68000 µP (mode 1)
Fast dual-port RAM access (mode 2)
Access time: 120 nsec
Parallel bus controller (mode 3) - no external
controller required
Flexible interrupt capabilities - two
independent/programmable interrupt sources
with auto-vectoring
Selectable 24 and 32 channel operation
Programmable loop-around modes
Low power CMOS technology
March 1997
Ordering Information
MT8920BE
28 Pin Plastic DIP
MT8920BP
28 Pin Plastic J-Lead
MT8920BS
28 Pin SOIC
-40°C to 85°C
Description
The ST-BUS Parallel Access Circuit (STPA) provides
a simple interface between Mitel’s ST-BUS and
parallel system environments.
Applications
•
•
•
•
•
Parallel control/data access to T1/CEPT digital
trunk interfaces
Digital signal processor interface to ST-BUS
Computer to Digital PABX link
Voice store and forward systems
Interprocessor communications
D7-D0
A4-A0
CS
DS, OE
R/W, WE
DTACK,
BUSY, DCS
IRQ, 24/32
IACK, MS1
Tx0
Dual Port Ram
32 X 8
Parallelto-serial
Converter
STo0
Rx0
Dual Port Ram
32 X 8
Serial-toParallel
Converter
STi0
Tx1
Dual Port Ram
32 X 8
Parallelto-Serial
Converter
STo1
Parallel
Port
Interface
Interrupt
Registers
Comp/
MUX
Control
Registers
A5, STCH
MMS
Address
Generator
VSS
F0i
C4i
VDD
Figure 1 - Functional Block Diagram
3-3
3
MT8920B
4
3
2
1
28
27
26
VDD
MMS
DTACK, BUSY, DCS
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
CS
DS, OE
R/W, WE
A0
A1
A2
A3
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
28
27
26
25
24
23
22
21
20
19
18
17
16
15
25
24
23
22
21
20
19
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
A4
A5, STCH
VSS
D0
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C4i
F0i
IACK, MS1
STi0
CS
DS, OE
R/W, WE
A0
A1
A2
A3
A4
A5, STCH
VSS
STi0
IACK, MS1
F0i
C4i
VDD
MMS
DTACK,
BUSY, DCS
CMOS
28 PIN PDIP/SOIC
28 PIN J-LEAD
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description‡
1
C4i
4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial
bus.
2
F0i
Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS
stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of
a frame.
3
IACK
Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is
an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will
output a user-programmed vector number on D0 - D7 indicating the source of the interrupt.
MS1
Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low
applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)
4
STi0
ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream.
5
CS
Chip Select. This active low input is used to select the STPA for a parallel access .
6
DS
Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data
bus during a write operation or that the STPA must output valid data on the data bus during a
read operation.
OE
Output Enable (Mode 2). This active low input enables the data bus driver outputs.
OE
Output Enable (Mode 3). This active low output indicates that the selected device is to be
read and that the data bus is available for data transfer.
R/W
Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write
(R/W= 0) cycle.
WE
Write Enable (Mode 3). This active low output indicates the data on the data bus is to be
written into the selected location of an external device.
7
8-12
A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port
memories of the STPA.
A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the
position in internal RAM where the information will be fetched from or stored in. Addresses
generated in this mode are used to access external devices for direct memory transfer.
3-4
CMOS
MT8920B
Pin Description (continued)
Description‡
Pin #
Name
13
A5
Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5
selects internal registers when high and Tx/Rx RAM’s when low.
A5
Address Bit A5 (Mode 2). This input is used to extend the address range of the STPA. A5
selects Tx0/Rx0 RAM’s when low and Tx1/Rx0 RAM’s when high.
STCH Start of Channel (Mode 3). This signal is a low going pulse which indicates the start of an
ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel.
14
15-22
VSS
Ground.
D0-D7 Bidirectional Data Bus. This bus is used to transfer data to or from the STPA during a write
or read operation.
23
STo0
ST-BUS Output 0. This output supplies the output ST-BUS 2048 kbit/s serial data stream from
Tx0 two-port RAM.
24
STo1
ST-BUS Output 1. In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial
data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with
one frame delay.
25
IRQ
Interrupt Request (Mode 1). This open drain output, when low, indicates when an interrupt
condition has been raised within the STPA.
24/32
24 Channel/32 Channel Select (Mode 2,3). This input is used to select the channel
configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode
while a high will select a 32 (CEPT) channel mode.
26
DTACK Data Transfer Acknowledge (Mode 1). This open drain output is supplied by the STPA to
acknowledge the completion of data transfers back to the µP. On a read of the STPA, DTACK
low indicates that the STPA has put valid data on the data bus. On a write, DTACK low
indicates that the STPA has completed latching the µP’s data from the data bus.
BUSY BUSY (Mode 2). This open drain output signals that the controller and the ST-BUS are
accessing the same location in the dual-port RAM’s. It is intended to delay the controller
access until after the ST-BUS completes its access.
27
DCS
Delayed Chip Select (Mode 3). This low going pulse, which is four bit cells long, is active
during the last half of a valid channel. This signal is used to daisy-chain together two STPA’s in
mode 3 that are accessing devices on the same parallel data bus.
MMS
Master Mode Select (Reset). This Schmitt trigger input selects between either mode 1 (MMS
= 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and
interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the
reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.
28
VDD Power Supply Input. (+5V).
‡ Pin Descriptions pertain to all modes unless otherwise stated.
Mode
MMS
MS1
Mode of
Operation
Function
1
1
N/A
µP
Peripheral
Mode
The STPA provides parallel-to-serial and serial-to-parallel conversions through a
68000-type interface. Two Tx RAMs and one Rx RAM are available along with full
interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit
D5 (RAMCON) = 0 for 32 channel operation and D5 (RAMCON)= 1 for 24 channel
operation.
2
0
1
Fast RAM
Mode
The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is
intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT
trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32
channel operation.
3
0
0
Bus
Controller
Mode
The STPA will synchronously drive the parallel bus using the address generator and
provide all data transfer signals. This mode is intended to support 24 or 32 channel
devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel
operation, input 24/32 (pin 25) = 1 for 32 channel operation.
Table 1. STPA Modes of Operation
3-5
MT8920B
CMOS
Functional Description
control busses are used to communicate between
the RAM‘s and a parallel environment.
The STPA (ST-BUS Parallel Access) device provides
a simple interface between Mitel’s ST-BUS and
parallel system environments. The ST-BUS is a
synchronous, time division, multiplexed serial
bussing scheme with data streams operating at 2048
kbit/s. The ST-BUS is the primary means of access
for voice, data and control information to Mitel’s
family of digital telecommunications components,
including North American and European digital trunk
interfaces, ISDN U and S digital line interfaces, filter
codecs, rate adapters, etc. The STPA provides
several modes of operation optimized according to
the type of information being handled.
For interfacing parallel data and control information
to the ST-BUS, such as signalling and link control for
digital trunks, the STPA provides a µP access mode
(Mode 1), and looks like a 68000 type peripheral. In
this mode, the device provides powerful interrupt
features, useful in monitoring digital trunk or line
status (i.e., synchronization, alarms, etc.) or for
setting up message communication links between
microprocessors.
To interface high speed data or multi-channel voice/
data to the ST-BUS for switching or transmission, the
STPA has a high speed synchronous access mode
(Mode 2) and acts like a fast RAM. For voice storage
and forward, bulk data transfer, data buffering and
other similar applications, the STPA has a
controllerless mode (Mode 3) in which it provides
address and control signals to the parallel bus This
is useful for performing direct transfers to the
ST-BUS from external devices such as a RAM buffer.
The STPA is a two port device as shown in the
functional block diagram in Figure 1. The parallel
port provides direct access to three dual port RAM’s,
two transmit and one receive. The address, data and
µP Peripheral Mode #1
C4i
F0i
IACK
STi0
CS
DS
R/W
A0
A1
A2
A3
A4
A5
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Two
parallel-to-serial
converters,
and
one
serial-to-parallel converter interface the dual port
RAM’s to the ST-BUS port of the STPA. This port
consists of two serial output streams and one serial
input stream operating at 2048 kbit/s.
This
configuration of two outputs and one input was
designed to allow a single STPA to form a complete
control interface to Mitel’s digital trunk interfaces
(MT8976, MT8978 and MT8979) which have two
serial input and one serial output control streams.
ST-BUS clocking circuitry, address generator and
various control and interrupt registers complete the
STPA’s functionality.
Modes of Operation
The three basic modes of operation, µP Peripheral
Mode (Mode 1), Fast RAM Mode (Mode 2) and Bus
Controller Mode (Mode 3) are selected using two
external input pins. These inputs are MMS and MS1
and are decoded as shown in Table 1. Whenever
MMS=1 the device resides in Mode 1. In this mode,
MS1 pin is unavailable and is used for a different
function.
When MMS=0, Modes 2 or 3 are selected as
determined by input MS1. If MS1=1, Mode 2 is
selected and if MS1 =0, Mode 3 is selected.
Each of the modes of the STPA provides a different
pinout to ease interfacing requirements of different
parallel environments. These are shown in Figure 3
below. In µP Peripheral Mode the device uses
interface signals consistent with a 68000-type µP
bus. Mode 2, Fast RAM Mode, uses signals typical
of standard RAM type interfaces. Mode 3 interface
signals are very similiar to Mode 2 signals except
that the address and control signals are supplied as
outputs by the STPA.
Fast RAM Mode #2
VDD
MMS
DTACK
IRQ
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
C4i
F0i
MS1
STi0
CS
OE
R/W
A0
A1
A2
A3
A4
A5
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Bus Controller Mode #3
VDD
MMS
BUSY
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
C4i
F0i
MS1
STi0
CS
OE
WE
A0
A1
A2
A3
A4
STCH
VSS
Figure 3 - Modes 1, 2, 3 Pin Connections
3-6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MMS
DCS
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
CMOS
24/32 Channel Operation
The STPA may be configured to operate as a 32
channel or 24 channel device. This feature, which is
available in all three modes of operation, is
particularly useful in applications involving data
access to CEPT and T1 digital trunk interfaces.
When used as a data interface to Mitel‘s CEPT
digital trunks, the STPA maps the 32 consecutive
bytes of each dual port memory directly to ST-BUS
channels 0-31. This is performed by the address
generator shown in the functional block diagram (see
Figure 1). Figures 4 c & d show the relationship
between relative dual port RAM locations and
corresponding ST-BUS channels, for both input and
output serial streams, when the STPA is configured
as a 32 channel device.
When used as a data interface to Mitel’s T1 trunk
devices, however, only the first 24 consecutive RAM
locations are mapped to 24 of the 32 ST-BUS
channels. This mapping follows a specific pattern
which corresponds with the data streams used by
Mitel‘s T1 products. Instead of a direct correlation
(as in 32 channel operation), the 24 consecutive
RAM locations are mapped to the ST-BUS with every
fourth channel, beginning at channel 0, set to FF16
(ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). Figures
4 a & b show the relationship between RAM
locations and ST-BUS channel configuration. This
feature allows the STPA to be interfaced directly to
Mitel’s T1 trunk family.
When the STPA is operated in Mode 1, 24 and 32
channel configurations are selected using bit D5
(RAMCON) in Control Register 1. D5 = 0 selects 32
channel operation and D5 = 1 selects 24 channel
operation. When the STPA is operated in Modes 2 or
3, however, the channel configuration is done
using input 24/32 (pin 25). When 24/32 = 1 the
device uses all 32 channels and when 24/32 = 0 it
uses 24.
Dual Port RAMS
Each of the three serial ST-BUS streams is
interfaced to the parallel bus through a 32 byte dual
port RAM. This allows parallel bus accesses to be
performed asynchronously while accesses at the
ST-BUS port are synchronous with ST-BUS clock.
As with any dual port RAM interface between two
asynchronous systems, the possibility of access
contention exists. The STPA minimizes this
occurrence by recognizing contention only when
accesses are performed at the same time for the
same 8-bit cell within the dual port RAM’s.
Furthermore, the probability of contention is
MT8920B
lessened since ST-BUS accesses require only the
last half cycle of C4i of every channel. When
contention does occur, priority is always given to the
ST-BUS access.
The STPA indicates this contention situation in a
different manner for Modes 1 and 2. In Mode 1, the
contention
is
masked
by
virtue
of
the
"handshaking" method used to transfer data on
this 68000-type interface.
Data Strobe (DS)
and Data Transfer Acknowledge (DTACK) control
the exchange.
If contention should occur the
device will delay returning DTACK and thus stretch
the bus cycle until the µP access can be completed.
In Mode 2, if access is attempted during a
"contention window" the STPA will supply the
BUSY signal to delay the start of the bus cycle. This
“contention window” is defined as shown in Figure
16. The window exists during the last cycle of C4i
clock in each channel timeslot. Although ST-BUS
access is only required during the last half of this
clock period, the “contention window“ exists for the
entire clock period since a parallel access occurring
just prior to an ST-BUS access will not complete
before the ST-BUS access begins. Figure 16 further
shows four possible situations that may occur when
parallel accesses are attempted in and around the
“contention window”. Condition 1 indicates that an
access occurring prior to the contention window but
lasting into the first half of it will complete normally
with no contention arbitration. If the access should
extend past the first half of the contention window
and into the ST-BUS access period, the BUSY signal
will be generated. Conditions 3 and 4 show accesses
occurring inside
the contention window. These
accesses will result in BUSY becoming active
immediately after the access is initiated and
remaining active as shown in Figure 16.
Access contention is non-existent in Mode 3 since
the parallel bus signals, driven by the STPA, are
synchronized to the ST-BUS clocks.
Mode 1 - µP Peripheral Mode
In Mode 1, the STPA operates as an asynchronous
68000-type microprocessor peripheral. All three
dual-port RAMS (Tx0, Tx1, Rx0) are made available
and may be configured as 32 or 24 byte RAM’s. Also
available are the full complement of control and
interrupt registers. The address map for Mode 1 is
shown in Table 2.
The STPA, in Mode 1, uses signals CS, R/W, DS
(Data Strobe), DTACK (Data Acknowledge) IRQ, and
IACK (Interrupt Acknowledge) at the parallel interface.
The pinout of the device is shown in Figure 3.
3-7
3-8
RELATIVE
RAM
LOCATION
0
1
1
0
STo0
STo1
1
0
RELATIVE
RAM
LOCATION
1
0
1
0
1
0
0
X
0
X
STi0
RELATIVE
RAM
LOCATION
STo0
STo1
RELATIVE
RAM
LOCATION
STi0
2
2
2
2
1
2
1
2
3
3
3
3
2
3
2
3
3
5
4
6
5
7
8
X
6
9
7
8
9
10 11
12 13 14
15 16 17
18 19 20
3
5
4
6
5
7
8
X
6
9
7
8
9
10 11
12 13 14
15 16 17
18 19 20
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
X- unused channels marked X transmit FF16
Figure 4 d) RELATIVE Tx RAM ADDRESS vs. ST-BUS CHANNEL - 32 CHANNEL MODE
4
4
Figure 4 c) RELATIVE Rx RAM ADDRESS vs. ST-BUS CHANNEL - 32 CHANNEL MODE
4
4
21 22 23
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
X
X
X
X
X
Figure 4 b) RELATIVE Tx RAM ADDRESS vs. ST-BUS CHANNEL - 24 CHANNEL MODE
4
X
21 22 23
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
X
X
X
X
X
Figure 4 a) RELATIVE Rx RAM ADDRESS vs. ST-BUS CHANNEL - 24 CHANNEL MODE
4
X
MT8920B
CMOS
CMOS
ADDRESS BITS
MT8920B
REGISTERS
A6
A5
A4
A3
A2
A1
A0
READ
WRITE
0
•
•
•
0
0
•
•
•
0
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
Tx0 - Channel 0
•
•
•
Tx0 - Channel 31
X
1
0
0
0
0
0
Control Register 1
Control Register 1
X
1
0
0
0
0
1
Control Register 2
Control Register 2
X
1
0
0
0
1
0
Interrupt Vector Register
Interrupt Vector Register
X
1
0
0
1
0
0
Interrupt Flag Register 1
-
X
1
0
0
1
0
1
Interrupt Flag Register 2
-
X
1
0
0
1
1
0
Image Register 1
-
X
1
0
0
1
1
1
Image Register 2
-
X
1
0
1
0
0
0
Interrupt Mask Register 1
Interrupt Mask Register 1
X
1
0
1
0
0
1
Interrupt Mask Register 2
Interrupt Mask Register 2
X
1
0
1
0
1
0
Match Byte Register 1
Match Byte Register 1
X
1
0
1
0
1
1
Match Byte Register 2
Match Byte Register 2
X
1
0
1
1
0
0
Interrupt Channel Address 1
Interrupt Channel Address 1
X
1
0
1
1
0
1
Interrupt Channel Address 2
Interrupt Channel Address 2
1
•
•
•
1
0
•
•
•
0
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
Rx0 - Channel 0
•
•
•
•
•
•
1
Rx0 - Channel 31
Table 2. Mode 1 Address Map
NOTES:
Tx1 - Channel 0
•
•
•
Tx1 - Channel 31
X is don’t care
A 6 is bit D4 of Control Register 1
Bit
Name
Description
7
(Unused)
6
IRQRST
5
RAMCON
4
A6
3
IRQ2MODE
Interrupt Source 2 Mode Select. This bit configures the source 2 interrupt generator.
D3 = 0 selects “static” interrupt mode; D3 = 1 selects “dynamic” interrupt mode.
2
IRQ1MODE
Interrupt Source 1 Mode Select. This bit configures the source 1 interrupt generator.
D2 = 0 selects “static” interrupt mode; D2 = 1 selects “dynamic” interrupt mode.
1
IRQ2EN
Interrupt Source 2 Enable. IRQ2EN = 1 enables interrupts to occur from source 2.
0
IRQ1EN
Interrupt Source 1 Enable. IRQ1EN = 1 enables interrupts to occur from source 1.
Table 3. Control Register 1 Bit Definitions
Interrupt Reset. This bit, when set high, automatically clears the Interrupt Flag Register
and the Interrupt Image Register without these registers being serviced. This bit
automatically resets to zero after the register clear is completed.
RAM Configuration. This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte
operation. D5 = 0 for 32 channel; D5 = 1 for 24 channel.
Address Bit A6.
This bit extends the addressing range for access to Tx1 memory.
3-9
MT8920B
CMOS
Timing information for data transfers on this interface
is shown in Figure 14. The Mode 1 interface is
designed to operate directly with a 68000-type
asynchronous bus but can easily accommodate most
other popular microprocessors as well.
Control Registers
Two control registers allow control of Mode 1
features. Control Register 1 provides bits to select
the type of interrupt, to enable interrupts from two
different and independent sources and to reset the
interrupt registers.
Also contained in Control
Register 1 are bits to configure the device for 24 or
32 channel operation and to expand the address
range for convenient access to the second transmit
RAM Tx1. A description of the bit functions in
Control Register 1 is shown in Table 3.
Mode 1 provides various loopback paths and output
configuration options which are controlled by bits in
Control Register 2. Bits D0, D1 of Control Register 2
configure loopbacks using input and output streams
STi0, STo0 as described in Table 4. The input
stream STi0 can be looped back to source the output
stream STo0 as well as receive RAM Rx0. The
transmit RAM Tx0 can be looped to source the
receive RAM Rx0, as well as STo0 and, the transmit
RAM Tx0 can be looped to the receive RAM Rx0
while STi0 sources STo0. The function of these
loopback configurations is shown in Figure 5.
In a similar way, the output STo1 can be reconfigured
for different functionality. Bits D2 and D3 of Control
Register 2 allow STo1 to be sourced, with a one
frame delay via Tx1 from receive stream STi0. STo1
can also output the result of a comparison of the
contents of Tx1 ram with input stream STi0. These
output configurations of STo1 are shown in Figure 6
Bit
Name
7-4
(Unused)
3-2
CONFIG
1-0
3-10
a and b. Figure 6 c shows the effect of combining
these two features.
Interrupt Registers
Interrupts can be generated in Mode 1 only. Two
channels of the ST-BUS input stream, STi0, can be
selected to provide an interrupt to the system.
Interrupts can be of two types: Static or Dynamic.
Static interrupts are caused when data within a
selected channel matches a given pattern. Dynamic
interrupts occur when bits in a selected channel
change state (1 to 0, 0 to 1 or toggle). Interrupts are
controlled through two identical paths (1 and 2)
consisting of the following registers:
Interrupt Channel Address (1/2): The address
(0-31) of the channel which will generate the
interrupt is stored in this register.
Image Register (1/2):
The contents of the
channel causing the interrupt is stored in this
register. Reading this register will clear its contents.
Match Byte Register (1/2):
In static mode this
register is used to store the byte which will be
compared with the contents of the selected channel
causing the interrupt.
In dynamic mode, the bits in this register and the
corresponding bit in the Interrupt Mask Register
define the type of dynamic interrupt (i.e., 0 to 1, 1 to
0, toggle). (Refer to Table 5.)
Description
STo1 Output Configuration Bits:
D3D2 = 00Normal operation. ST-BUS stream from Tx1 is output on STo1 pin.
01STi0 stream is output on STo1 pin delayed one frame (Figure 6 a).
10STi0 is compared through XOR (exclusive OR) with ST-BUS stream
from Tx1 and output at STo1 (Figure 6 b).
11STi0 stream, delayed one frame (via Tx1), is compared (XOR) with the
next frame arriving at STi0 and the result output at STo1 (Figure 6 c).
LOOPBACK Internal Loopback Configuration Bits:
D1D0 = 00Normal operation. No internal loops.
01Loop STi0 to STo0 while still receiving STi0 in Rx0 (Figure 5 a).
10Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream while
outputting Tx0 output to STo0. STi0 is not received (Figure 5 b).
11Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream. Loop
STi0 to STo0 (Figure 5 c).
Table 4. Control Register 2 Bit Definitions
MT8920B
CMOS
Control Register 2
Bits D3 = 0, D2 = 1
Control Register 2
Bits D1 = 0, D0 = 1
µP
STo0
Tx0
STo0
Rx0
STi0
µP
Rx0
STi0
Tx1
a)
STo1
1 Frame Delay
a)
Control Register 2
Bits D3 = 1, D2 = 0
Control Register 2
Bits D1 = 1, D0 = 0
Tx0
STo0
µP
µP
Rx0
Tx0
STo0
Rx0
STi0
STi0
STo1
Tx1
b)
b)
Control Register 2
Bits D3 = 1, D2 = 1
Control Register 2
Bits D1 = 1, D0 = 1
µP
Tx0
STo0
Rx0
STi0
Tx0
STo0
Rx0
STi0
µP
STo1
Tx1
c)
c)
Figure 5 - Loopback Configurations
Interrupt Mask Register (1/2): In static mode the
contents of this register masks bits in the Match Byte
Register that are ’don’t care’ bits
1 - bit masked
0 - bit not masked
In dynamic mode, each bit in this register and the
corresponding bit in the Match Byte Register define
what type of dynamic interrupt is selected. (Refer to
Table 5.)
1 Frame Delay
Figure 6 - STo1 Configurations
Interrupt Vector Register
This register shown in Figure 7 is common to both
interrupt paths and stores an 8 bit vector number
which will be output on the data bus when
Interrupt Acknowledge (IACK) is asserted. Bits
labelled V2 - V7 are stored by the controlling µP.
Bits IRQ1 and IRQ2 are set by the STPA to indicate
which path caused the interrupt. This creates unique
vectors which are used by the µP to vector to
interrupt service routines. This feature may be
bypassed by simply not asserting IACK during
interrupt acknowledged.
Interrupt Flag Register (1/2):
In static mode
the least significant bit in this register is set to 1 to
flag the corresponding path in which the interrupt
occurs.
In dynamic mode this register sets the bits which
reflect the position of the bits in the corresponding
Interrupt Register which caused the interrupt.
D7
D6
D5
D4
D3
D2
V7
V6
V5
V4
V3
V2
D1
D0
IRQ2 IRQ1
Figure 7 - Interrupt Vector Registers
3-11
MT8920B
CMOS
Interrupt Modes and Servicing
D7 D6 D5 D4 D3 D2 D1 D0
Channel Address Register 1 =
Static Interrupt Mode
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
(channel 4 of STi0 selected)
A static interrupt is caused when an incoming byte
matches a predefined byte. The incoming byte from
a selected channel is stored in Interrupt Image
Register (1/2) where it is compared with the contents
of the corresponding Match Byte Register. The
result of the comparison of individual bits is masked
by the contents of the Mask Register (1/2) before it
is used to generate an IRQ. After a static interrupt
occurs, information in the Interrupt Image Register is
frozen until the µP performs a read operation on this
register.
When servicing static interrupts assertion of IACK
will cause the contents of the Vector Register, with
the IRQ1 or IRQ2 bit set, to be output on the data
bus. The service routine can subsequently clear IRQ
by reading the Interrupt Image Register.
Alternatively, the IRQRST bit in Control Register 1
can be set to clear the associated interrupt registers.
Static Interrupts are selected using IRQ1MODE and
IRQ2MODE bits in Control Register 1. Interrupts are
then enabled to the IRQ pin with IRQ1EN and
IRQ2EN bits of the same register.
Dynamic Interrupt Mode
A dynamic interrupt is generated by a change of
state of bits in a selected channel. A 0 to 1 transition
or a 1 to 0 transition or a simple change of state from
the previous state (toggle) can be detected. The
type of transition to be detected is selected using two
bits, one from the Match Byte Register (1/2) and one
from the Interrupt Mask Register (1/2), in the
corresponding bit positions. Table 5 shows how the
two registers are programmed.
Match
Byte
Register
bit DX
Mask
Byte
Register
bit DX
Transition Type Detected
on Incoming bit DX
(x = 0 ....7)
0
0
1
1
0
1
0
1
Mask Bit DX
0 to 1 transition
1 to 0 transition
Toggle
0
0
Match Byte Register 1 =
Interrupt Mask Register 1 =
0
0
0
0
0
0
(When bit D3 toggles 0 to 1)
Dynamic interrupts from interrupt path 1 would then
be enabled using the Control Register 1.
0
Control Register 1 =
0
0
0
0
1
As with static interrupts, upon serving a dynamic
interrupt, assertion of IACK will cause the contents
of the Vector Register, with the appropriate path bit
set, to be output on the data bus. The information
contained in the channel is frozen in the Interrupt
Image Register.
To clear a dynamic interrupt,
however, the µP must read the Interrupt Flag
Register of the path responsible for the interrupt to
determine which bit caused the interrupt. The bit in
the corresponding position will be set to 1 and
reading this register will clear its contents.
Alternatively, as with static interrupts, the IRQRST bit
in Control Register 1 can be set to clear the Image
Interrupt Register, Flag Register and path bits in the
Vector Register.
Dynamic Interrupts are selected using IRQ1MODE
and IRQ2MODE bits in Control Register 1 and are
enabled using IRQ1EN and IRQ2EN in the same
register.
MMS Pin Reset
The STPA can be RESET in Mode 1 using the MMS
pin (27). Applying a low pulse (0V) to MMS after
power is applied to the device will reset all control
and interrupt registers to 0016.
This can be
accomplished on power up with a simple R-C circuit
as shown in Figure 8.
VDD
R
STPA
MMS
27
C
Figure 8 - MMS Reset Function
3-12
1
This would cause interrupt 1 path to be enabled
while interrupt 2 path is disabled.
Table 5 - Dynamic Interrupt Types
For example, the following steps are required to
generate an interrupt when bit D3 of channel 4
changes state from 0 to 1 (all other bits are masked):
0
CMOS
Mode 2 - Fast RAM Mode
MT8920B
reads and writes with framing and channel boundary
information.
Mode 2 operates as a high speed dual port RAM
interface to the ST-BUS. Only the two transmit
RAM’s, Tx0 and Tx1, and the receive RAM, Rx0 are
active in this mode (i.e., control registers and
interrupt registers are inactive).
The main feature of this mode is fast access to the
dual-port RAM’s. Fast access allows high-speed
controllers to use this device as a data interface to
T1 and CEPT digital links. Timing information is
shown in Figure 15.
Mode 2 can also support 24 channel and 32 channel
operation. The channel configuration is selected
using 24/32 pin. When 24/32=0 the device operates
in 24 channel mode and when 24/32=1, it operates in
32 channel mode.
The physical interface in this mode resembles that of
a simple RAM device. The signals used to read
and write the device are CS, OE, R/W. The pinout of
the STPA in this mode is shown in Figure 3. Address
decoding for Tx0, Tx1, Rx0 is shown in Table 6.
Contention can arise for access to the dual port
RAMS. The occurrence of this is minimized since
the ST-BUS serial-to-parallel and parallel-to-serial
converters require RAM access for only 1/32 of
a channel time (i.e., last half cycle of C4i for
each channel). For contention to occur the high
speed controller must access the same RAM
location as that of the ST-BUS. For a parallel read
operation this corresponds to the current ST-BUS
channel and for a write operation, the next ST-BUS
channel. Access contention in Mode 2 is arbitrated
with the BUSY signal. BUSY is intended to hold
off any parallel access cycle until it again goes
inactive. Figure 16 shows how the access is
arbitrated for accesses near the contention window.
Applications using high speed access can easily
avoid generating BUSY by co-ordinating channel
Mode 3 - Parallel Bus Controller
In this mode the STPA outputs all necessary signals
required to drive devices attached to the parallel
port. The STPA can be used to drive devices such
as RAM’s, FIFO’s, latches, A/D and D/A converters,
and CODECS, directly from the ST-BUS without an
intervening µP. As with the other modes, Mode 3 can
operate from 32 channels or 24 channels by
connecting 24/32 high or low, respectively. This
allows devices to be driven remotely via a T1 or
CEPT digital trunk link when used with Mitel’s trunk
products.
Referring to Figure 1, the Address Generator block
generates and drives the external address lines
A4-A0. The STPA also generates OE (output
enable) and WE (write enable) to facilitate data
transfers from Rx0 RAM and to Tx0 RAM. Tx1 RAM
is unavailable in this mode.
The STPA, in Mode 3, generates external addresses
in a particular sequence that minimizes throughput
delay through the device. When channel N is
present on the ST-BUS, the STPA generates address
N+1 on the address bus and asserts OE to output
data from an external device and latch it into the
STPA. During the same channel N, the STPA
will generate address N-1 with WE asserted to
write from the STPA to an external device. Timing for
Mode 3 transfers is shown in Figure 17. All parallel
bus signals are synchronized to the ST- BUS clock.
The device must be selected using CS in order for
the parallel bus drivers to be enabled. CS should
remain active for four ST-BUS bit periods (8 x C4i
cycles) since a read and a write operation require 2
bit periods each. The STPA generates a signal STCH
(start of channel) which becomes active at the start
of each channel and remains active for 1/2 of the
channel time (Figure 18). This signal may be
ADDRESS BITS
REGISTERS
A5
A4
A3
A2
A1
A0
READ
WRITE
0
•
•
•
0
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
Tx0 - Channel 0
•
•
•
Tx0 - Channel 31
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
Tx1 - Channel 0
•
•
•
Tx1 - Channel 31
Table 6. Mode 2 Address Map
3-13
MT8920B
CMOS
connected directly
appropriately.
to CS to enable the device
connected on a common bus, to be driven by two
ST-BUS streams. Figure 9 shows how this "daisy
chaining" of STPA’s is implemented while Figure 10
illustrates the timing on the shared parallel bus.
Common Bus
OE
WE
CS
STCH
Applications
STi0
A0
A1
A2
A3
A4
Parallel PBX to Digital Trunk Interface
STo0
The STPA is an ideal component for interfacing
parallel PBX environments to Mitel’s family of digital
trunk devices.
MMS MS1 24/32
0
0
CS
OE
WE
1
Figure 11 shows a typical interface for both T1/ESF
and CRC-4 CEPT digital trunks to a system utilizing
a parallel bus architecture.
Both the MH89760B
T1/ESF and the MH89790B CRC-4 CEPT trunk
modules are shown interfaced to a parallel bus
structure using two STPAs operating in modes 1 and
2.
DCS
STi0
A0
A1
A2
A3
A4
STo0
MMS MS1 24/32
0
0
1
Figure 9 - "Daisy-chained" STPA’s in 32 Channel
Parallel Bus Controller Mode (Mode 3)
In order to facilitate efficient use of the parallel bus
another signal, similar to STCH, is supplied by the
STPA. Delayed Chip Select (DCS) becomes active
for the last half of each channel (Figure 19). This
may be connected to a second STPA, residing on the
same physical parallel bus, enabling it to perform its
read/write operations in the second half of each
channel. This allows a large number of devices,
The first STPA operating in mode 2 (MMS=0,
MS1=1, 24/32=0), routes data and/or voice
information between the parallel telecom bus and the
T1 or CEPT link via DSTi and DSTo. The second
STPA, operating in mode 1 (MMS=1) provides
access from the signalling and link control bus to the
MH89760B or MH89790B status and control
channels. All signalling and link functions may be
controlled easily through the STPA transmit RAM’s
Tx0, Tx1, while status information is read at receive
RAM Rx0. In addition, interrupts can be set up to
notify the system in case of slips, loss of sync,
alarms, violations, etc.
CHANNEL N
ST-BUS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
C4i
Address
N+1
N-1
N+1
N-1
OE
WE
Data Bus
IN
OUT
IN
OUT
STCH
DCS
Figure 10 - Timing Relationship for Mode 3 Daisy Chaining
3-14
F0i
C4i
STi0
STo1
STo0
+5V
MMS
F0i
IACK
C4i
IRQ
STi0
STo1
STo0
†
DS
R/W
DTACK
CS
A0-A5
D0-D7
(Mode 1)
MT8920B
+5V
MMS MS1 24/32
R/W
OE
CS
A0-A5
D0-D7
+5V††
RxD
RxA
RxB
TxA
TxB
E8Ko
Clock
Extractor
E1.5i† (E2i††)
C1.5i†
F0i
C2i
CSTi1
CSTi0
CSTo
DSTi
DSTo
MT8977/79
MH89760B/790B
Rx
Line
Receiver
Tx
Line
Driver
Figure 11 - Typical T1-ESF / CRC-4 CEPT Digital Trunk Configuration
NOTES:
† Signals applicable to T1-ESF applications using MT8977 and MH89760B
†† Signals applicable to CRC-4 CEPT applications using MT8979 and MH89790B
* Equalizer MH89761 available for T1/ESF applications
SIGNALLING
AND LINK
CONTROL
BUS
HIGH
SPEED
PARALLEL
TELECOM
BUS
(Mode 2)
MT8920B
C8Kb
C4b
F0b
C2o
F0i†
C1.5o†
MT8940†
MH89761*
EQU
DIP
Switch
16.388
MHz Osc.
12.355†
MHz Osc.
CMOS
MT8920B
3-15
MT8920B
CMOS
Digital Signal Processor to ST-BUS Interface
Mode 2 allows many high speed devices to be easily
connected to the ST-BUS. Figure 12 shows a
TMS32020 digital signal processor interfaced to the
ST-BUS through the STPA. This simple interface
allows complex functions to be implemented in such
systems as PBX’s and computer systems. Some of
the possible functions include:
-
Digital Filtering
Voice Conferencing
Speech/Data Compression
Encryption
Tone Detection and Generation
Frequency Spectrum Analysis
Image Processing
µ-Law to A-Law Conversion
Echo Cancellation
Modulation
Speech Synthesis and Recognition
74HCT
138
TMS32020
DS
MT8920B
E2
A9
A8
E1
A
A7
B
A6
C
CS
STo0
A8-A0
A5-A0
STi0
D7-D0
D7-D0
STo1
STRB
RW
OE
WE
MSC
READY
MMS MS1 24/32
+5V +5V
Figure 12 - ST-BUS to DSP Interface
3-16
CMOS
Connecting the STPA to a shared ST-BUS Line
MT8920B
a high impedance state at the output of U1,
corresponding to the selected channel.
The STPA’s STo0 and STo1 outputs cannot be
directly forced into a high impedance state.
However, with some external logic, the STo0 output
can be buffered by a three-state device, controlled by
the STo1 output. This application is only possible if
the Tx1 RAM and associated STo1 output are not
required for some other purpose.
Figure 13 shows an external buffer U1 controlled by
the STo1 output and an external Output Data Enable
(ODE) signal. When FF (hex) is written to the Tx1
RAM, the corresponding STo1 output channel goes
to logic high. This signal, AND-ed together with a
logic high at ODE, enables U1, resulting in the STo0
signal transparently passed to the output of U1.
When 00 (hex) is written to the Tx1 RAM, the STo1
output goes logic low. This disables U1, resulting in
This method of three-state buffering permits output
control on a per-channel or per-bit basis.
The ODE input is used to enable the ST-BUS outputs
after all ST-BUS devices are properly configured by
software.
This eliminates the possibility of
contention on the ST-BUS lines during the power-up
state.
74HC125
STo0
Parallel Port
U1
ST-BUS
MT8920B
STo1
74HC00
U2
ODE
ODE
STi0
STi1
STo0
STo1
MT8980
STi7
STo7
Parallel Port
Figure 13 - Connecting STPA to a Common ST-BUS Line
3-17
MT8920B
CMOS
Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
VDD
-0.3
7.0
V
-0.3
VDD + 0.3
V
±25
mA
125
°C
600
mW
1
Supply Voltage
2
Voltage on any I/O pin
3
Current on any I/O pin
II/O
4
Storage Temperature
TST
5
Package Power Dissipation
Plastic
-55
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
5.0
5.25
V
Test Conditions
1
Supply Voltage
VDD
4.75
2
Input High Voltage
VIH
2.4
VDD
V
for 400mV noise margin
3
Input Low Voltage
VIL
0
0.4
V
for 400mV noise margin
4
Operating Temperature
TA
-40
85
°C
25
5
‡
Operating Clock Frequency
fCK
4.096
MHz
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
Supply Current
Static
Dynamic
Sym
Min
ICCS
ICCD
Typ‡
Max
Units
10
5
10
µA
mA
2.0
Test Conditions
outputs unloaded
@fCK = 4.096 MHz
2
Input High Voltage
VIH
3
Input Low Voltage
VIL
0.8
V
4
Input Leakage Current
IZ
±10
µA
5
Input capacitance
CIN
10
pF
6
Schmitt trigger input high (MMS)
VT+
7
Schmitt trigger input low (MMS)
VT-
8
Schmitt trigger hysteresis (MMS)
VH
0.8
1.0
V
9
Output high current (except IRQ)
IOH
10
15
mA
VOH = 2.4V, VDD = 4.75V
10
Output low current (except IRQ)
IOL
5
10
mA
VOL = 0.4V, VDD = 4.75V
11
IRQ, DTACK, BUSY Sink Current
IOL
10
15
mA
VOL = 0.4V, VDD = 4.75V
12
Tristate Leakage A4-A0, OE, WE
(mode 3)
IOZ
±1
±10
µA
VDD = 5.25V
VOUT = VSS to VDD
13
Open drain off-state current
IRQ, DTACK, BUSY
IOFF
±1
±20
µA
VDD = 5.25V
VOUT = VDD
3.8
V
3.0
2.0
VDD=5.25V,
VIN=VSS to VDD
V
1.0
V
14 Output capacitance
CO
15
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-18
MT8920B
CMOS
AC Electrical Characteristics†- Mode 1 Parallel Bus Timing (see Fig. 14)
(VCC=5.0V ±5%,TA=-40 to 85°C)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Address to DS (CS) Low††
tARDS
0
ns
2
R/W to DS (CS) Low††
tRWDS
20
ns
tRDS1,2
tcwm
tcwm
-30
Low††
3
DS (CS) Low to DTACK
tCLK
2*tCLK
4
Valid Data to DTACK Low (Read)
tRD
5
DS High to DTACK High
tDAR
6
DS High to Data High Imped.(Read)
tDHZ
0
7
DS High to CS High
tCSH
0
ns
8
Data Hold Time (Write)
tDHT
0
ns
9
Input Data Valid after DS
tDST
10
Address Hold Time††
Test Conditions
ns
Load C
ns
Load A, CL=130pF, RL=740Ω
65
ns
Load C, CL=50pF
45
ns
Load A, CL=130pF, RL=740Ω
tcwm
-30
ns
tADHT
50
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, VDD=5V, tCLK=244 ns, tCH=tCL=122 ns and are for design aid only: not guaranteed and not subject to production
testing.
††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.
(1) tcwm is equal to tCH or tCL whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t CHmin=70ns
or t CLmin=70ns.
(2) Worst case access when memory contention occurs.
A0 - A5
tADHT
CS (IACK†)
tARDS
R/W
tCSH
tRWDS
DS
tRDS
tDAR
DTACK
tRD
tDHZ
DATA OUT
D0 - D7
tDHT
tDST
D0 - D7
DATA IN
Figure 14 - Mode 1 Parallel Bus Timing
† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.
3-19
MT8920B
CMOS
AC Electrical Characteristics† - Mode 2 Parallel Bus Timing - (see Figures 15 and 16)
(VCC=5.0V ±5%,TA=-40 to 85°C)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
OE Low to Valid Data
tEVD
60
ns
Load A, CL=130pF, RL=740Ω
2
Address Access Time
tAA
120
ns
Load A, CL=130pF, RL= 740Ω
3
CS Low to Valid Data
tCSD
60
ns
Load A, CL=130pF, RL=740Ω
4
Output Disable
tOHZ
50
ns
Load A, CL=130pF, RL=740Ω
5
Address Setup Time
tASF
20
ns
6
Data Setup Time
tDST
30
ns
7
Data Hold Time
tDHT
5
ns
8
Address Hold Time
tAH
50
ns
9
Write Pulse Width
tWP
50
ns
10
OE, R/W High to C4i High
tEC4H
-10
ns
11
OE, R/W Low to C4i Low
tEC4L
10
ns
12
C4i High to Busy Low
tC4BL
50
ns
Load C
13
C4i Low to Busy High
tC4BH
50
ns
Load C
14
OE, R/W High to Busy Low
tEBL
40
ns
Load C
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, VDD=5V, tCLK=244 ns, tCH=tCL=122 ns and are for design aid only: not guaranteed and not subject to production
testing.
A0 - A5
tAH
CS
tASF
OE
tWP
R/W
tOHZ
tEVD
tDST
tCSD
tAA
D0 - D7
DATA OUT
Figure 15 - Mode 2 Timing Diagram (No Contention)
3-20
DATA IN
tDHT
CMOS
MT8920B
CHANNEL (N + 1) - BIT 7
CHANNEL N - BIT 0
ST-BUS ACCESS
CONTENTION WINDOW
C4i
A0 - A5
READ ADDRESS N or WRITE ADDRESS (N + 1)
(N matches incoming
ST-BUS channel)
CS
CONDITION 1:
Access begins before contention window and finishes before ST-BUS access - No contention.
OE, R/W
tEC4H
BUSY
CONDITION 2:
Access begins before contention window and continues into ST-BUS access.
tEC4L
OE, R/W
tC4BL
tC4BH
BUSY
CONDITION 3:
OE, R/W
Access begins within contention window but before ST-BUS access.
tEC4L
tC4BH
tEBL
BUSY
CONDITION 4:
Access begins during ST-BUS access
OE, R/W
tEBL
tC4BH
BUSY
Figure 16 - Mode 2 Access Contention Resolution
3-21
MT8920B
CMOS
AC Electrical Characteristics† - Mode 3 Timing (see Fig.17, 18 and 19)
((VCC=5.0V ±5%,TA=-40 to 85°C)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
CS to OE, WE, Address Enabled
tZR
50
ns
Load A, CL = 130pF, RL = 740Ω
2
C4i Low to Address Change
tACS
110
ns
Load A, CL = 130pF, RL = 740Ω
3
CS to OE, WE, Address Disabled
tRZ
ns
Load A, CL = 130pF, RL = 740Ω
4
C4i Low to Output Enable Low
tOED
75
ns
Load A, CL = 130pF, RL = 740Ω
5
C4i Low to Output Enable High
tOEH
75
ns
Load A, CL = 130pF, RL = 740Ω
6
OE, WE, Pulse Width
tENPW
ns
Load A, CL = 130pF, RL = 740Ω
7
C4i Low to Write Enable Low
tWED
75
ns
Load A, CL = 130pF, RL = 740Ω
8
C4i Low to Write Enable High
tWEH
75
ns
Load A, CL = 130pF, RL = 740Ω
9
Read Data Valid from OE
tRST
(2*tCLK)
-60
ns
50
2*tCLK
10 Read Data Hold Time
tRHT
0
ns
11 Write Data Setup Time
tWST
70
100
ns
Load A, CL = 130pF, RL = 740Ω
12 Write Data Hold Time
tWHT
70
100
ns
Load A, CL = 130pF, RL = 740Ω
13 C4i Transition to STCH, DCS Trans.
tSTC
ns
Load A, CL = 70pF, RL = 1.22KΩ
120
14 STCH Pulse Width
tSCPW
1830
ns
Load A, CL = 70pF, RL = 1.22KΩ
15 DCS Pulse Width
tCSPW
1830
ns
Load A, CL = 70pF, RL = 1.22KΩ
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, VDD=5V,tCLK=244ns, tCH=tCL=122ns and are for design aid only: not guaranteed and not subject to production
testing.
CHANNEL N
BIT 7 (BIT 3)
BIT 6 (BIT 2)
BIT 5 (BIT 1)
BIT 4 (BIT 0)
C4i
tACS
A4 - A0
N+1
N-1
tOEH
tOED
tENPW
OE
tWED
tWEH
tENPW
WE
tRST
tWST
tWHT
tRHT
D7 - D0
DATA IN
DATA OUT
tRZ
tZR
CS
Figure 17 - Mode 3 Timing Diagram
3-22
CMOS
MT8920B
CHANNEL N
CHANNEL N-1
BIT 0
BIT 7
BIT 6
BIT 5
BIT 4
C4i
STCH
tSTC
tSTC
tSCPW
Figure 18 - Mode 3 STCH Timing Diagram
CHANNEL N
BIT 4
BIT 3
BIT 2
BIT 1
CHANNEL
N+1
BIT 0
C4i
STCH
DCS
tSTC
tSTC
tCSPW
Figure 19 - Mode 3 DCS Timing Diagram
3-23
MT8920B
CMOS
AC Electrical Characteristics† - ST-BUS Timing (see Figure 20)
(VCC = 5.0V ± 5%, TA = -40 to 85°C)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Clock C4i Period
tCLK
244
ns
2
Clock C4i Period High
tCH
70
122
ns
3
Clock C4i Period Low
tCL
70
122
ns
4
C4i Rise Time
tR
20
ns
5
C4i Fall Time
tF
12
ns
6
Frame Pulse Setup Time
tFPS
20
ns
7
Frame Pulse Hold Time
tFPH
20
ns
8
STo0/1 Delay from C4i
tSOD
9
STi0 Setup Time
tSTS
100
20
ns
Test Conditions
Load B
ns
35
ns
10 STi0 Hold Time
tSTH
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, VDD=5V and are for design aid only: not guaranteed and not subject to production testing.
Bit Cell
tCL
C4i
tCLK
tFPS
tCH
tFPH
F0i
tSOD
STo0
STo1
tSTS
tSTH
STi0
Figure 20 - ST-BUS Timing Diagram
3-24
tR
tF
MT8920B
CMOS
125 µs
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
31
0
30
31
0
(8/2.048) µs
Bit D0
Bit D7
on
Data Bus
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
on
Data Bus
Figure 21 - Format of 2048 kbit/s ST-BUS Streams
2.0 V
INPUTS
0.8 V
2.0 V
OUTPUTS
0.8 V
Figure 22 - Waveform Test Point Reference
VDD
VDD
RL
500Ω
CL
CL=150pF
6.0k
CL=130pF
IN4148
LOAD A
LOAD B
LOAD C
Figure 23 - Test Load Circuits
3-25
MT8920B
Notes:
3-26
CMOS
Package Outlines
Pin 1
E
A
C
L
H
e
D
L
4 mils (lead coplanarity)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
A1
B
DIM
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.030
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.4625
(11.75)
0.496
(12.60)
0.512
(13.00)
0.5985
(15.2)
0.614
(15.6)
0.697
(17.7)
0.7125
(18.1)
E
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
e
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
General-7
Package Outlines
F
A
G
D1
D2
D
H
E
E1
e: (lead coplanarity)
A1
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"
I
E2
20-Pin
28-Pin
44-Pin
68-Pin
84-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.200
(5.08)
0.165
(4.20)
0.200
(5.08)
A1
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.130
(3.30)
0.090
(2.29)
0.130
(3.30)
D/E
0.385
(9.78)
0.395
(10.03)
0.485
(12.32)
0.495
(12.57)
0.685
(17.40)
0.695
(17.65)
0.985
(25.02)
0.995
(25.27)
1.185
(30.10)
1.195
(30.35)
D1/E1
0.350
(8.890)
0.356
0.450
0.456
0.650
0.656
0.950
0.958
1.150
1.158
(9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413)
D2/E2
0.290
(7.37)
0.330
(8.38)
0.390
(9.91)
0.430
(10.92)
0.590
(14.99)
0.630
(16.00)
0.890
(22.61)
0.930
(23.62)
1.090
(27.69)
1.130
(28.70)
e
0
0.004
0
0.004
0
0.004
0
0.004
0
0.004
F
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
G
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
H
I
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
Package Outlines
3
2
1
E1
E
n-2 n-1 n
D
A2
A
L
C
eA
b2
e
eC
eB
b
Notes:
D1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
A
Max
Min
0.210 (5.33)
Max
Min
0.210 (5.33)
Max
Min
0.210 (5.33)
Max
0.210 (5.33)
A2
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b2
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
C
0.008
(0.203)
0.014 (0.356)
0.008 (0.203)
0.014(0.356)
0.008 (0.203)
0.014 (0.356)
0.008 (0.203)
0.014 (0.356)
D
0.355 (9.02)
0.400 (10.16)
0.780 (19.81)
0.800 (20.32)
0.880 (22.35)
0.920 (23.37)
0.980 (24.89)
1.060 (26.9)
D1
0.005 (0.13)
E
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
E1
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
eA
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
L
0.115 (2.92)
eB
eC
0.150 (3.81)
0.115 (2.92)
0.430 (10.92)
0
0.060 (1.52)
0.150 (3.81)
0.430 (10.92)
0
0.060 (1.52)
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
General-8
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.430 (10.92)
0
0.060 (1.52)
0.150 (3.81)
0.430 (10.92)
0
0.060 (1.52)
Package Outlines
3
2
1
E1
E
n-2 n-1 n
D
α
A2
A
L
C
eA
b2
e
eB
b
Notes:
D1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin
24-Pin
28-Pin
40-Pin
Plastic
Plastic
Plastic
Plastic
Min
A
Max
Min
0.210 (5.33)
Max
Min
0.250 (6.35)
Max
Min
0.250 (6.35)
Max
0.250 (6.35)
A2
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b2
0.045 (1.15)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
C
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
D
1.050 (26.67)
1.120 (28.44)
1.150 (29.3)
1.290 (32.7)
1.380 (35.1)
1.565 (39.7)
1.980 (50.3)
2.095 (53.2)
D1
0.005 (0.13)
E
0.390 (9.91)
0.005 (0.13)
0.430 (10.92)
E
E1
0.330 (8.39)
0.380 (9.65)
E1
0.005 (0.13)
0.600 (15.24)
0.670 (17.02)
0.290 (7.37)
.330 (8.38)
0.485 (12.32)
0.580 (14.73)
0.246 (6.25)
0.254 (6.45)
0.005 (0.13)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
eA
0.400 BSC (10.16)
0.600 BSC (15.24)
0.600 BSC (15.24)
0.600 BSC (15.24)
eA
0.300 BSC (7.62)
eB
L
α
0.430 (10.92)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
15°
Shaded areas for 300 Mil Body Width 24 PDIP only
15°
0.115 (2.93)
0.200 (5.08)
15°
0.115 (2.93)
0.200 (5.08)
15°
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