Features • Single 2.7V to 3.6V Supply • Hardware and Software Data Protection • Low Power Dissipation • • • • • • • • – 15 mA Active Current – 20 µA CMOS Standby Current Fast Read Access Time – 200 ns Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 10 ms Maximum – 1 to 64 Byte Page Write Operation DATA Polling for End of Write Detection High-reliability CMOS Technology – Endurance: 100,000 Cycles – Data Retention: 10 Years JEDEC Approved Byte-wide Pinout Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Only 64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection 1. Description The AT28BV64B is a high-performance electrically erasable programmable read onlymemory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA. AT28BV64B The AT28BV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64 byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28BV64B has additional features to ensure high quality and manufacturability. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0299I–PEEPR–4/09 2. Pin Configurations 32-lead PLCC Top View A0 - A12 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 Function A8 A9 A11 NC OE A10 CE I/O7 I/O6 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 Pin Name 4 3 2 1 32 31 30 A7 A12 NC DC VCC WE NC 2.2 2.1 28-lead SOIC Top View NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Note: PLCC package pins 1 and 17 are Don’t Connect. 2.3 28-lead TSOP Top View OE A11 A9 A8 NC WE VCC NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 3. Block Diagram 4. Device Operation 4.1 Read The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their systems. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Page Write The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 100 µs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28BV64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same. The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 3 0299I–PEEPR–4/09 4.4 DATA Polling The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 4.5 Toggle Bit In addition to DATA Polling, the AT28BV64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28BV64B in the following ways: (a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 4.6.2 Software Data Protection A software-controlled data protection feature has been implemented on the AT28BV64B. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability. The AT28BV64B can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array. 4 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 5. DC and AC Operating Range AT28BV64B-20 Operating Temperature (Case) -40°C - 85°C VCC Power Supply 2.7V to 3.6V 6. Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT VIL VIH VIL DIN VIH X(1) X High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High Z Chip Erase VIL VH(3) VIL High Z Write (2) Standby/Write Inhibit Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 7. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 5 0299I–PEEPR–4/09 8. DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Min Max Units VIN = 0V to VCC + 1V 10 µA Output Leakage Current VI/O = 0V to VCC 10 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 50 µA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 15 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA VOH Output High Voltage IOH = -100 µA 2.0 V 0.45 2.0 V V 9. AC Read Characteristics AT28BV64B-20 Symbol Parameter tACC tCE(1) tOE(2) OE to Output Delay tDF(3)(4) tOH Min Max Units Address to Output Delay 200 ns CE to Output Delay 200 ns 0 80 ns CE or OE to Output Float 0 55 ns Output Hold from OE, CE or Address, Whichever Occurred First 0 ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 6 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 11. Input Test Waveforms and Measurement Level tR, tF < 20 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 1. This parameter is characterized and is not 100% tested. 7 0299I–PEEPR–4/09 14. AC Write Characteristics Symbol Parameter tAS, tOES Address, OE Set-up Time tAH Address Hold Time tCS Min Max Units 0 ns 100 ns Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 100 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid tWPH Write Pulse Width High Notes: NR (1) 100 ns 1. NR = No Restriction 2. All byte write operations must be preceded by the SDP command sequence. 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 16. Page Mode Characteristics Symbol Parameter tWC Write Cycle Time tAS Address Set-up Time tAH Min Max Units 10 ms 0 ns Address Hold Time 100 ns tDS Data Set-up Time 100 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 100 100 µs ns 17. Write Algorithm(1) LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA A0 TO ADDRESS 1555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS Notes: ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 2. Data protect state will be re-activated at the end of the write cycle. 3. 1 to 64 bytes of data are loaded. 9 0299I–PEEPR–4/09 18. Software Data Protection Write Cycle Waveforms(1)(2)(3) Notes: 1. A0 - A12 must conform to the addressing sequence for the first three bytes as shown above. 2. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 3. OE must be high only when WE and CE are both low. 19. Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min OE to Output Delay tWR Write Recovery Time Notes: Max Units 0 ns 0 ns (2) tOE Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 20. Data Polling Waveforms 10 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 21. Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tOEHP OE High Pulse tWR Write Recovery Time Notes: Min Typ Max Units ns 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 22. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used, but the address should not vary. 11 0299I–PEEPR–4/09 23. Ordering Information 23.1 Green Package Option (Pb/Halide-free) ICC (mA) tACC (ns) Active Standby 200 15 0.05 23.2 Ordering Code Package AT28BV64B-20JU AT28BV64B-20SU AT28BV64B-20TU 32J 28S 28T Operation Range Industrial (-40°C to 85°C) Die Products Contact Atmel Sales in regards to die and wafer sales. Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) 12 AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 24. Packaging Information 24.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 E E2 B1 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B 13 0299I–PEEPR–4/09 24.2 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0.32(0.0125) 0.23(0.0091) 0º ~ 8º 1.27(0.050) 0.40(0.016) 8/4/03 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. REV. 28S B AT28BV64B 0299I–PEEPR–4/09 AT28BV64B 24.3 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 NOTE 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC 12/06/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 28T C 15 0299I–PEEPR–4/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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