ON MC74HC4060ADT 14-stage binary ripple counter with oscillator Datasheet

MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
High–Performance Silicon–Gate CMOS
The MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip–flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative–going edge of
the Osc In. The active–high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand–by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
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MARKING
DIAGRAMS
16
PDIP–16
N SUFFIX
CASE 648
16
MC74HC4060AN
AWLYYWW
1
1
16
SO–16
D SUFFIX
CASE 751B
16
HC4060A
AWLYWW
1
1
16
HC40
60A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
Pinout: 16–Lead Plastic Package (Top View)
VCC
16
Q10
Q8
Q9
15
14
13
10
Osc Osc
Reset Osc In Out 1 Out 2
12
11
10
9
Osc In
1
2
3
4
5
6
7
8
Q12
Q13
Q14
Q6
Q5
Q7
Q4
GND
Reset
FUNCTION TABLE
Clock
Reset
Output State
X
L
L
H
No Charge
Advance to Next State
All Outputs Are Low
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 2
11
12
9
7
5
4
6
14
13
15
1
2
3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
Pin 16 = VCC
Pin 8 = GND
ORDERING INFORMATION
Device
1
Package
Shipping
MC74HC4060AN
PDIP–16
2000 / Box
MC74HC4060AD
SOIC–16
48 / Rail
MC74HC4060ADR2
SOIC–16
2500 / Reel
MC74HC4060ADT
TSSOP–16
96 / Rail
MC74HC4060ADTR2
TSSOP–16
2500 / Reel
Publication Order Number:
MC74HC4060A/D
MC74HC4060A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature Range
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
Max
Unit
2.5*
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested
at 2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1V or VCC –0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1V or VCC – 0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout| ≤ 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
Vin =VIH or VIL
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2
MC74HC4060A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
VOL
Parameter
Condition
Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)
Vin = VIH or VIL
|Iout| ≤ 20µA
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
Vin = VIH or VIL
VOH
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout| ≤ 20µA
|Iout| ≤ 0.7mA
|Iout| ≤ 1.0mA
|Iout| ≤ 1.3mA
Vin =VCC or GND
VOL
Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
|Iout| ≤ 20µA
|Iout| ≤ 0.7mA
|Iout| ≤ 1.0mA
|Iout| ≤ 1.3mA
Vin =VCC or GND
Iin
ICC
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
V
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
10
30
50
9.0
14
28
45
8.0
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
300
180
60
51
375
200
75
64
450
250
90
75
ns
tPLH,
tPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
500
350
250
200
750
450
275
220
1000
600
300
250
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
195
75
39
33
245
100
49
42
300
125
61
53
ns
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
75
60
15
13
95
75
19
16
125
95
24
20
ns
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MC74HC4060A
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) – continued
Symbol
tTLH,
tTHL
Cin
Parameter
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Maximum Input Capacitance
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n–1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
pF
35
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
100
75
20
17
125
100
25
21
150
120
30
25
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
trec
tr, tf
Parameter
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
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MC74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
6, Osc Out 2 must be left open circuited.
Negative–edge triggering clock input. A high–to–low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
SWITCHING WAVEFORMS
tf
tw
tr
90%
50%
10%
Osc In
Reset
VCC
GND
tPHL
GND
tw
1/fMAX
Q
tPHL
tPLH
Q
VCC
50%
90%
50%
10%
50%
trec
tTLH
Osc In
tTHL
GND
Figure 1.
Figure 2.
TEST
POINT
VCC
Qn
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Qn+1
VCC
50%
tPHL
CL*
50%
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
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5
MC74HC4060A
Q4
Q5
7
Osc Out 1
Osc In
Reset
Q13
Q14
1
2
3
C
Q
C
Q
C
Q
C
Q
C
Q
C
C
Q
C
Q
C
Q
C
Q
C
Q
C
R
Osc Out 2
5
Q12
Q
R
9
Q6 = Pin 4
Q7 = Pin 6
Q8 = Pin 14
Q9 = Pin 13
10
Q10 = Pin 15
VCC = Pin 16
GND = Pin 8
11
12
Figure 5. Expanded Logic Diagram
Reset
For 2.0V ≤ VCC ≤ 6.0V
10Rtc > RS > 2Rtc
400Hz ≤ f ≤ 400Khz:
12
Osc In
11
Osc Out 1
10
Osc Out 2
9
f
Rtc
RS
Ctc
[ 3 R1tcCtc (f in Hz, Rtc in ohms, Ctc in farads)
The formula may vary for other frequencies.
Figure 6. Oscillator Circuit Using RC Configuration
Reset
12
Osc In
11
Osc Out 1
10
Rf
R1
C1
C2
Figure 7. Pierce Crystal Oscillator Circuit
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6
9
Osc Out 2
MC74HC4060A
TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)
Type
Positive Reactance (Pierce)
Input Resistance, Rin
60MΩ Minimum
Output Impedance, Zout (4.5V Supply)
200Ω (See Text)
Input Capacitance, Cin
5pF Typical
Output Capacitance, Cout
7pF Typical
Series Capacitance, Ca
5pF Typical
Open Loop Voltage Gain with Output at Full Swing, α
3Vdc Supply
4Vdc Supply
5Vdc Supply
6Vdc Supply
5.0 Expected Minimum
4.0 Expected Minimum
3.3 Expected Minimum
3.1 Expected Minimum
PIERCE CRYSTAL OSCILLATOR DESIGN
RS
1
2
LS
CS
1
2
1
Re
Xe
2
CO
Value are supplied by crystal manufacturer (parallel resonant crystal).
Figure 8. Equivalent Crystal Networks
RS
–jXC2
R
Rload
Ca
–jXCo
jXLs
Xload
Zload
–jXCs
Cin
–jXC
Cout
NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of
the load. Ca and Rf typically have minimal effect below 2MHz.
Values are listed in Table 1.
Figure 9. Series Equivalent Crystal Load
Figure 10. Parasitic Capacitances of the Amplifier
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MC74HC4060A
DESIGN PROCEDURES
The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional
impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from
180°C.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.
Ze
+ **jXjXCCo)(RRs s))jXjXLsL**jXjXCCs) + Re ) jXe
o
s
s
Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum Rs for the crystal should be used in the equation.
Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is
the gain of the HC4060A amplifier.
Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load
capacitance of 32pF at the required frequency.
Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of
100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) – Rs where Ls and Rs are
crystal parameters.
Step 5: Simultaneously solve, using a computer,
b
@ XC2
+ R @ Re )XCXC2
(Xe * XC)
(with feedback phase shift = 180°)
+ XC2 ) XC ) ReRXC2 + XCload (where the loading capacitor is an external load, not including Co)
RXCoXC2 [(XC ) XC2)(XC ) XCo) * XC(XC ) XCo ) XC2)]
Rload +
X2C2(XC ) XCo)2 ) R2(XC ) XCo ) XC2)2
Xe
( Eq 1 )
( Eq 2 )
( Eq 3 )
Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.
Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that
Q = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.
CHOOSING R1
the first overtone. Rf must be large enough so as to not affect
Power is dissipated in the effective series resistance of the
the phase of the feedback network in an appreciable manner.
crystal. The drive level specified by the crystal manufacturer
ACKNOWLEDGEMENTS AND RECOMMENDED
is the maximum stress that a crystal can withstand without
REFERENCES
damage or excessive shift in frequency. R1 limits the drive
The following publications were used in preparing this
level.
data sheet and are hereby acknowledged and recommended
To verify that the maximum dc supply voltage does not
for reading:
overdrive the crystal, monitor the output frequency as a
Technical Note TN-24, Statek Corp.
function of voltage at Osc Out 2 (Pin 9). The frequency
Technical Note TN-7, Statek Corp.
should increase very slightly as the dc supply voltage is
D. Babin, “Designing Crystal Oscillators”, Machine
increased. An overdriven crystal will decrease in frequency
Design, March 7, 1985.
or become unstable with an increase in supply voltage. The
D. Babin, “Guidelines for Crystal Oscillator Design”,
operating supply voltage must be reduced or R1 must be
Machine Design, April 25, 1985.
increased in value if the overdriven condition exists. The
ALSO RECOMMENDED FOR READING:
user should note that the oscillator start-up time is
E. Hafner, “The Piezoelectric Crystal Unit-Definitions
proportional to the value of R1.
and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2,
SELECTING Rf
Feb., 1969.
The feedback resistor, Rf, typically ranges up to 20MΩ. Rf
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
determines the gain and bandwidth of the amplifier. Proper
Control”, Electro-Technology, June, 1969.
bandwidth insures oscillation at the correct frequency plus
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
roll-off to minimize gain at undesirable frequencies, such as
Design, May, 1966.
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8
MC74HC4060A
1
2
4
8
16
32
64
128
256
Clock
Reset
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
Figure 11. Timing Diagram
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9
512
1024
2048
4096
8192
16384
MC74HC4060A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A
–
16
9
1
8
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
0.250 0.270
6.85
6.35
0.145 0.175
4.44
3.69
0.015 0.021
0.53
0.39
0.040 0.070
1.77
1.02
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.008 0.015
0.38
0.21
0.110 0.130
3.30
2.80
0.295 0.305
7.74
7.50
10°
0°
10°
0°
0.020 0.040
1.01
0.51
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
16
9
1
8
–B
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 8 PL
0.25 (0.010)
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
http://onsemi.com
10
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
MC74HC4060A
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
G
http://onsemi.com
11
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC4060A
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MC74HC4060A/D