CAT24C44 256-Bit Serial Nonvolatile CMOS Static RAM FEATURES ■ Single 5V Supply ■ JEDEC Standard Pinouts: –8-pin DIP –8-pin SOIC ■ Infinite EEPROM to RAM Recall ■ CMOS and TTL Compatible I/O ■ 100,000 Program/Erase Cycles (EEPROM) ■ Low CMOS Power Consumption: ■ Auto Recall on Power-up –Active: 3 mA Max. –Standby: 30 µA Max. ■ Commercial, Industrial and Automotive Temperature Ranges ■ Power Up/Down Protection ■ "Green" Package Options Available ■ 10 Year Data Retention DESCRIPTION The CAT24C44 Serial NVRAM is a 256-bit nonvolatile memory organized as 16 words x 16 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy transfer of data from RAM array to EEPROM (STORE) and from EEPROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5µs. The CAT24C44 features unlimited RAM write operations either through external RAM writes or internal recalls from EEPROM. Internal false store protection circuitry prohibits STORE operations when VCC is less than 3.5V (typical) ensuring EEPROM data integrity. PIN CONFIGURATION PIN FUNCTIONS The CAT24C44 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (EEPROM) and has a data retention of 10 years. The device is available in JEDEC approved 8-pin plastic DIP and SOIC packages. Pin Name DIP Package (P, L, GL) CE SK DI DO 1 2 3 4 8 7 6 5 SOIC Package (S, V, GV) VCC CE STORE SK RECALL DI VSS DO © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 2 3 4 8 7 6 5 VCC STORE RECALL VSS 1 Function SK Serial Clock DI Serial Input DO Serial Data Output CE Chip Enable RECALL Recall STORE Store VCC +5V VSS Ground Doc. No. 1083, Rev. R CAT24C44 BLOCK DIAGRAM EEPROM ARRAY RECALL ROW DECODE STATIC RAM ARRAY 256-BIT STORE STORE CONTROL LOGIC RECALL CE INSTRUCTION REGISTER DI COLUMN DECODE DO SK VCC VSS INSTRUCTION DECODE 4-BIT COUNTER MODE SELECTION(1)(2) Mode STORE RECALL Software Instruction Write Enable Latch Previous Recall Latch Hardware Recall(3) 1 0 NOP X X Software Recall 1 1 RCL X X Hardware Store(3) 0 1 NOP SET TRUE Software Store 1 1 STO SET TRUE X = Don’t Care POWER-UP TIMING(4) Symbol Parameter Min. Max. Units VCCSR VCC Slew Rate 0.5 0.005 V/m tpur Power-Up to Read Operations 200 µs tpuw Power-Up to Write or Store Operation 5 ms Note: (1) The store operation has priority over all the other operations. (2) The store operation is inhibited when VCC is below ≈ 3.5V. (3) NOP designates that the device is not currently executing an instruction. (4) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1083, Rev. R 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ............. –2.0 to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter NEND(1) Endurance TDR(1) Data Retention VZAP(1) ILTH(1)(4) Min. Typ. Max. Units 100,000 Cycles/Byte 10 Years ESD Susceptibility 2000 Volts Latch-up 100 mA D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter ICCO Min. Typ. Max. Unit Conditions Current Consumption (Operating) 3 mA Inputs = 5.5V, TA = 0°C All Outputs Unloaded ISB Current Consumption (Standby) 30 µA CE = VIL ILI Input Current 2 µA 0 ≤ VIN ≤ 5.5V ILO Output Leakage Current 10 µA 0 ≤ VOUT ≤ 5.5V VIH High Level Input Voltage 2 VCC V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage 2.4 0.4 V IOH = –2mA V IOL = 4.2mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O (1) CIN(1) Parameter Max. Unit Conditions Input/Output Capacitance 10 pF VI/O = 0V Input Capacitance 6 pF VIN = 0V Note: (1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1083, Rev. R CAT24C44 A.C. CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Symbol Parameter Min. Max. Units 1 MHz Conditions FSK SK Frequency DC tSKH SK Positive Pulse Width 400 ns tSKL SK Negative Pulse Width 400 ns CL = 100pF + 1TTL gate tDS Data Setup Time 400 ns VOH = 2.2V, VOL = 0.65V tDH Data Hold Time 80 ns VIH = 2.2V, VIL = 0.65V tPD SK Data Valid Time 375 ns Input rise and fall times = 10ns tZ CE Disable Time 1 µs tCES CE Enable Setup Time 800 ns tCEH CE Enable Hold Time 400 ns tCDS CE De-Select Time 800 ns A.C. CHARACTERISTICS, Store Cycle VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter tST Store Time tSTP Store Pulse Width tSTZ Store Disable Time Min. Max. Units Conditions 10 ms CL = 100pF + 1TTL gate ns VOH = 2.2V, VOL = 0.65V 100 ns VIH = 2.2V, VIL = 0.65V Max. Units Conditions 200 A.C. CHARACTERISTICS, Recall Cycle VCC = 5V ±10%, unless otherwise specified. Symbol Parameter Min. tRCC Recall Cycle Time 2.5 µs tRCP Recall Pulse Width 500 ns CL = 100pF + 1TTL gate tRCZ Recall Disable Time ns VOH = 2.2V, VOL = 0.65V tORC Recall Enable Time ns VIH = 2.2V, VIL = 0.65V tARC Recall Data Access Time 500 10 1.5 µs INSTRUCTION SET Format Instruction Start Bit Address OP Code Operation WRDS 1 XXXX 000 Reset Write Enable Latch (Disables, Writes and Stores) STO 1 XXXX 001 Store RAM Data in EEPROM WRITE 1 AAAA 011 Write Data into RAM Address AAAA WREN 1 XXXX 100 Set Write Enable Latch (Enables, Writes and Stores) RCL 1 XXXX 101 Recall EEPROM Data into RAM READ 1 AAAA 11X Read Data From RAM Address AAAA X = Don’t care A = Address bit Doc. No. 1083, Rev. R 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 from the device: If the CE pin is prematurely deselected while shifting in an instruction, that instruction will not be executed, and the shift register internal to the CAT24C44 will be cleared. If there are more than or less than 16 clocks during a memory data transfer, an improper data transfer will result. The SK clock is completely static allowing the user to stop the clock and restart it to resume shifting of data. DEVICE OPERATION The CAT24C44 is intended for use with standard microprocessors. The CAT24C44 is organized as 16 registers by 16 bits. Seven 8-bit instructions control the device’s operating modes, the RAM reading and writing, and the EEPROM storing and recalling. It is also possible to control the EEPROM store and recall functions in hardware with the STORE and RECALL pins. The CAT24C44 operates on a single 5V supply and will generate, on chip, the high voltage required during a RAM to EEPROM storing operation. Read Upon receiving a start bit, 4 address bits, and the 3-bit read command (clocked into the DI pin), the DO pin of the CAT24C44 will come out of the high impedance state and the 16 bits of data, located at the address specified in the instructions, will be clocked out of the device. When clocking data from the device, the first bit clocked out (DO) is timed from the falling edge of the 8th clock, all succeeding bits (D1–D15) are timed from the rising edge of the clock. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin remains in a high impedance state except when outputting data from the device. The CE (Chip Enable) pin must remain high during the entire data transfer. The format for all instructions sent to the CAT24C44 is a logical ‘1’ start bit, 4 address bits (data read or write operations) or 4 “Don’t Care” bits (device mode operations), and a 3-bit op code (see Instruction Set). For data write operations, the 8-bit instruction is followed by 16 bits of data. For data read instructions, DO will come out of the high impedance state and enable 16 bits of data to be clocked from the device. The 8th bit of the read instruction is a “Don’t Care” bit. This is to eliminate any bus contention that would occur in applications where the DI and DO pins are tied together to form a common DI/DO line. A word of caution while clocking data to and Write After receiving a start bit, 4 address bits, and the 3-bit WRITE command, the 16-bit word is clocked into the device for storage into the RAM memory location specified. The CE pin must remain high during the entire write operation. Figure 1. RAM Read Cycle Timing CE 1 2 3 4 5 6 7 1 A A A AX 1 1 8 9 10 11 12 22 23 24 SK (1) (8) DI HIGH-Z DO D0 D1 D2 D3 D14 D15 D0 Figure 2. RAM Write Cycle Timing CE 1 2 3 4 5 6 7 1 A A A A1 0 1 8 9 10 11 12 22 23 24 SK DI D0 D1 D2 D3 D13 D14 D15 Note: (1) Bit 8 of READ instruction is “Don’t Care”. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1083, Rev. R CAT24C44 WREN/WRDS The WRDS (write/store disable) can be used to disable all CAT24C44 programming functions, and will prevent any accidental writing to the RAM, or storing to the EEPROM. The CAT24C44 powers up in the program disable state (the “write enable latch” is reset). Any programming after power-up or after a WRDS (RAM write/EEPROM store disable) instruction must first be preceded by the WREN (RAM write/EEPROM store enable) instruction. Once writing/storing is enabled, it will remain enabled until power to the device is removed, the WRDS instruction is sent, or an EEPROM store has been executed (STO). Data can be read normally from the CAT24C44 regardless of the “write enable latch” status. Figure 3. Read Cycle Timing 6 SK CYCLE # 7 8 9 10 11 SK VIH CE tPD DI tPD tZ HIGH-Z DO D0 D1 Dn HIGH-Z Figure 4. Write Cycle Timing 1/FSK tSKH SK x tSKL 1 2 n tCES tCEH tCDS CE tDS tDH DI Doc. No. 1083, Rev. R 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24C44 RECALL RCL/RECALL inadvertent store operations, the following conditions must each be met before data can be transferred into nonvolatile storage: Data is transferred from the EEPROM data memory to RAM by either sending the RCL instruction or by pulling the RECALL input pin low. A recall operation must be performed before the EEPROM store, or RAM write operations can be executed. Either a hardware or software recall operation will set the “previous recall” latch internal to the CAT24C44. • The “previous recall” latch must be set (either a software or hardware recall operation). • The “write enable” latch must be set (WREN instruction issued). POWER-ON RECALL • STO instruction issued or STORE input low. The CAT24C44 has a power-on recall function that transfers the EEPROM data to the RAM. After Powerup, all functions are inhibited for at least 200ns (Tpur) from stable Vcc. During the store operation, all other CAT24C44 functions are inhibited. Upon completion of the store operation, the “write enable” latch is reset. The device also provides false store protection whenever VCC falls below a 3.5V level. If VCC falls below this level, the store operation is disabled and the “write enable” latch is reset. STORE STO/STORE Data in the RAM memory area is stored in the EEPROM memory either by sending the STO instruction or by pulling the STORE input pin low. As security against any Figure 5. Recall Cycle Timing tRCC tRCP RECALL tRCZ tARC HIGH-Z DO VALID DATA tORC UNDEFINED DATA Figure 6. Hardware Store Cycle Timing tST tSTP STORE tSTZ HIGH-Z DO © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1083, Rev. R CAT24C44 Figure 7. Non-Data Operations CE 1 2 3 4 5 1 X X X X 6 7 8 SK DI OP-CODE ORDERING INFORMATION Prefix Device # CAT 24C44 Optional Company ID Product Number Suffix S I Temperature Range Blank = Commercial (0˚C to 70˚C) I = Industrial (-40˚C to 85˚C) A = Automotive (-40˚C to 105˚C) E = Extended (-40˚C to 125˚C) -TE13 Tape & Reel Package P: PDIP S: SOIC, JEDEC L: PDIP (Lead-free, Halogen-free) V: SOIC, JEDEC (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) Notes: (1) The device used in the above example is a CAT24C44SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Doc. No. 1083, Rev. R 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date Revision Comments 04/17/2004 O Add Lead Free Logo Update Features Update Pin Configuration Update Block Diagram Update Instruction Set Update Device Operation Update Ordering Information Add Revision History Update Rev Number 11/16/2004 P Update Pin Configuration Update Ordering Information 04/17/2004 Q Update Ordering Information 08/03/2005 R Update Pin Configuration Update Reliability Characteristics Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com Publication #: Revison: Issue date: 1083 R 08/03/05