Intersil ISL62875 Pwm dc/dc controller with vid inputs for portable gpu core-voltage regulator Datasheet

ISL62875
Features
The ISL62875 is a Single-Phase Synchronous-Buck
PWM voltage regulator featuring Intersil’s Robust Ripple
Regulator (R3) Technology™. The wide 3.3V to 25V
input voltage range is ideal for systems that run on
battery or AC-adapter power sources. The ISL62875 is a
low-cost solution for applications requiring dynamically
selected slew-rate controlled output voltages. The
soft-start and dynamic setpoint slew-rates are capacitor
programmed. Voltage identification logic-inputs select
four resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter
between 0.5V to 1.5V, and up to 3.3V using a feedback
voltage divider. Robust integrated MOSFET drivers and
Schottky bootstrap diode reduce the implementation
area and component cost.
• Input Voltage Range: 3.3V to 25V
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The
PWM frequency is 500kHz during static operation,
becoming variable during changes in load, setpoint
voltage, and input voltage when changing between
battery and AC-adapter power. The modulators ability to
change the PWM switching frequency during these
events in conjunction with external loop compensation
produces superior transient response. For maximum
efficiency, the converter automatically enters diodeemulation mode (DEM) during light-load conditions such
as system standby.
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID Selects Four Independent Setpoint
Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• Fixed 500kHz PWM Frequency in Continuous
Conduction
• Integrated High-current MOSFET Drivers and
Schottky Boot-Strap Diode for Optimal Efficiency
Applications*(see page 21)
• Mobile PC GPU Core Power
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Tablet PCs/Slates and Netbooks
• Hand-Held Portable Instruments
Related Literature*(see page 21)
• TB389 “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
Typical Application
+5V
VIN
3.3V TO 25V
1
5
GPIO
6
7
8
9
LGATE
PVCC
EN
UGATE
VID1
PHASE
SET0
OCSET
SET1
RSET4
CSOFT
RSET1 RSET2 RSET3
1
17
LO
16
QLS
VO
FB
CBOOT
14
13
12
GPIO
VOUT
0.5V TO 3.3V
COUT
COCSET
RO
VCC
RPGOOD
10 11
FN6905.1
September 18, 2009
QHS
18
VID0
SREF
CIN
19
RCOMP
ROFS
4
VCC
BOOT
GND
SET2
3
PGND
PGOOD
2
CVCC
20
ROCSET
CPVCC
CCOMP
RFB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL62875
PWM DC/DC Controller with VID Inputs for
Portable GPU Core-Voltage Regulator
ISL62875
Application Schematics
RVCC
SREF
SET0
16
6
15
7
14
8
13
9
RSET2
RSET3
RSET4
CSOFT
RSET1
PVCC
5
SET2
SET1
17
12
CINB
QHS
BOOT
UGATE
LO
PHASE
QLS
NC
OCSET
CBOOT
VO
COB
COCSET
FB
RO
RCOMP
VCC
GPIO
VOUT
0.5V TO 3.3V
COC
ROCSET
VID0
4
CINC
VCC
CCOMP
RFB
ROFS
GPIO
18
11
VID1
19
3
PGOOD
EN
2
CVCC
RPGOOD
GND
10
PGND
1
CPVCC
VIN
3.3V TO 25V
20
LGATE
+5V
FIGURE 1. ISL62875 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT
SENSE
RVCC
SET0
RSET2
16
6
15
7
14
8
13
9
RSET3
RSET4
CSOFT
RSET1
PVCC
5
SET2
SET1
17
12
CINB
QHS
BOOT
UGATE
LO
RSNS
PHASE
QLS
NC
OCSET
ROCSET
SREF
4
CINC
VCC
CBOOT
VO
FB
RCOMP
VCC
GPIO
VOUT
0.5V TO 3.3V
COC
COB
COCSET
RO
ROFS
VID0
18
11
GPIO
19
3
PGOOD
EN
VID1
CVCC
RPGOOD
GND
2
10
PGND
1
CPVCC
VIN
3.3V TO 25V
20
LGATE
+5V
CCOMP
RFB
FIGURE 2. ISL62875 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR
CURRENT SENSE
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September 18, 2009
FN6905.1
ISL62875
Application Schematics (Continued)
RVCC
VID0
EXT_REF
CSOFT
SREF
SET0
SET1
4
17
5
16
6
15
7
14
8
13
9
12
GPIO
CINB
QHS
BOOT
UGATE
LO
PHASE
QLS
NC
OCSET
CBOOT
VO
FB
VOUT
0.5V TO 3.3V
COC
COB
COCSET
RO
RCOMP
ROFS
RPGOOD
PVCC
18
SET2
VCC
19
CINC
VCC
ROCSET
VID1
CVCC
3
11
EN
GPIO
2
VIN
3.3V TO 25V
PGOOD
GND
10
PGND
20
CPVCC
1
LGATE
+5V
CCOMP
RFB
FIGURE 3. ISL62875 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
3
September 18, 2009
FN6905.1
Block Diagram
EN
VCC
100kΩ
POR
FAULT
4
−
EA
+
FB
VW
VCOMP
BOOT
RUN
RUN
PWM
H
L
IN
DRIVER
UGATE
PHASE
SHOOT-THROUGH
PROTECTION
OTP
PVCC
PWM
RUN
DRIVER
LGATE
100pF
PGND
gmVIN
+
VCC
+
−
−
ISL62875
VSET
Cr
VR
SW0
+
SREF
SW1
SET0
gmVO
SW2
−
SET1
SW3
SET2
VID1
VID DECODER
VID0
EXT
VREF
GND
500mV
INT
SW4
−
OCP
+
FB
−
UVP
+
FAULT
September 18, 2009
FN6905.1
FIGURE 4. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62875
VO
OCSET
IOCSET
10µA
PGOOD
ISL62875
Pin Configuration
2 PVCC
PGND 2
1 LGATE
ISL62875
(20 LD 3.2X1.8 µTQFN)
TOP VIEW
19 VCC
18 BOOT
GND 3
VID1 5
16 PHASE
VID0 6
15 NC
SREF 7
14 OCSET
SET0 8
13 VO
SET1 9
12 FB
PGOOD 11
17 UGATE
SET2 10
EN 4
ISL62875 Functional Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of
the converter.
2
PGND
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
3
GND
4
EN
5
VID1
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four
setpoint reference voltages.
6
VID0
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among
four setpoint reference voltages. External reference input when enabled by connecting the
SET0 pin to the VCC pin.
7
SREF
Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage
programming resistor input. Connects internally to the inverting input of the VSET voltage
setpoint amplifier.
8
SET0
Voltage set-point programming resistor input.
9
SET1
Voltage set-point programming resistor input.
10
SET2
Voltage set-point programming resistor input.
11
PGOOD
Power-good open-drain indicator output. This pin changes to high impedance when the
converter is able to supply regulated voltage. The pull-down resistance between the PGOOD
pin and the GND pin identifies which protective fault has shut down the regulator.
12
FB
Voltage feedback sense input. Connects internally to the inverting input of the control-loop
error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage
on the SREF pin. The control loop compensation network connects between the FB pin and the
converter output.
13
VO
Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input
for the overcurrent detection circuit.
IC ground for bias supply and signal reference.
Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the
soft-start sequence.
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September 18, 2009
FN6905.1
ISL62875
ISL62875 Functional Pin Descriptions (Continued)
PIN
NUMBER
SYMBOL
14
OCSET
15
NC
16
PHASE
Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3
modulator. Inductor current polarity detector input. Connect to junction of output inductor,
high-side MOSFET, and low-side MOSFET. See Figures 1 and 2 on page 2.
17
UGATE
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET
of the converter.
18
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the
BOOT pin and the PHASE pin.
19
VCC
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1µF
MLCC to the GND pin. See “Application Schematics” (Figures 1 and 2) on page 2.
20
PVCC
DESCRIPTION
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor
ROCSET connects from this pin to the sense node.
No internal connection. Pin 15 should be connected to the GND pin.
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected
to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple
with a 10µF MLCC to the PGND pin. See “Application Schematics” (Figures 1 and 2) on page 2.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
ISL62875HRUZ-T*
GAR
TEMP RANGE
(°C)
-10 to +100
PACKAGE
(Pb-Free)
20 Ld 3.2x1.8 µTQFN (Tape and Reel)
PKG. DWG. #
L20.3.2x1.8
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62875. For more information on MSL please
see techbrief TB363.
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September 18, 2009
FN6905.1
ISL62875
Table of Contents
Application Schematics ....................................................................................................................... 2
Block Diagram .................................................................................................................................... 4
Pin Configuration ................................................................................................................................ 5
ISL62875 Functional Pin Descriptions ................................................................................................ 5
Ordering Information ......................................................................................................................... 6
Absolute Maximum Ratings ................................................................................................................ 8
Thermal Information .......................................................................................................................... 8
Recommended Operating Conditions .................................................................................................. 8
Electrical Specifications ...................................................................................................................... 8
Theory of Operation .......................................................................................................................... 11
Modulator ......................................................................................................................................
Synchronous Rectification .................................................................................................................
Diode Emulation ..............................................................................................................................
Power-On Reset ..............................................................................................................................
VIN and PVCC Voltage Sequence .......................................................................................................
Start-Up Timing ..............................................................................................................................
PGOOD Monitor ...............................................................................................................................
LGATE and UGATE MOSFET Gate-Drivers ............................................................................................
Adaptive Shoot-Through Protection ....................................................................................................
11
11
11
12
12
12
12
12
12
Setpoint Reference Voltage Programming ........................................................................................ 13
Calculating Setpoint Voltage Programming Resistor Values ................................................................... 13
External Setpoint Reference .............................................................................................................. 14
Soft-Start and Voltage-Step Delay .................................................................................................... 14
Circuit Description ........................................................................................................................... 14
Component Selection For CSOFT Capacitor .......................................................................................... 15
Compensation Design ....................................................................................................................... 15
Fault Protection ................................................................................................................................ 15
Overcurrent ....................................................................................................................................
Component Selection for ROCSET and CSEN .........................................................................................
Overvoltage ....................................................................................................................................
Undervoltage ..................................................................................................................................
Over-Temperature ...........................................................................................................................
15
16
16
16
16
General Application Design Guide ..................................................................................................... 16
Selecting the LC Output Filter ...........................................................................................................
Selection of the Input Capacitor ........................................................................................................
Selecting The Bootstrap Capacitor .....................................................................................................
Driver Power Dissipation ..................................................................................................................
MOSFET Selection and Considerations ................................................................................................
17
17
17
18
18
PCB Layout Considerations ............................................................................................................... 19
Power and Signal Layers Placement on the PCB ...................................................................................
Component Placement .....................................................................................................................
Signal Ground and Power Ground ......................................................................................................
Routing and Connection Details .........................................................................................................
Copper Size for the Phase Node ........................................................................................................
19
19
19
19
20
Revision History ............................................................................................................................... 21
Products ........................................................................................................................................... 21
Package Outline Drawing ................................................................................................................. 22
7
September 18, 2009
FN6905.1
ISL62875
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, PGOOD to GND . . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, SET0, SET1, SET2, VO,
VID0, VID1, FB, OCSET, SREF . . . -0.3V to GND, VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . -0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE) . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Thermal Resistance (Typical)
θJA (°C/W)
20 Ld µTQFN Package (Notes 4, 5) . . . . . . . .
84
Junction Temperature Range . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range . . . . . . . . . . -10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . -10°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C.
MIN
MAX
(Note 7) TYP (Note 7) UNIT
SYMBOL
TEST CONDITIONS
VCC Input Bias Current
IVCC
EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB
-
1.1
1.5
mA
VCC Shutdown Current
IVCCoff
EN = GND, VCC = 5V
-
0.1
1.0
µA
PVCC Shutdown Current
IPVCCoff
EN = GND, PVCC = 5V
-
0.1
1.0
µA
VCC and PVCC
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
VVCC_THR
4.40
4.49
4.60
V
Falling VCC POR Threshold Voltage
V
4.10
4.22
4.35
V
-
0.50
-
V
-0.75
-
+0.75
%
450
500
550
kHz
0
-
3.6
V
EN = 5V
-
600
-
kΩ
VCC_THF
REGULATION
Reference Voltage
VREF(int)
System Accuracy
VID0 = VID1 = GND, PWM Mode = CCM
PWM
Switching Frequency
FSW
PWM Mode = CCM
VO
VO Input Voltage Range
VVO
VO Input Impedance
RVO
VO Reference Offset Current
IVOSS
VENTHR < EN, SREF = Soft-Start Mode
-
10
-
µA
VO Input Leakage Current
IVOoff
EN = GND, VO = 3.6V
-
0.1
-
µA
EN = 5V, FB = 0.50V
-20
-
+50
nA
Nominal SREF Setting with 1% Resistors
0.5
-
1.5
V
SREF = Soft-Start Mode
10
20
30
µA
ERROR AMPLIFIER
FB Input Bias Current
IFB
SREF
SREF Operating Voltage Range
Soft-Start Current
VSREF
ISS
8
September 18, 2009
FN6905.1
ISL62875
Electrical Specifications
PARAMETER
These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C. (Continued)
SYMBOL
Voltage Step Current
IVS
TEST CONDITIONS
SREF = Setpoint-Stepping Mode
MIN
MAX
(Note 7) TYP (Note 7) UNIT
±60
±100
±140
µA
0
-
1.5
V
-0.5
-
+0.5
%
EXTERNAL REFERENCE
EXTREF Operating Voltage Range
EXTREF Accuracy
VEXT
SET0 = VCC
VEXT_OFS SET0 = VCC, VID0 = 0V to 1.5V
POWER GOOD
PGOOD Pull-down Impedance
PGOOD Leakage Current
RPG_SS
PGOOD = 5mA Sink
75
95
150
Ω
RPG_UV
PGOOD = 5mA Sink
75
95
150
Ω
RPG_OV
PGOOD = 5mA Sink
50
65
90
Ω
RPG_OC
PGOOD = 5mA Sink
25
35
50
Ω
-
0.1
1.0
µA
-
5.0
-
mA
IPG
PGOOD Maximum Sink Current
(Note 6)
PGOOD = 5V
IPG_max
GATE DRIVER
UGATE Pull-Up Resistance (Note 6)
RUGPU
200mA Source Current
-
1.0
1.5
Ω
UGATE Source Current (Note 6)
IUGSRC
UGATE - PHASE = 2.5V
-
2.0
-
A
UGATE Sink Resistance (Note 6)
RUGPD
250mA Sink Current
-
1.0
1.5
Ω
UGATE Sink Current (Note 6)
IUGSNK
UGATE - PHASE = 2.5V
-
2.0
-
A
LGATE Pull-Up Resistance (Note 6)
RLGPU
250mA Source Current
-
1.0
1.5
Ω
LGATE Source Current (Note 6)
ILGSRC
LGATE - GND = 2.5V
-
2.0
-
A
LGATE Sink Resistance (Note 6)
RLGPD
250mA Sink Current
-
0.5
0.9
Ω
LGATE Sink Current (Note 6)
ILGSNK
LGATE - PGND = 2.5V
-
4.0
-
A
UGATE to LGATE Deadtime
tUGFLGR UGATE falling to LGATE rising, no load
-
21
-
ns
LGATE to UGATE Deadtime
tLGFUGR LGATE falling to UGATE rising, no load
-
21
-
ns
RPHASE
-
33
-
kΩ
PHASE
PHASE Input Impedance
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
-
0.58
-
V
Reverse Leakage
IR
VR = 25V
-
0.2
-
µA
CONTROL INPUTS
EN High Threshold Voltage
VENTHR
2.0
-
-
V
EN Low Threshold Voltage
VENTHF
-
-
1.0
V
1.5
2.0
2.5
µA
-
0.1
1.0
µA
EN Input Bias Current
IEN
EN Leakage Current
IENoff
EN = 5V
EN = GND
VID<0,1> High Threshold Voltage
VVIDTHR
0.6
-
-
V
VID<0,1> Low Threshold Voltage
VVIDTHF
-
-
0.5
V
-
0.5
-
µA
-
0
-
µA
VID<0,1> Input Bias Current
VID<0,1> Leakage Current
IVID
IVIDoff
9
EN = 5V, VVID = 1V
September 18, 2009
FN6905.1
ISL62875
Electrical Specifications
PARAMETER
These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C. (Continued)
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNIT
PROTECTION
OCP Threshold Voltage
VOCPTH
OCP Reference Current
IOCP
OCSET Input Resistance
VOCSET - VO
-1.75
-
1.75
mV
EN = 5.0V
9.0
10
11
µA
ROCSET
EN = 5.0V
-
600
-
kΩ
OCSET Leakage Current
IOCSET
EN = GND
-
0
-
µA
UVP Threshold Voltage
VUVTH
VFB = %VSREF
81
84
87
%
OTP Rising Threshold Temperature
(Note 6)
TOTRTH
-
150
-
°C
OTP Hysteresis (Note 6)
TOTHYS
-
25
-
°C
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
10
September 18, 2009
FN6905.1
ISL62875
Theory of Operation
The modulator features Intersil’s R3 Robust-RippleRegulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The
PWM frequency is maintained at 500kHz under static
continuous-conduction-mode operation within the entire
specified envelope of input voltage, output voltage, and
output load. If the application should experience a rising
load transient and/or a falling line transient such that the
output voltage starts to fall, the modulator will extend
the on-time and/or reduce the off-time of the PWM pulse
in progress. Conversely, if the application should
experience a falling load transient and/or a rising line
transient such that the output voltage starts to rise, the
modulator will truncate the on-time and/or extend the
off-time of the PWM pulse in progress. The period and
duty cycle of the ensuing PWM pulses are optimized by
the R3 modulator for the remainder of the transient and
work in concert with the error amplifier VERR to maintain
output voltage regulation. Once the transient has
dissipated and the control loop has recovered, the PWM
frequency returns to the nominal static 500kHz.
Modulator
The R3 modulator synthesizes an AC signal VR, which is
an analog representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The
current through CR is provided by a transconductance
amplifier gm that measures the input voltage (VIN) at the
PHASE pin and output voltage (VOUT) at the VO pin. The
positive slope of VR can be written as Equation 1:
V RPOS = ( g m ) ⋅ ( V IN – V OUT ) ⁄ C R
(EQ. 1)
The negative slope of VR can be written as Equation 2:
(EQ. 2)
V RNEG = g m ⋅ V OUT ⁄ C R
Where, gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the
error amplifier output voltage VCOMP, creating an
envelope into which the ripple voltage VR is compared.
The amplitude of VW is controlled internally by the IC.
The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold
voltage and VW is the higher threshold voltage. Figure 5
shows PWM pulses being generated as VR traverses the
VW and VCOMP thresholds. The PWM switching frequency
is proportional to the slew rates of the positive and
negative slopes of VR; it is inversely proportional to the
voltage between VW and VCOMP.
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction
through the output inductor when the high-side MOSFET
switches off for the balance of the PWM switching cycle.
Low conversion efficiency as a result of the conduction
loss of the diode makes this an unattractive option for all
but the lowest current applications. Efficiency is
dramatically improved when the free-wheeling diode is
11
replaced with a MOSFET that is turned on whenever the
high-side MOSFET is turned off. This modification to the
standard DC/DC buck regulator is referred to as
synchronous rectification, the topology implemented by
the ISL62875 controller.
RIPPLE CAPACITOR VOLTAGE CR
WINDOW VOLTAGE VW
ERROR AMPLIFIER VOLTAGE VCOMP
PWM
FIGURE 5. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Diode Emulation
The polarity of the output inductor current is defined as
positive when conducting away from the phase node,
and defined as negative when conducting towards the
phase node. The DC component of the inductor current is
positive, but the AC component known as the ripple
current, can be either positive or negative. Should the
sum of the AC and DC components of the inductor
current remain positive for the entire switching period,
the converter is in continuous-conduction-mode (CCM.)
However, if the inductor current becomes negative or
zero, the converter is in discontinuous-conduction-mode
(DCM.)
Unlike the standard DC/DC buck regulator, the
synchronous rectifier can sink current from the output
filter inductor during DCM, reducing the light-load
efficiency with unnecessary conduction loss as the lowside MOSFET sinks the inductor current. The ISL62875
controller avoids the DCM conduction loss by making the
low-side MOSFET emulate the current-blocking behavior
of a diode. This smart-diode operation called diodeemulation-mode (DEM) is triggered when the negative
inductor current produces a positive voltage drop across
the rDS(ON) of the low-side MOSFET for eight consecutive
PWM cycles while the LGATE pin is high. The converter
will exit DEM on the next PWM pulse after detecting a
negative voltage across the rDS(ON) of the low-side
MOSFET.
It is characteristic of the R3 architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is
proportional to the reduction of load current. Upon
entering DEM, the PWM frequency is forced to fall
approximately 30% by forcing a similar increase of the
September 18, 2009
FN6905.1
ISL62875
window voltage V W. This measure is taken to prevent
oscillating between modes at the boundary between CCM
and DCM. The 30% increase of VW is removed upon exit
of DEM, forcing the PWM switching frequency to jump
back to the nominal CCM value.
LGATE and UGATE MOSFET Gate-Drivers
Power-On Reset
The LGATE driver is optimized for low duty-cycle
applications where the low-side MOSFET experiences
long conduction times. In this environment, the low-side
MOSFETs require exceptionally low rDS(ON) and tend to
have large parasitic charges that conduct transient
currents within the devices in response to high dv/dt
switching present at the phase node. The drain-gate
charge in particular can conduct sufficient current
through the driver pull-down resistance that the VGS(th)
of the device can be exceeded and turned on. For this
reason the LGATE driver has been designed with low
pull-down resistance and high sink current capability to
ensure clamping the MOSFETs gate voltage below
VGS(th).
The IC is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR)
threshold voltage VVCC_THR. The controller will become
disabled when the voltage at the VCC pin decreases below
the falling POR threshold voltage VVCC_THF. The POR
detector has a noise filter of approximately 1µs.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the VENTHR rising threshold
voltage, the following criteria must be met:
- VPVCC is at least equivalent to the VCC rising
power-on reset voltage VVCC_THR
- VVIN must be 3.3V or the minimum required by the
application
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller
can be enabled by pulling the EN pin voltage above the
input-high threshold VENTHR. Approximately 20µs later,
the voltage at the SREF pin begins slewing to the
designated VID set-point. The converter output voltage
at the FB feedback pin follows the voltage at the SREF
pin. During soft-start, The regulator always operates in
CCM until the soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable
of supplying regulated voltage. The PGOOD pin is an
undefined impedance if the VCC pin has not reached the
rising POR threshold VVCC_THR, or if the VCC pin is below
the falling POR threshold VVCC_THF. The PGOOD
pull-down resistance corresponds to a specific protective
fault, thereby reducing troubleshooting time and effort.
Table 1 maps the pull-down resistance of the PGOOD pin
to the corresponding fault status of the controller.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft-Start or Undervoltage
95Ω
Overcurrent
35Ω
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of
the converter while the UGATE pin drives the high-side
MOSFET of the converter.
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver
output has fallen below approximately 1V. The dead-time
shown in Figure 6 is extended by the additional period
that the falling gate voltage remains above the 1V
threshold. The high-side gate-driver output voltage is
measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across
the LGATE and PGND pins. The power for the LGATE
gate-driver is sourced directly from the PVCC pin. The
power for the UGATE gate-driver is supplied by a bootstrap capacitor connected across the BOOT and PHASE
pins. The capacitor is charged each time the phase node
voltage falls a diode drop below PVCC such as when the
low-side MOSFET is turned on.
UGATE
1V
1V
1V
1V
LGATE
FIGURE 6. GATE DRIVER ADAPTIVE SHOOT-THROUGH
12
September 18, 2009
FN6905.1
ISL62875
Setpoint Reference Voltage
Programming
the attenuation factor K in all the calculations for
selecting the RSET programming resistors.
Voltage identification (VID) pins select user-programmed
setpoint reference voltages that appear at the SREF pin.
The converter is in regulation when the FB pin voltage
(VFB) equals the SREF pin voltage (VSREF.) The IC
measures VFB and VSREF relative to the GND pin, not the
PGND pin. The setpoint reference voltages use the
naming convention VSET(x) where (x) is the first, second,
third, or fourth setpoint reference voltage where:
- VSET1 < VSET2 < VSET3 < VSET4
- VOUT1 < VOUT2 < VOUT3 < VOUT4
The VSET1 setpoint is fixed at 500mV because it
corresponds to the closure of internal switch SW0 that
configures the VSET amplifier as a unity-gain voltage
follower for the 500mV voltage reference VREF.
A feedback voltage-divider network may be required to
achieve the desired reference voltages. Using the
feedback voltage-divider allows the maximum output
voltage of the converter to be higher than the 1.5V
maximum setpoint reference voltage that can be
programmed on the SREF pin. Likewise, the feedback
voltage-divider allows the minimum output voltage of the
converter to be higher than the fixed 500mV setpoint
reference voltage of VSET1. Scale the voltage-divider
network such that the voltage VFB equals the voltage
VSREF when the converter output voltage is at the
desired level. The voltage-divider relation is given in
Equation 3:
R OFS
V FB = V OUT ⋅ ---------------------------------R +R
FB
(EQ. 3)
OFS
The value of offset resistor ROFS can be calculated only
after the value of loop-compensation resistor RFB has
been determined. The calculation of ROFS is written as
Equation 5:
V SET ( x ) ⋅ R
FB
R OFS = -------------------------------------------V OUT – V SET ( x )
(EQ. 5)
The setpoint reference voltages are programmed with
resistors that use the naming convention RSET(x) where
(x) is the first, second, third, or fourth programming
resistor connected in series starting at the SREF pin and
ending at the GND pin. When one of the internal switches
closes, it connects the inverting input of the VSET
amplifier to a specific node among the string of RSET
programming resistors. All the resistors between that
node and the SREF pin serve as the feedback impedance
RF of the VSET amplifier. Likewise, all the resistors
between that node and the GND pin serve as the input
impedance RIN of the VSET amplifier. Equation 6 gives
the general form of the gain equation for the VSET
amplifier:
RF ⎞
⎛
V SET ( X ) = V REF ⋅ ⎜ 1 + ----------⎟
R IN⎠
⎝
(EQ. 6)
Where:
- VREF is the 500mV internal reference of the IC
- VSET(x) is the resulting setpoint reference voltage
that appears at the SREF pin
Calculating Setpoint Voltage Programming
Resistor Values
Where:
TABLE 2. ISL62875 VID TRUTH TABLE
- VFB = VSREF
- RFB is the loop-compensation feedback resistor
that connects from the FB pin to the converter
output
- ROFS is the voltage-scaling programming resistor
that connects from the FB pin to the GND pin
The attenuation of the feedback voltage divider is written
as:
R OFS
V SREF ( lim )
K = ------------------------------- = ---------------------------------V OUT ( lim )
R FB + R OFS
(EQ. 4)
Where:
- K is the attenuation factor
- VSREF(lim) is the VSREF voltage setpoint of either
500mV or 1.50V
- VOUT(lim) is the output voltage of the converter
when VSREF = VSREF(lim)
Since the voltage-divider network is in the feedback
path, all output voltage setpoints will be attenuated by K,
so it follows that all of the setpoint reference voltages will
be attenuated by K. It will be necessary then to include
13
VID STATE
RESULT
VID1
VID0
CLOSE
VSREF
VOUT
1
1
SW0
VSET1
VOUT1
1
0
SW1
VSET2
VOUT2
0
1
SW2
VSET3
VOUT3
0
0
SW3
VSET4
VOUT4
First, determine the attenuation factor K. Next, assign an
initial value to RSET4 of approximately 100kΩ then
calculate RSET1, RSET2, and RSET3 using Equations 7, 8,
and 9 respectively. The equation for the value of RSET1 is
written as Equation 7:
R SET4 ⋅ KV SET4 ⋅ ( KV SET2 – V REF )
R SET1 = ---------------------------------------------------------------------------------------------------V REF ⋅ KV SET2
(EQ. 7)
The equation for the value of RSET2 is written as
Equation 8:
R SET4 ⋅ KV SET4 ⋅ ( KV SET3 – KV SET2 )
R SET2 = ----------------------------------------------------------------------------------------------------------KV SET2 ⋅ KV SET3
(EQ. 8)
September 18, 2009
FN6905.1
ISL62875
The equation for the value of RSET3 is written as
Equation 9:
R SET4 ⋅ ( KV SET4 – KV SET3 )
R SET3 = -------------------------------------------------------------------------------KV SET3
(EQ. 9)
The sum of all the programming resistors should be
approximately 300kΩ as shown in Equation 10 otherwise
adjust the value of RSET4 and repeat the calculations.
R SET1 + R SET2 + R SET3 + R SET4 ≅ 300kΩ
(EQ. 10)
Equations 11, 12, 13 and 14 give the specific VSET gain
equations for the ISL62875 setpoint reference voltages.
The ISL62875 VSET1 setpoint is written as Equation 11:
(EQ. 11)
V SET1 = V REF
The ISL62875 VSET2 setpoint is written as Equation 12:
R SET1
⎛
⎞
V SET2 = V REF ⋅ ⎜ 1 + ---------------------------------------------------------------------⎟
R SET2 + R SET3 + R SET4⎠
⎝
(EQ. 12)
The ISL62875 VSET3 setpoint is written as Equation 13:
R SET1 + R SET2⎞
⎛
V SET3 = V REF ⋅ ⎜ 1 + --------------------------------------------⎟
R SET3 + R SET4⎠
⎝
(EQ. 13)
The ISL62875 VSET4 setpoint is written as Equation 14:
R SET1 + R SET2 + R
⎛
SET3⎞
V SET4 = V REF ⋅ ⎜ 1 + ---------------------------------------------------------------------⎟
R
⎝
⎠
SET4
(EQ. 14)
External Setpoint Reference
RFB
FB
VCOMP
EA
ROFS
VOUT
+
+
VSET
SW0
SW1
SET0
SW2
SET1
SW3
SET2
- VID0 pin opens its 500nA pull-down current sink
- Reference source selector switch SW4 moves from
INT position (internal 500mV) to EXT position
(VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage
on the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage
range on the VID0 pin is 500mV to 1.5V. Use Equations
3, 4, and 5 beginning on page 13 should it become
necessary to implement an output voltage-divider
network to make the external setpoint reference voltage
compatible with the 500mV to 1.5V constraint.
Soft-Start and Voltage-Step
Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage
on the EN pin has increased above the rising enable
threshold voltage VENTHR, the SREF pin releases its
discharge clamp and enables the reference amplifier
VSET. The soft-start current ISS is limited to 20µA and is
sourced out of the SREF pin into the parallel RC network
of capacitor CSOFT and resistance RT. The resistance RT
is the sum of all the series connected RSET programming
resistors and is written as Equation 15:
R T = R SET1 + R SET2 + …R SET ( n )
(EQ. 15)
The voltage on the SREF pin rises as ISS charges CSOFT
to the voltage reference setpoint selected by the state of
the VID inputs at the time the EN pin is asserted. The
regulator controls the PWM such that the voltage on the
FB pin tracks the rising voltage on the SREF pin. Once
CSOFT charges to the selected setpoint voltage, the ISS
current source comes out of the 20µA current limit and
decays to the static value set by VSREF ÷ RT. The elapsed
time from when the EN pin is asserted to when VSREF
has reached the voltage reference setpoint is the softstart delay tSS which is given by Equation 16:
V START-UP
t SS = – ( R T ⋅ C SOFT ) ⋅ LN(1 – ------------------------------)
I SS ⋅ R T
(EQ. 16)
Where:
RSET4
RSET3
RSET2
RSET1
SREF
CSOFT
VREF
500mV
voltage to the VID0 pin. When SET0 and VCC are tied
together, the following internal reconfigurations take
place:
FIGURE 7. VOLTAGE PROGRAMMING CIRCUIT
The IC can use an external setpoint reference voltage as
an alternative to VID-selected, resistor-programmed
setpoints. This is accomplished by removing all setpoint
programming resistors, connecting the SET0 pin to the
VCC pin, and feeding the external setpoint reference
14
- ISS is the soft-start current source at the 20µA
limit
- VSTART-UP is the setpoint reference voltage
selected by the state of the VID inputs at the time
EN is asserted
- RT is the sum of the RSET programming resistors
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to the designated VSET voltage
September 18, 2009
FN6905.1
ISL62875
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the ISS current source changes over to
the voltage-step current source IVS which has a current
limit of ±100µA. Whenever the VID inputs or the
external setpoint reference, programs a different setpoint
reference voltage, the IVS current source charges or
discharges capacitor CSOFT to that new level at ±100µA.
Once CSOFT charges to the selected setpoint voltage, the
IVS current source comes out of the 100µA current limit
and decays to the static value set by VSREF ÷ RT. The
elapsed time to charge CSOFT to the new voltage is
called the voltage-step delay tVS and is given by
Equation 17:
( V NEW – V OLD )
t VS = – ( R T ⋅ C SOFT ) ⋅ LN(1 – -------------------------------------------)
I VS ⋅ R T
Compensation Design
Figure 8 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error
amplifier. The COMP signal, the output of the error
amplifier, is inside the chip and unavailable to users.
CINT is a 100pF capacitor integrated inside the IC,
connecting across the FB pin and the COMP signal. RFB,
RCOMP, CCOMP and CINT form the Type-II compensator.
The frequency domain transfer function is given by
Equation 20:
1 + s ⋅ ( R FB + R COMP ) ⋅ C
COMP
G COMP ( s ) = --------------------------------------------------------------------------------------------------------------s ⋅ R FB ⋅ C INT ⋅ ( 1 + s ⋅ R COMP ⋅ C
)
(EQ. 17)
CINT = 100pF
Where:
- IVS is the ±100µA setpoint voltage-step current
- VNEW is the new setpoint voltage selected by the
VID inputs
- VOLD is the setpoint voltage that VNEW is changing
from
- RT is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements
of a particular soft-start delay tSS is calculated with
Equation 18, which is written as:
(EQ. 18)
Where:
- tSS is the soft-start delay
- ISS is the soft-start current source at the 20µA
limit
- VSTART-UP is the setpoint reference voltage
selected by the state of the VID inputs at the time
EN is asserted
- RT is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements
of a particular voltage-step delay tVS is calculated with
Equation 19, which is written as:
– t VS
C SOFT = -----------------------------------------------------------------------------V NEW – V OLD ⎞
⎛
⎜ R T ⋅ LN(1 – ---------------------------------------)⎟
± I VS ⋅ R T
⎝
⎠
(EQ. 19)
CCOMP
RCOMP
RFB
-
VOUT
FB
EA
COMP
ROFS
+
SREF
Component Selection For CSOFT Capacitor
– t SS
C SOFT = --------------------------------------------------------------------V START-UP ⎞
⎛
⎜ R T ⋅ LN(1 – ------------------------------)⎟
I SS ⋅ R T ⎠
⎝
FIGURE 8. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant
frequency that causes rapid phase change. The R3
modulator used in the IC makes the LC output filter
resemble a first order system in which the closed loop
stability can be achieved with the recommended Type-II
compensation network. Intersil provides a PC-based tool
that can be used to calculate compensation network
component values and help simulate the loop frequency
response.
Fault Protection
Overcurrent
The overcurrent protection (OCP) setpoint is
programmed with resistor ROCSET which is connected
across the OCSET and PHASE pins. Resistor RO is
connected between the VO pin and the actual output
voltage of the converter. During normal operation, the
VO pin is a high impedance path, therefore there is no
voltage drop across RO. The value of resistor RO should
always match the value of resistor ROCSET.
L
Where:
DCR
- tVS is the voltage-step delay
- VNEW is the new setpoint voltage
- VOLD is the setpoint voltage that VNEW is changing
from
- IVS is the ±100µA setpoint voltage-step current;
positive when VNEW > VOLD, negative when VNEW
< VOLD
- RT is the sum of the RSET programming resistors
15
(EQ. 20)
COMP
PHASE
+
ROCSET
10µA
OCSET
+ VROCSET
IL
VDCR
CSEN
_
VO
CO
_
RO
VO
FIGURE 9. OVERCURRENT PROGRAMMING CIRCUIT
September 18, 2009
FN6905.1
ISL62875
Figure 9 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current IL creates a voltage drop across
DCR, which is given by Equation 21:
V DCR = I L ⋅ DCR
(EQ. 21)
The IOCSET current source sinks 10µA into the OCSET
pin, creating a DC voltage drop across the resistor
ROCSET, which is given by Equation 22:
V ROCSET = 10μA ⋅ R OCSET
(EQ. 22)
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 23:
V OCSET – V VO = V DCR – V ROCSET = I L ⋅ DCR – I OCSET ⋅ R OCSET
(EQ. 23)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
Component Selection for ROCSET and CSEN
The value of ROCSET is calculated with Equation 24,
which is written as:
I OC ⋅ DCR
R OCSET = ---------------------------I OCSET
(EQ. 24)
Where:
- ROCSET (Ω) is the resistor used to program the
overcurrent setpoint
- IOC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if IOC is 20A and DCR is 4.5mΩ, the choice
of ROCSET is = 20A x 4.5mΩ/10µA = 9kΩ.
Resistor ROCSET and capacitor CSEN form an R-C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant ROCSET CSEN needs to match the inductor time
constant L/DCR. The value of CSEN is then written as
Equation 25:
L
C SEN = -----------------------------------------R OCSET ⋅ DCR
(EQ. 25)
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) =
0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault
will remain latched until the EN pin has been pulled below
the falling EN threshold voltage VENTHF or if VCC has
decayed below the falling POR threshold voltage
V
VCC_THF.
16
Overvoltage
The ISL62875 does not feature overvoltage fault
protection.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold VUVTH for
more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical VUVTH threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
VENTHF or if VCC has decayed below the falling POR
threshold voltage VVCC_THF.
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature TOTRTH, it will enter the OTP
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature TOTHYS at which time
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
voltage VENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF. All other protection
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold VUVTH.
General Application Design
Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a singlephase power converter. It is assumed that the reader is
familiar with many of the basic skills and techniques
referenced in the following. In addition to this guide,
Intersil provides complete reference designs that
include schematics, bills of materials, and example
board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of
the input and the output voltage. This relationship is
expressed in Equation 26:
VO
D = --------V IN
(EQ. 26)
The output inductor peak-to-peak ripple current is
expressed in Equation 27:
VO ⋅ ( 1 – D )
I P-P = ------------------------------F SW ⋅ L
(EQ. 27)
September 18, 2009
FN6905.1
ISL62875
2
(EQ. 28)
P COPPER = I LOAD ⋅ DCR
Where, ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider
when choosing the inductor is its saturation
characteristics at elevated temperature. A saturated
inductor could cause destruction of circuit components,
as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance
CO into which ripple current IP-P can flow. Current IP-P
develops a corresponding ripple voltage VP-P across CO,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages
are expressed in Equations 29 and 30:
(EQ. 29)
ΔV ESR = I P-P ⋅ E SR
I P-P
ΔΔV C = --------------------------------8 ⋅ CO ⋅ F
(EQ. 30)
SW
If the output of the converter has to support a load with
high pulsating current, several capacitors will need to be
paralleled to reduce the total ESR until the required VP-P
is achieved. The inductance of the capacitor can cause a
brief voltage dip if the load transient has an extremely
high slew rate. Low inductance capacitors should be
considered. A capacitor dissipates heat as a function of
RMS current and frequency. Be sure that IP-P is shared
by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at
FSW. Take into account that the rated value of a
capacitor can fade as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance
are the voltage rating and the RMS current rating. For
reliable operation, select bulk capacitors with voltage and
current ratings above the maximum input voltage and
capable of supplying the RMS current required by the
switching circuit. Their voltage rating should be at least
1.25x greater than the maximum input voltage, while a
voltage rating of 1.5x is a preferred rating. Figure 10 is a
graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty
cycle that is adjusted for converter efficiency. The ripple
current calculation is written as Equation 31:
2
2 D
2
( I MAX ⋅ ( D – D ) ) + ⎛ x ⋅ I MAX ⋅ ------ ⎞
⎝
12 ⎠
I IN_RMS = ----------------------------------------------------------------------------------------------------I MAX
Where:
17
(EQ. 31)
- IMAX is the maximum continuous ILOAD of the
converter
- x is a multiplier (0 to 1) corresponding to the
inductor peak-to-peak ripple amplitude expressed
as a percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into
account the efficiency of the converter
Duty cycle is written as Equation 32:
VO
D = -------------------------V IN ⋅ EFF
(EQ. 32)
In addition to the bulk capacitance, some low ESL
ceramic capacitance is recommended to decouple
between the drain of the high-side MOSFET and the
source of the low-side MOSFET.
NORMALIZED INPUT RMS RIPPLE CURRENT
A typical step-down DC/DC converter will have an IP-P of
20% to 40% of the maximum DC output load current.
The value of IP-P is selected based upon several criteria,
such as MOSFET switching loss, inductor core loss, and
the resistive loss of the inductor winding. The DC copper
loss of the inductor can be estimated using Equation 28:
0.60
x=1
0.55
0.50
0.45
x = 0.75
0.40
0.35
x = 0.50
x = 0.25
0.30
0.25
0.20
x=0
0.15
0.10
0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
DUTY CYCLE
FIGURE 10. NORMALIZED RMS INPUT CURRENT FOR
x = 0.8
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. We selected
the bootstrap capacitor breakdown voltage to be at
least 10V. Although the theoretical maximum voltage of
the capacitor is PVCC-VDIODE (voltage drop across the
boot diode), large excursions below ground by the
phase node requires we select a capacitor with at least
a breakdown rating of 10V. The bootstrap capacitor can
be chosen from Equation 33:
Q GATE
C BOOT ≥ -----------------------ΔV BOOT
(EQ. 33)
Where:
- QGATE is the amount of gate charge required to
fully charge the gate of the upper MOSFET
- ΔVBOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, QGATE , of 25nC at 5V and also assume the droop
in the drive voltage over a PWM cycle is 200mV. One will
find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
September 18, 2009
FN6905.1
ISL62875
source and the voltage spike that occurs when the
MOSFET switches off.
2.0
1000
1.8
900
1.6
800
1.4
700
POWER (mW)
CBOOT_CAP (µF)
0.15µF. A good quality ceramic capacitor such as X7R or
X5R is recommended.
1.2
1.0
0.8
QGATE = 100nC
0.6
0.2
QU = 50nC
QL = 50nC
600
QU = 20nC
QL = 50nC
500
400
300
nC
50
0.4
QU = 100nC QU = 50nC
QL = 200nCQL = 100nC
200
100
20nC
0.0
0.0 0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ΔVBOOT_CAP (V)
1.0
FIGURE 11. BOOT CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Driver Power Dissipation
Switching power dissipation in the driver is mainly a
function of the switching frequency and total gate charge
of the selected MOSFETs. Calculating the power
dissipation in the driver for a desired application is critical
to ensuring safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond
the maximum recommended operating junction
temperature of +125°C. When designing the application,
it is recommended that the following calculation be
performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power
dissipated by the drivers is approximated as
Equation 34:
P = F sw ( 1.5V U Q + V L Q ) + P L + P U
U
L
(EQ. 34)
Where:
Fsw is the switching frequency of the PWM signal
VU is the upper gate driver bias supply voltage
VL is the lower gate driver bias supply voltage
QU is the charge to be delivered by the upper
driver into the gate of the MOSFET and discrete
capacitors
- QL is the charge to be delivered by the lower driver
into the gate of the MOSFET and discrete
capacitors
- PL is the quiescent power consumption of the lower
driver
- PU is the quiescent power consumption of the upper
driver
-
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating.
The MOSFETs used in the power stage of the converter
should have a maximum VDS rating that exceeds the
sum of the upper voltage tolerance of the input power
18
0
0
200 400 600 800 1k
1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 12. POWER DISSIPATION vs FREQUENCY
There are several power MOSFETs readily available that
are optimized for DC/DC converter applications. The
preferred high-side MOSFET emphasizes low switch
charge so that the device spends the least amount of
time dissipating power in the linear region. Unlike the
low-side MOSFET which has the drain-source voltage
clamped by its body diode during turn-off, the high-side
MOSFET turns off with VIN -VOUT, plus the spike, across
it. The preferred low-side MOSFET emphasizes low
r DS(ON) when fully saturated to minimize conduction
loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 35:
2
P CON_LS ≈ I LOAD ⋅ r DS ( ON )_LS ⋅ ( 1 – D )
(EQ. 35)
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 36:
2
P CON_HS = I LOAD ⋅ r DS ( ON )_HS ⋅ D
(EQ. 36)
For the high-side MOSFET, its switching loss is written as
Equation 37:
V IN ⋅ I VALLEY ⋅ t ON ⋅ F
V IN ⋅ I PEAK ⋅ t OFF ⋅ F
SW
SW
P SW_HS = ---------------------------------------------------------------------- + -----------------------------------------------------------------2
2
(EQ. 37)
Where:
- IVALLEY is the difference of the DC component of
the inductor current minus 1/2 of the inductor
ripple current
- IPEAK is the sum of the DC component of the
inductor current plus 1/2 of the inductor ripple
current
- tON is the time required to drive the device into
saturation
September 18, 2009
FN6905.1
ISL62875
- tOFF is the time required to drive the device into
cut-off
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the SREF components.
The island should be connected to the rest of the ground
plane layer at one point.
Component Placement
There are two sets of critical components in a DC/DC
converter; the power components and the small signal
components. The power components are the most critical
because they switch large amount of energy. The small
signal components connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. Keeping the distance between the power train
and the control IC short helps keep the gate drive traces
short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the
upper MOSFETs and the drain of the lower MOSFETs as
close as thermally possible (see Figure 13). Input highfrequency capacitors should be placed close to the drain
of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. Highfrequency output decoupling capacitors (ceramic) should
be placed as close as possible to the decoupling target
(GPUor CPU), making use of the shortest connection
paths to any internal planes. Place the components in
such a way that the area under the IC has less noise
traces with high dV/dt and di/dt, such as gate signals and
phase node signals.
VIAS TO
GROUND
PLANE
GND
VOUT
INDUCTOR
PHASE
NODE
HIGH-SIDE
MOSFETS
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
19
Signal Ground and Power Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the
bottom setpoint-reference programming-resistor, bottom
feedback voltage-divider resistor (if used), and the
CSOFT capacitor be made as close as possible to the
GND pin on a conductor not shared by any other
components.
In addition to the critical single point connection
discussed in the previous paragraph, the ground plane
layer of the PCB should have a single-point-connected
island located under the area encompassing the IC,
setpoint reference programming components, feedback
voltage divider components, compensation components,
CSOFT capacitor, and the interconnecting traces among
the components and the IC. The island should be
connected using several filled vias to the rest of the
ground plane layer at one point that is not in the path of
either large static currents or high di/dt currents. The
single connection point should also be where the VCC
decoupling capacitor and the GND pin of the IC are
connected.
Anywhere not within the analog-ground island is Power
Ground. Connect the input capacitor(s), the output
capacitor(s), and the source of the lower MOSFET(s) to
the power ground plane.
Routing and Connection Details
Specific pins (and the trace routing from them), require
extra attention during the layout process. The following
sub-sections outline concerns by pin name.
VCC PIN
For best performance, place the decoupling capacitor
next to the VCC and GND pins. The VCC decoupling
capacitor should not share any vias with the PVCC
decoupling capacitor.
PVCC PIN
For best performance, place the PVCC decoupling
capacitor next to the PVCC and PGND pins, preferably on
the same side of the PCB as the ISL62875. The PVCC
decoupling capacitor should have a very short and wide
trace connection to the PGND pin.
EN, PGOOD, VID0, AND VID1 PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of ROCSET, RO,
and CSEN must be connnected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
September 18, 2009
FN6905.1
ISL62875
FB, SREF, SET0, SET1, AND SET2 PINS
Copper Size for the Phase Node
The input impedance of these pins is high, making it
critical to place the loop compensation components,
setpoint reference programming resistors, feedback
voltage divider resistors, and CSOFT close to the IC,
keeping the length of the traces short.
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing.
It is best to limit the size of the PHASE node copper in
strict accordance with the current and thermal
management of the application. An MLCC should be
connected directly across the drain of the upper MOSFET
and the source of the lower MOSFET to suppress the
turn-off voltage.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are boht high
dv/dt and di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when
LGATE goes low. Ideally, route the trace from the LGATE
pin in parallel with the trace from the PGND pin, route
the trace from the UGATE pin in parallel with the trace
from the PHASE pin, and route the trace from the BOOT
pin in parallel with the trace from the PHASE pin. These
pairs of traces should be short, wide, and away from
other traces with high input impedance; weak signal
traces should not be in proximity with these traces on
any layer.
20
September 18, 2009
FN6905.1
ISL62875
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
8/09
FN6905.0
Initial Release
9/09
FN6905.1
Page 10: Removed “OVP Rising Threshold Voltage” and “OVP Falling Threshold Voltage” lines
from the “Electrical Specifications” table.
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21
September 18, 2009
FN6905.1
ISL62875
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN)
Rev 0, 5/08
1.80
A
6
PIN #1 ID
16X 0.40
B
20
6
PIN 1 ID#
1
19
2
3.20
0.50±0.10
(4X)
0.10
9
12
11
10
VIEW “A-A”
TOP VIEW
0.10 M C A B
0.05 M C
4 20X 0.20
19X 0.40 ± 0.10
BOTTOM VIEW
( 1.0 )
(1 x 0.70)
SEE DETAIL "X"
0.10 C
MAX 0.55
C
BASE PLANE
( 2. 30 )
SEATING PLANE
0.05 C
SIDE VIEW
( 16 X 0 . 40 )
C
0 . 2 REF
5
( 20X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 19X 0 . 60 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
22
September 18, 2009
FN6905.1