TI1 LMZ14201 Simple switcher 6v to 42v, 1a power module in leaded smt-to package Datasheet

Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
LMZ14201 SIMPLE SWITCHER® 6V to 42V, 1A Power Module in Leaded SMT-TO Package
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Integrated Shielded Inductor
Simple PCB Layout
Flexible Start-Up Sequencing Using External SoftStart and Precision Enable
Protection Against Inrush Currents and Faults
Such as Input UVLO and Output Short Circuit
–40°C to 125°C Junction Temperature Range
Single Exposed Pad and Standard Pinout for Easy
Mounting and Manufacturing
Fast Transient Response for Powering FPGAs
and ASICs
Low Output Voltage Ripple
Pin-to-Pin Compatible Family:
– LMZ1420x (42 V Maximum 3 A, 2 A, 1 A)
– LMZ1200x (20 V Maximum 3 A, 2 A, 1 A)
Fully Enabled for WEBENCH® Power Designer
Electrical Specifications
– 6-W Maximum Total Output Power
– Up to 1-A Output Current
– Input Voltage Range 6 V to 42 V
– Output Voltage Range 0.8 V to 6 V
– Efficiency up to 90%
Performance Benefits
– Operates at High Ambient Temperature With
No Thermal Derating
– High Efficiency Reduces System Heat
Generation
– Low Radiated Emissions (EMI) Tested With
EN55022 Class B Standard
– Low External Component Count
Simplified Application Schematic
•
•
•
Point of Load Conversions From 12-V and 24-V
Input Rail
Time-Critical Projects
Space Constrained and High Thermal
Requirement Applications
Negative Output Voltage Applications
(See AN-2027) SNVA425
3 Description
The LMZ14201 SIMPLE SWITCHER® power module
is an easy-to-use step-down DC-DC solution that can
drive up to 1-A load with exceptional power
conversion efficiency, line and load regulation, and
output accuracy. The LMZ14201 is available in an
innovative
package
that
enhances
thermal
performance and allows for hand or machine
soldering.
The LMZ14201 can accept an input voltage rail
between 6 V and 42 V and deliver an adjustable and
highly accurate output voltage as low as 0.8 V. The
LMZ14201 only requires three external resistors and
four external capacitors to complete the power
solution. The LMZ14201 is a reliable and robust
design with the following protection features: thermal
shutdown, input UVLO, output overvoltage protection,
short-circuit protection, output current limit, and
allows start-up into a prebiased output. A single
resistor adjusts the switching frequency up to 1 MHz.
Device Information(1)(2)
PART NUMBER
LMZ14201
Efficiency 12-V Input at 25°C
90
EFFICIENCY (%)
VOUT
CFF
RFBT
Enable
CSS
6.0
5.0
3.3
2.5
1.8
1.5
1.2
0.8
95
VOUT
FB
SS
EN
GND
VIN
RON
100
RON
CIN
BODY SIZE (NOM)
10.16 mm × 9.85 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
LMZ14201
VIN
PACKAGE
TO-PMOD (7)
RFBB
COUT
85
80
75
70
65
60
55
50
25°C
0
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
4
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 21
10.3 Power Dissipation and Board Thermal
Requirements........................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (August 2015) to Revision I
•
Added this new bullet in the Power Module SMT Guidelines section .................................................................................. 19
Changes from Revision G (May 2015) to Revision H
•
Page
Page
Changed the title of the document ......................................................................................................................................... 1
Changes from Revision F (October 2013) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Easy-to-Use Pin Package image .......................................................................................................................... 1
•
Removed Evaluation Board Schematic Diagram and BOM section..................................................................................... 22
Changes from Revision E (March 2013) to Revision F
Page
•
Added Peak Reflow Case Temp = 245°C ............................................................................................................................. 1
•
Deleted 10 mils ...................................................................................................................................................................... 5
•
Changed 10 mils................................................................................................................................................................... 19
•
Added Power Module SMT Guidelines section .................................................................................................................... 19
•
Changed 10 mils................................................................................................................................................................... 22
2
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
NDW Package
7-Pin TO-PMOD
Top View
Exposed Pad
Connect to GND
7
6
5
4
3
2
1
VOUT
FB
SS
GND
EN
RON
VIN
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
VIN
Power
Supply input — Nominal operating range is 6 V to 42 V . A small amount of internal
capacitance is contained within the package assembly. Additional external input
capacitance is required between this pin and exposed pad.
2
RON
Analog
On Time Resistor — An external resistor from VIN to this pin sets the ON-time of the
application. Typical values range from 25 kΩ to 124 kΩ.
3
EN
Analog
Enable — Input to the precision enable comparator. Rising threshold is 1.18 V nominal;
90 mV hysteresis nominal. Maximum recommended input level is 6.5 V.
4
GND
Ground
Ground — Reference point for all stated voltages. Must be externally connected to EP.
5
SS
Analog
Soft-Start — An internal 8-µA current source charges an external capacitor to produce
the soft-start function. This node is discharged at 200 µA during disable, overcurrent,
thermal shutdown and internal UVLO conditions.
6
FB
Analog
Feedback — Internally connected to the regulation, overvoltage, and short-circuit
comparators. The regulation reference point is 0.8 V at this input pin. Connected the
feedback resistor divider between the output and ground to set the output voltage.
7
VOUT
Power
Output Voltage — Output from the internal inductor. Connect the output capacitor
between this pin and exposed pad.
—
EP
Ground
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package
during operation. Must be electrically connected to pin 4 external to the package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
VIN, RON to GND
–0.3
43.5
V
EN, FB, SS to GND
–0.3
7
V
150
°C
150
°C
Junction Temperature
Storage Temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For soldering specifications, see product folder at www.ti.com and SNOA549.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
3
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN
6
42
EN
0
6.5
V
−40
125
°C
Operation Junction Temperature
(1)
V
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings are conditions
under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical
Characteristics.
6.4 Thermal Information
LMZ14201
THERMAL METRIC (1)
NDW (TO-PMOD)
UNIT
7 PINS
4 layer JEDEC Printed Circuit Board, 100 vias, No air flow
19.3
2 layer JEDEC Printed Circuit Board, No air flow
21.5
RθJA
Junction-to-ambient
thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
(1)
°C/W
1.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Limits are for TJ = 25°C only unless otherwise noted. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, Vout = 3.3 V
PARAMETER
MIN (1)
TEST CONDITIONS
TYP (2)
MAX (1)
UNIT
SYSTEM PARAMETERS
ENABLE CONTROL (3)
VEN
EN threshold trip point
VEN rising
1.18
over the junction temperature
(TJ) range of –40°C to +125°C
VEN-HYS
EN threshold hysteresis
1.10
V
1.25
VEN falling
90
mV
VSS = 0 V
8
µA
SOFT-START
ISS
SS source current
over the junction temperature
(TJ) range of –40°C to +125°C
ISS-DIS
5
SS discharge current
11
-200
µA
CURRENT LIMIT
ICL
Current limit threshold
DC average
1.95
over the junction temperature
(TJ) range of –40°C to +125°C
1.4
3
A
ON/OFF TIMER
tON-MIN
ON timer minimum pulse
width
150
ns
tOFF
OFF timer pulse width
260
ns
(1)
(2)
(3)
4
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
Electrical Characteristics (continued)
Limits are for TJ = 25°C only unless otherwise noted. Minimum and Maximum limits are ensured through test, design or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. Unless otherwise stated the following conditions apply: VIN = 24 V, Vout = 3.3 V
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
REGULATION AND OVERVOLTAGE COMPARATOR
VFB
In-regulation feedback
voltage
VSS >+ 0.8 V
TJ = -40°C to
125°C
IO = 1 A
0.798
over the junction temperature
(TJ) range of –40°C to +125°C
VSS > +0.8 V
TJ = 25°C
IO = 10 mA
VFB-OV
Feedback overvoltage
protection threshold
IFB
Feedback input bias
current
IQ
Non Switching Input
Current
VFB= 0.86 V
ISD
Shut Down Quiescent
Current
VEN= 0 V
.777
0.786
0.818
0.802
0.818
V
V
0.92
V
5
nA
1
mA
25
μA
165
°C
15
°C
THERMAL CHARACTERISTICS
TSD
Thermal Shutdown
Rising
TSD-HYST
Thermal shutdown
hysteresis
Falling
PERFORMANCE PARAMETERS
ΔVO
Output Voltage Ripple
ΔVO/ΔVIN
Line Regulation
VIN = 12 V to 42 V, IO= 1 A
ΔVO/IOUT
Load Regulation
VIN = 24 V
η
Efficiency
VIN = 24 V VO = 3.3 V IO = 1 A
8
1.5
Product Folder Links: LMZ14201
PP
mV/A
92%
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
mV
.01%
5
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic;
TA = 25 C for efficiency curves and waveforms.
0.3
100
95
3.3
2.5
1.8
1.5
1.2
0.8
85
80
DISSIPATION (W)
EFFICIENCY (%)
90
75
70
65
1.8
1.5
0.2
1.2
0.8
0.15
0.1
60
25°C
0.05
55
50
3.3
2.5
0.25
25°C
0
0.2
0.4
0.6
0.8
0
1
0
0.2
OUTPUT CURRENT (A)
Figure 1. Efficiency 6-V Input at 25°C
85
80
75
70
65
3.3
2.5
0.3
1.8
1.5
0.225
1.2
0.8
0.15
25°C
60
0.075
55
25°C
0
0
0.2
0.4
0.6
0.8
0
1
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Dissipation 12-V Input at 25°C
Figure 3. Efficiency 12-V Input at 25°C
0.7
100
95
0.6
85
80
DISSIPATION (W)
6.0
5.0
3.3
2.5
1.8
90
EFFICIENCY (%)
1
6.0
5.0
0.375
DISSIPATION (W)
EFFICIENCY (%)
90
75
70
65
60
6.0
5.0
3.3
2.5
0.5
0.4
1.8
0.3
0.2
0.1
55
25°C
0
25°C
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency 24-V Input at 25°C
6
0.8
0.45
6.0
5.0
3.3
2.5
1.8
1.5
1.2
0.8
95
50
0.6
Figure 2. Dissipation 6-V Input at 25°C
100
50
0.4
OUTPUT CURRENT (A)
Submit Documentation Feedback
Figure 6. Dissipation 24-V Input at 25°C
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic;
TA = 25 C for efficiency curves and waveforms.
100
1.2
95
1.0
6.0
5.0
85
DISSIPATION (W)
EFFICIENCY (%)
90
80
3.3
75
70
65
60
0.6
3.3
0.4
0.2
55
50
6.0
5.0
0.8
25°C
0
25°C
0.2
0.4
0.6
0.8
0
1
0.2
0
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 7. Efficiency 36-V Input at 25°C
Figure 8. Dissipation 36-V Input at 25°C
100
1.2
95
1.0
85
6.0
5.0
80
75
DISSIPATION (W)
EFFICIENCY (%)
90
3.3
70
65
60
5.0
0.8
3.3
0.6
0.4
0.2
55
50
6.0
25°C
0
25°C
0.2
0.4
0.6
0.8
0
1
0
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 9. Efficiency 42-V Input at 25°C
Figure 10. Dissipation 42-V Input at 25°C
0.45
100
95
85
80
DISSIPATION (W)
EFFICIENCY (%)
0.375
3.3
2.5
1.8
1.5
1.2
90
75
70
65
0.3
0.225
1.2
0.15
85°C
60
0.075
55
50
3.3
2.5
1.8
1.5
85°C
0
0.2
0.4
0.6
0.8
1
0
0
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 11. Efficiency 6-V Input at 85°C
Figure 12. Dissipation 6-V Input at 85°C
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
7
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic;
TA = 25 C for efficiency curves and waveforms.
100
0.45
95
5.0
3.3
2.5
1.8
1.5
1.2
85
80
DISSIPATION (W)
EFFICIENCY (%)
90
75
70
65
0.3
0.225
1.2
0.15
85°C
60
0.075
55
50
5.0
3.3
2.5
1.8
1.5
0.375
85°C
0
0.2
0.4
0.6
0.8
0
1
0
0.2
OUTPUT CURRENT (A)
1
0.8
Figure 14. Dissipation 8-V Input at 85°C
100
0.6
95
6.0
5.0
3.3
2.5
1.8
1.5
1.2
85
80
0.5
DISSIPATION (W)
90
EFFICIENCY (%)
0.6
OUTPUT CURRENT (A)
Figure 13. Efficiency 8-V Input at 85°C
75
70
65
60
6.0
5.0
3.3
2.5
0.4
0.3
1.8
1.5
0.2
1.2
0.1
55
50
0.4
85°C
85°C
0
0
0.2
0.4
0.6
0.8
0
1
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 15. Efficiency 12-V Input at 85°C
Figure 16. Dissipation 12-V Input at 85°C
1.2
100
95
80
6.0
5.0
3.3
2.5
75
1.8
85
1.0
DISSIPATION (W)
EFFICIENCY (%)
90
70
65
60
8
6.0
5.0
0.6
0.4
3.3
2.5
0.2
1.8
55
50
0.8
85°C
85°C
0
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 17. Efficiency 24-V Input at 85°C
Figure 18. Dissipation 24-V Input at 85°C
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic;
TA = 25 C for efficiency curves and waveforms.
100
1.2
95
80
6.0
5.0
75
3.3
DISSIPATION (W)
EFFICIENCY (%)
85
70
65
60
0.8
0.6
3.3
0.4
0.2
55
50
6.0
5.0
1.0
90
85°C
0
85°C
0
0.4
0.2
0.6
0.8
0.2
0
1
0.4
0.6
1
0.8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 19. Efficiency 36-V Input at 85°C
Figure 20. Dissipation 36-V Input at 85°C
1.2
100
6.0
95
1.0
85
DISSIPATION (W)
EFFICIENCY (%)
90
6.0
5.0
80
75
3.3
70
65
60
0.8
3.3
0.6
0.4
0.2
55
50
5.0
85°C
0
0
0.4
0.2
0.6
0.8
1
85°C
0
0.2
0.4
0.6
1
0.8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 21. Efficiency 42-V Input at 85°C
Figure 22. Dissipation 42-V Input at 85°C
3.34
3.36
3.32
3.34
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
24
42
3.30
6
3.28
24
8
20
12
3.26
42
3.32
36
8 12 20
6
3.30
3.28
36
85°C
25°C
3.26
3.24
0
0.2
0.4
0.6
0.8
0
1.0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 23. Line and Load Regulation at 25°C
Figure 24. Line and Load Regulation at 85°C
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
9
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24 V; CIN = 10 uF X7R Ceramic; CO = 100 uF X7R Ceramic;
TA = 25 C for efficiency curves and waveforms.
0.5 A/Div
20 mV/Div
Figure 26. Transient Response
24VIN 3.3 VO 0.5-A to 1-A Step
1.2
2.4
1
2.3
0.8
CURRENT (A)
OUTPUT CURRENT (A)
Figure 25. Output Ripple
24VIN 3.3 VO 1 A, BW = 200 MHz
6VIN
0.6
12VIN
0.4
ÆJA = 19°C/W
24VIN
VOUT = 3.3V
70
60
90
SHORT CIRCUIT
2.1
2.0
ONSET
25°C
36VIN
80
2.2
1.9
0.2
0
50
200 Ps/Div
1.8
100 110 120
0
5
10
15
20
25
AMBIENT TEMPERATURE (C)
INPUT VOLTAGE (V)
Figure 27. Thermal Derating VOUT = 3.3 V
Figure 28. Current Limit 1.8 VOUT at 25°C
2.4
2.5
2.3
2.4
SHORT CIRCUIT
2.2
CURRENT (A)
CURRENT (A)
SHORT CIRCUIT
2.1
ONSET
2.0
2.3
2.2
2.1
ONSET
1.9
2.0
25°C
1.8
0
10
20
30
40
50
INPUT VOLTAGE (V)
0
10
20
30
40
50
INPUT VOLTAGE (V)
Figure 29. Current Limit 3.3 VOUT at 25°C
10
85°C
1.9
Submit Documentation Feedback
Figure 30. Current Limit 3.3 VOUT at 85°C
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
7 Detailed Description
7.1 Overview
7.1.1 COT Control Circuit Overview
Constant On Time control is based on a comparator and an ON-time one-shot, with the output voltage feedback
compared with an internal 0.8-V reference. If the feedback voltage is below the reference, the main MOSFET is
turned on for a fixed ON-time determined by a programming resistor RON. RON is connected to VIN such that ONtime is reduced with increasing input supply voltage. Following this ON-time, the main MOSFET remains off for a
minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the ON-time cycle is
repeated. Regulation is achieved in this manner.
7.2 Functional Block Diagram
Vin
VIN 1
Linear reg
CIN
Cvcc
5
SS
Css
CBST
3
EN
RON
2
VOUT 7
RON
Timer
CFF
6
10 PH
VO
Co
FB
RFBT
RFBB
0.47 PF
Regulator IC
Internal
Passives
GND
4
7.3 Feature Description
7.3.1 Output Overvoltage Comparator
The voltage at FB is compared to a 0.92-V internal reference. If FB rises above 0.92-V the ON-time is
immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage
is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET ON-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
7.3.2 Current Limit
Current limit detection is carried out during the OFF-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 2.0 A (typical) the
current limit comparator disables the start of the next ON-time period. The next switching cycle will occur only if
the FB input is less than 0.8V and the inductor current has decreased below 2.0 A. Inductor current is monitored
during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 2.0 A,
further ON-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due
to the longer OFF-time.
NOTE
Current limit is dependent on both duty cycle and temperature as illustrated in the graphs
in the Typical Characteristics section.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
11
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
7.3.3 Thermal Protection
The junction temperature of the LMZ14201 should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145 °C (typical Hyst = 20 °C) the
SS pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application
derating at elevated temperatures.
7.3.4 Zero Coil Current Detection
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next ON-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
7.3.5 Prebiased Start-Up
The LMZ14201 will properly start up into a prebiased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the startup sequence. The
following scope capture shows proper behavior during this event.
OUTPUT
VOLTAGE
2V PRE-BIAS
OUTPUT
CURRENT
ENABLE
3.3V OUTPUT
1.0 V/Div
0.5 A/Div
2.0 V/Div
1 ms/Div
Figure 31. Prebiased Start-Up
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light-load, the regulator operates in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it operates in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the OFF-time. During the period of time that inductor current is zero, all load current is
supplied by the output capacitor. The next ON-time period starts when the voltage on the FB pin falls below the
internal reference. The switching frequency is lower in DCM and varies more with load current as compared to
CCM. Conversion efficiency in DCM is maintained because conduction and switching losses are reduced with
the smaller load and lower switching frequency.
12
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ14201 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select
components for the LMZ14201. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. For more details, go to www.ti.com.
8.2 Typical Application
U1
EP
VIN
Enable
VOUT
FB
3.3VO @ 1A
7
GND
EN
VIN
SS
6
5
4
3
2
1
RON
LMZ14201TZ-ADJ
6.0V to 42V
RENT
CFF
68.1k
0.022 PF
RON
RFBT
61.9k
RENB
D1
OPT
11.8k
3.32k
CIN2
CIN1
CSS
RFBB
10 PF
1 PF
0.022 PF
1.07k
CO1
CO2
1 PF
100 PF
Figure 32. Evaluation Board Schematic Diagram
Table 1. Schematic Bill of Materials
VOUT
RFBT
RFBB
RON
VIN RANGE
5V
5.62 K
1.07 K
100 K
7.7...42 V
3.3 V
3.32 K
1.07 K
61.9 K
6...42 V
2.5 V
2.26 K
1.07 K
47.5 K
6...30 V
1.8 V
1.87 K
1.50 K
32.4 K
6...25 V
1.5 V
1K
1.13 K
28 K
6...21 V
1.2 V
4.22 K
8.45 K
22.6 K
6...19 V
0.8 V
0
39.2
24.9 K
6...18 V
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
13
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Table 2. Bill of Materials
REF DES
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
U1
SIMPLE SWITCHER ®
PFM-7
Texas Instruments
LMZ14201TZ-ADJ
Cin1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
Cin2
10 µF, 50V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
CO1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
CO2
100 µF, 6.3V, X7R
1210
Taiyo Yuden
JMK325BJ107MM-T
RFBT
3.32 kΩ
0603
Vishay Dale
CRCW06033K32FKEA
RFBB
1.07 kΩ
0603
Vishay Dale
CRCW06031K07FKEA
RON
61.9 kΩ
0603
Vishay Dale
CRCW060361k9FKEA
RENT
68.1 kΩ
0603
Vishay Dale
CRCW060368k1FKEA
RENB
11.8 kΩ
0603
Vishay Dale
CRCW060311k8FKEA
CFF
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
CSS
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
D1
5.1V
SOD-23
—
Optional
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN Range = Up to 42 V
• VOUT = 0.8 V to 5 V
• IOUT = 1 A
Please refer to the table in Table 1 for more information.
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps for the LMZ14201 Application
The LMZ14201 is fully supported by WEBENCH and offers the following: Component selection, electrical and
thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be
used to manually design the LMZ14201 application.
1.
2.
3.
4.
5.
6.
7.
8.
Select minimum operating VIN with enable divider resistors
Program VO with divider resistor selection
Program turnon time with soft-start capacitor selection
Select CO
Select CIN
Set operating frequency with RON
Determine module dissipation
Lay out PCB for required thermal performance
8.2.2.1.1 Enable Divider, RENT and RENB Selection
The enable input provides a precise 1.18-V band-gap rising threshold to allow direct logic drive or connection to
a voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typical) of
hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V.
For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to
limit this voltage.
14
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit
will be disabled. This implements the feature of programmable under voltage lockout. This is often used in
battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for
sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at powerup. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems
such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of
sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the
LMZ14201 output rail. The two resistors should be chosen based on the following ratio:
RENT / RENB = (VIN UVLO/ 1.18 V) – 1
(1)
The LMZ14201 demonstration and evaluation boards use 11.8 kΩ for RENB and 68.1 kΩ for RENT resulting in a
rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V.
The EN pin is internally pulled up to VIN and can be left floating for always-on operation.
8.2.2.1.2 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal
operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ONtime cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at
FB is above 0.8 V, ON-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8V × (1 + RFBT / RFBB)
(2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8V) - 1
(3)
These resistors should be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For VO = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains
that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple
current and maintain proper regulation when no load is present.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT , RFBB , CFF, and RON is included in the applications schematic.
8.2.2.1.3 Soft-Start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turnon, after all UVLO conditions have been passed, an internal 8-µA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady-state operation is given by the formula:
tSS = VREF × CSS / Iss = 0.8V × CSS / 8 µA
(4)
This equation can be rearranged as follows:
CSS = tSS × 8 μA / 0.8 V
(5)
Use of a 0.022-μF results in 2.2 ms soft-start interval which is recommended as a minimum value.
As the soft-start input exceeds 0.8 V the output of the power stage will be in regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8 V and 3.8 V
have no effect on other circuit operation. Note the following conditions will reset the soft-start capacitor by
discharging the SS input to ground with an internal 200-μA current sink.
•
•
•
•
The enable input being “pulled low”
Thermal shutdown condition
Overcurrent fault
Internal VCC UVLO (Approximately 4 V input to VIN)
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
15
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
8.2.2.1.4 CO Selection
None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst-case minimum ripple current rating of 0.5 × ILR P-P, as calculated in Equation 20 below.
Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A
minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a
minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 for more detail.
Equation 6 provides a good first pass approximation of CO for load transient requirements:
CO≥ISTEP*VFB × L × VIN/ (4 × VO × (VIN – VO) × VOUT-TRAN)
(6)
Solving:
CO≥ 1 A × 0.8 V × 10 μH × 24 V / (4 × 3.3 V × ( 24 V – 3.3 V) × 33 mV) ≥ 21.3 μF
(7)
The LMZ14201 demonstration and evaluation boards are populated with a 100-uF 6.3-V X5R output capacitor.
Locations for other output capacitors are provided.
8.2.2.1.5 CIN Selection
The LMZ14201 module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance should
be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current
requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by Equation 8:
I(CIN(RMS)) ≊ 1 / 2 × IO × √ (D / 1-D)
where
•
D ≊ VO / VIN
(8)
(As a point of reference, the worst-case ripple current will occur when the module is presented with full load
current and when VIN = 2 × VO).
Recommended minimum input capacitance is 10-uF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. It is also recommended that attention be paid to the
voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of
ceramic capacitors may be missing from the capacitor data sheet and you may need to contact the capacitor
manufacturer for this rating.
If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then Equation 9
may be used.
CIN ≥ IO × D × (1–D) / fSW-CCM × ΔVIN
(9)
If ΔVIN is 1% of VIN for a 24-V input to 3.3-V output application this equals 240 mV and fSW = 400 kHz.
CIN≥ 1 A × 3.3 V / 24 V × (1– 3.3 V/24 V) / (400000 × 0.240 V)
≥ 0.9 μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
8.2.2.1.6 RON Resistor Selection
Many designs will begin with a desired switching frequency in mind. For that purpose Equation 10 can be used.
fSW(CCM) ≊ VO / (1.3 × 10-10 × RON)
(10)
This can be rearranged as
RON ≊ VO / (1.3 × 10 -10 × fSW(CCM))
(11)
The selection of RON and fSW(CCM) must be confined by limitations in the ON-time and OFF-time for the COT
Control Circuit Overview section.
The ON-time of the LMZ14201 timer is determined by the resistor RON and the input voltage VIN. It is calculated
as follows:
tON = (1.3 × 10-10 × RON) / VIN
16
(12)
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should
be selected such that the ON-time at maximum VIN is greater than 150 ns. The ON-timer has a limiter to ensure
a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by Equation 13:
fSW(MAX) = VO / (VIN(MAX) × 150 ns)
(13)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ONtime of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥ VIN(MAX) × 150 nsec / (1.3 × 10 -10)
(14)
If RON calculated in Equation 11 is less than the minimum value determined in Equation 14 a lower frequency
should be selected. Alternatively, VIN(MAX) can also be limited to keep the frequency unchanged.
NOTE
The minimum OFF-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW)
should be selected in any application requiring large duty ratio.
8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection
Operating frequency in DCM can be calculated as follows:
fSW(DCM) ≊ VO × (VIN-1) × 10 μH × 1.18 × 1020 × IO/(VIN–VO) × RON2
(15)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using Equation 7 above.
Figure 33 shows a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO × (VIN–VO) / (2 × 10 μH × fSW(CCM) × VIN)
(16)
Figure 34 shows a typical waveform showing the boundary condition.
500 mA/Div
500 mA/Div
2.00 Ps/Div
Figure 33. CCM and DCM Operating Modes
VIN = 12 V, VO = 3.3 V, IO = 1 A / 0.25 A
2.00 Ps/Div
Figure 34. Transition Mode Operation
VIN = 24 V, VO = 3.3 V, IO = 0.29 A
The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO × (VIN– VO) / (10 µH × fSW × VIN)
where
•
VIN is the maximum input voltage and fSW is determined from Equation 10.
(17)
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
17
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
8.2.3 Application Curves
100
1.2
95
1
OUTPUT CURRENT (A)
EFFICIENCY (%)
90
85
80
75
70
65
60
0.8
0.6
0.4
0.2
55
50
0
0.2
0.4
0.6
0.8
0
50
1
OUTPUT CURRENT (A)
60
70
80
90
100 110 120
AMBIENT TEMPERATURE (°C)
Figure 35. Efficiency VIN = 24 V VOUT = 5.0 V
Figure 36. Thermal Derating Curve
VIN = 24 V, VOUT = 5.0 V
RADIATED EMISSIONS (dBµV/m)
80.0
70.0
60.0
50.0
EN 55022 CLASS B LIMIT
40.0
30.0
20.0
10.0
0.0
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 37. Radiated Emissions (EN 55022 Class B)
from Evaluation Board
18
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
9 Power Supply Recommendations
The LMZ14201 device is designed to operate from an input voltage supply range between 4.5 V and 42 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ14201 supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ14201, additional bulk capacitance may
be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that
will cause observable high-frequency noise on the output pin if the input capacitor (Cin1) is placed at a
distance away from the LMZ14201. Therefore place CIN1 as close as possible to the LMZ14201 VIN and
GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for
both the input and output capacitor should consist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.The ground connections for the feedback, soft-start, and enable components
should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in
the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.Both feedback resistors, RFBT and RFBB, and the feed forward
capacitor CFF, should be close to the FB pin. Because the FB node is high impedance, maintain the copper
area as small as possible. The trace are from RFBT, RFBB, and CFF should be routed away from the body of
the LMZ14201 to minimize noise.
4. Make input and output bus connections as wide as possible.This reduces any voltage drops on the input
or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a
separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and
provide optimum output accuracy.
5. Provide adequate device heat-sinking.Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can
also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6
× 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough
copper area is used for heat-sinking to keep the junction temperature below 125°C.
10.1.1 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness – 0.125 to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to AN SNAA214 for Reflow information
• Maximum number of reflows allowed is one
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
19
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Layout Guidelines (continued)
Figure 38. Sample Reflow Profile
Table 3. Sample Reflow Profile Table
20
PROBE
MAX TEMP
(°C)
REACHED
MAX TEMP
TIME ABOVE
235°C
REACHED
235°C
TIME ABOVE
245°C
REACHED
245°C
TIME ABOVE
260°C
REACHED
260°C
1
242.5
6.58
0.49
6.39
0.00
–
0.00
–
2
242.5
7.10
0.55
6.31
0.00
7.10
0.00
–
3
241.0
7.09
0.42
6.44
0.00
–
0.00
–
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
10.2 Layout Example
VIN
VO
LMZ14201
VOUT
VIN
High
di/dt
Cin1
CO1
GND
Loop 2
Loop 1
Figure 39. Minimize Area of Current Loops in Buck Module
Top View
Thermal Vias
GND
GND
EPAD
1
2
3
4 5
6 7
VIN
EN
RON
SS
GND
VOUT
FB
CIN
VIN
COUT
VOUT
RON
RENT
RFBT
CSS
RENB
CFF
RFBB
GND Plane
Figure 40. PCB Layout Guide
Figure 41. EVM Board Layout - Top View
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
21
LMZ14201
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
www.ti.com
Layout Example (continued)
Figure 42. EVM Board Layout - Bottom View
10.3 Power Dissipation and Board Thermal Requirements
For the design case of VIN = 24 V, VO = 3.3 V, IO = 1A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device
must see a thermal resistance from case to ambient of less than:
RθCA< (TJ-MAX – TAMB(MAX)) / PIC-LOSS – RθJC
(18)
Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves
in the Typical Performance Characteristics section to estimate the PIC-LOSS for the application being designed. In
this application it is 0.52W.
RθCA = (125 — 85) / 0.52 W — 1.9 = 75
(19)
To reach RθCA = 75, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:
Board Area_cm2 = 500°C x cm2/W / RθJC
(20)
As a result, approximately 6 square cm of 1 oz copper on top and bottom layers is required for the PCB design.
Additional area will decrease die temperature proportionately. The PCB copper heat sink must be connected to
the exposed pad. Approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the
top copper to the bottom copper. For an example of a high thermal performance PCB layout of approximately 31
square cm area. Refer to the Evaluation Board application note AN-2024 SNVA422. For more information on
thermal design see AN-2020 SNVA419 and AN-2026 SNVA424.
22
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
LMZ14201
www.ti.com
SNVS649I – JANUARY 2010 – REVISED OCTOBER 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
• Design Summary LMZ1 and LMZ2 Power Modules, SNAA214
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, SNVA425
• Evaluation Board Application Note AN-2024, SNVA422
• AN-2020 Thermal Design By Insight, Not Hindsight, SNVA419
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules, SNVA424
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LMZ14201
23
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
551600437-001/NOPB
ACTIVE
LMZ14201TZ-ADJ/NOPB
ACTIVE
TO-PMOD
LMZ14201TZE-ADJ/NOPB
ACTIVE
LMZ14201TZX-ADJ/NOPB
ACTIVE
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
0
1
TBD
Call TI
Call TI
-40 to 125
NDW
7
250
RoHS (In
Work) & Green
(In Work)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14201
TZ-ADJ
TO-PMOD
NDW
7
45
RoHS (In
Work) & Green
(In Work)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14201
TZ-ADJ
TO-PMOD
NDW
7
500
RoHS (In
Work) & Green
(In Work)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14201
TZ-ADJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMZ14201TZ-ADJ/NOPB
LMZ14201TZX-ADJ/NOP
B
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TOPMOD
NDW
7
250
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
TOPMOD
NDW
7
500
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ14201TZ-ADJ/NOPB
TO-PMOD
NDW
7
250
367.0
367.0
45.0
LMZ14201TZX-ADJ/NOPB
TO-PMOD
NDW
7
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated