MCP6141/2/3/4 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Features: Description: • • • • • • • • • The MCP6141/2/3/4 family of non-unity gain stable operational amplifiers (op amps) from Microchip Technology Inc. operate with a single supply voltage as low as 1.4V, while drawing less than 1 µA (maximum) of quiescent current per amplifier. These devices are also designed to support rail-to-rail input and output operation. This combination of features supports battery-powered and portable applications. Low Quiescent Current: 600 nA/amplifier (typical) Gain Bandwidth Product: 100 kHz (typical) Stable for gains of 10 V/V or higher Rail-to-Rail Input/Output Wide Supply Voltage Range: 1.4V to 6.0V Available in Single, Dual, and Quad Chip Select (CS) with MCP6143 Available in 5-lead and 6-lead SOT-23 Packages Temperature Ranges: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C Applications: • • • • The MCP6141/2/3/4 family operational amplifiers are offered in single (MCP6141), single with Chip Select (CS) (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. The MCP6141 device is available in the 5-lead SOT-23 package, and the MCP6143 device is available in the 6-lead SOT-23 package. Toll Booth Tags Wearable Products Temperature Measurement Battery Powered Design Aids: • • • • • • SPICE Macro Models FilterLab® Software Mindi™ Simulation Tool Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Package Types MCP6141 PDIP, SOIC, MSOP MCP6143 PDIP, SOIC, MSOP NC 1 NC 1 8 NC VIN– 2 7 VDD VIN+ 3 6 VOUT VSS 4 Related Devices: • MCP6041/2/3/4: Unity Gain Stable Op Amps 5 NC VIN+ 3 V1 RF VOUT R3 V3 4 VIN– VIN+ 3 MCP614X VREF Inverting, Summing Amplifier © 2009 Microchip Technology Inc. VSS 2 VOUTA 1 8 VDD VINA– 2 7 VOUTB VINA– 2 6 VINB– VINA+ 3 VSS 4 5 VINB+ 7 VDD 6 VOUT 5 NC 6 VDD 5 CS 4 VIN– MCP6144 PDIP, SOIC, TSSOP VOUTA 1 VINA+ 3 8 CS MCP6143 SOT-23-6 VOUT 1 MCP6142 PDIP, SOIC, MSOP R2 VSS 4 5 VDD VSS 2 R1 VIN– 2 VIN+ 3 MCP6141 SOT-23-5 VOUT 1 Typical Application V2 The MCP6141/2/3/4 amplifiers have a gain bandwidth product of 100 kHz (typical) and are stable for gains of 10 V/V or higher. These specifications make these op amps appropriate for battery powered applications where a higher frequency response from the amplifier is required. VDD 4 14 VOUTD 13 VIND– 12 VIND+ 11 VSS VINB+ 5 10 VINC+ VINB– 6 9 VINC– VOUTB 7 8 VOUTC DS21668D-page 1 MCP6141/2/3/4 NOTES: DS21668D-page 2 © 2009 Microchip Technology Inc. MCP6141/2/3/4 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Analog Input Pins .........................................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings † Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ................................... –65°C to +150°C Maximum Junction Temperature (TJ)......................... .+150°C ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 400V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Drift with Temperature Power Supply Rejection VOS -3 — +3 mV ΔVOS/ΔTA — ±1.8 — µV/°C VCM = VSS VCM = VSS, TA= -40°C to +85°C ΔVOS/ΔTA — ±10 — µV/°C VCM = VSS, TA = +85°C to +125°C PSRR 70 85 — dB VCM = VSS Input Bias Current and Impedance IB — 1 — pA Industrial Temperature IB — 20 100 pA TA = +85° Extended Temperature IB — 1200 5000 pA TA = +125° IOS — 1 — pA 13 Input Bias Current Input Offset Current Common Mode Input Impedance ZCM — 10 ||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||6 — Ω||pF Common-Mode Input Range VCMR VSS−0.3 — VDD+0.3 V Common-Mode Rejection Ratio CMRR 62 80 — dB VDD = 5V, VCM = -0.3V to 5.3V CMRR 60 75 — dB VDD = 5V, VCM = 2.5V to 5.3V CMRR 60 80 — dB VDD = 5V, VCM = -0.3V to 2.5V AOL 95 115 — dB RL = 50 kΩ to VL, VOUT = 0.1V to VDD−0.1V VOL, VOH VSS + 10 — VDD − 10 mV RL = 50 kΩ to VL, 0.5V input overdrive VOVR VSS + 100 — VDD − 100 mV RL = 50 kΩ to VL, AOL ≥ 95 dB ISC — 2 — mA VDD = 1.4V ISC — 20 — mA VDD = 5.5V VDD 1.4 — 6.0 V Note 1 IQ 0.3 0.6 1.0 µA IO = 0 Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Linear Region Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: All parts with date codes February 2008 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V © 2009 Microchip Technology Inc. DS21668D-page 3 MCP6141/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 100 — kHz Slew Rate SR — 24 — V/ms Phase Margin PM — 60 — ° Input Voltage Noise Eni — 5.0 — Input Voltage Noise Density eni — 170 — nV/√Hz f = 1 kHz Input Current Noise Density ini — 0.6 — fA/√Hz f = 1 kHz G = +10 V/V Noise µVP-P f = 0.1 Hz to 10 Hz MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, and CL = 60 pF (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — VSS+0.3 V CS Input Current, Low ICSL — 5 — pA CS Logic Threshold, High VIH VDD–0.3 — VDD V CS Input Current, High ICSH — 5 — pA CS = VDD ISS — -20 — pA CS = VDD IOLEAK — 20 — pA CS = VDD CS Low to Amplifier Output Turn-on Time tON — 2 50 ms G = +1 V/V, CS = 0.3V to VOUT = 0.9VDD/2 CS High to Amplifier Output High-Z tOFF — 10 — µs G = +1 V/V, CS = VDD–0.3V to VOUT = 0.1VDD/2 VHYST — 0.6 — V VDD = 5.0V CS Low Specifications CS = VSS CS High Specifications CS Input High, GND Current Amplifier Output Leakage, CS High Dynamic Specifications Hysteresis CS VIL VIH tOFF tON VOUT High-Z ISS -20 pA (typical) ICS 5 pA (typical) High-Z -0.6 µA (typical) -20 pA (typical) 5 pA (typical) FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). DS21668D-page 4 © 2009 Microchip Technology Inc. MCP6141/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND. Parameters Sym. Min. Typ. Max. Units Conditions Specified Temperature Range TA -40 — +85 TA -40 — +125 °C Extended Temperature parts Operating Temperature Range TA -40 — +125 °C (Note 1) Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 6L-SOT-23 θJA — 230 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Temperature Ranges °C Industrial Temperature parts Thermal Package Resistances Note 1: 1.1 The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “Supply Bypass”. VDD VIN RN 0.1 µF 1 µF VOUT MCP614X CL VDD/2 RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD VDD/2 RN 0.1 µF 1 µF VOUT MCP614X CL VIN RG RL RF VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. © 2009 Microchip Technology Inc. DS21668D-page 5 MCP6141/2/3/4 NOTES: DS21668D-page 6 © 2009 Microchip Technology Inc. MCP6141/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 2 3 -8 -6 -4 -2 0 2 4 6 8 Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. © 2009 Microchip Technology Inc. 2% -8 -6 -4 -2 0 2 4 6 8 Input Offset Voltage Drift (µV/°C) 10 VDD = 5.5V TA = +125°C TA = +85°C 6.0 5.5 5.0 3.0 2.5 TA = +25°C TA = -40°C 2.0 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 1.5 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 TA = +25°C TA = -40°C 4% FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. Input Offset Voltage (µV) TA = +125°C TA = +85°C 6% -10 VDD = 1.4V -0.4 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 8% 0% 10 FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. 10% 1.0 8 12% 0.5 -6 -4 -2 0 2 4 6 Input Offset Voltage Drift (µV/°C) 234 Samples Representative Lot VDD = 5.5V VCM = VSS TA = +85°C to +125°C 14% 0.0 2267 Samples TA = -40°C to +85°C VCM = VSS -8 10 FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. Input Offset Voltage. 16% 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% -10 Input Offset Voltage (µV) -10 -0.5 Percentage of Occurrences FIGURE 2-1: -1 0 1 Input Offset Voltage (mV) 234 Samples Representative Lot VDD = 1.4V VCM = VSS TA = +85°C to +125°C 4.5 -2 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% 4.0 -3 Percentage of Occurrences 2396 Samples VCM = VSS 3.5 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% Percentage of Occurrences Percentage of Occurrences Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. DS21668D-page 7 MCP6141/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. 6 Input, Output Voltages (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-8: vs. Frequency. 200 150 100 80 50 40 PSRR (VCM = VSS) 90 85 80 CMRR (VDD = 5.0V, VCM = -0.3V to +5.3V) 75 Referred to Input 1 1 FIGURE 2-9: Frequency. DS21668D-page 8 10 10 5.5 FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. 95 60 30 5.0 -0.5 0 100 70 20 50 Common Mode Input Voltage (V) PSRR– PSRR+ CMRR 90 25 f = 1 kHz VDD = 5.0V 250 1000 Input Noise Voltage Density 100 CMRR, PSRR (dB) 10 100 Frequency (Hz) 20 4.5 Input Noise Voltage Density (nV/√Hz) 1 Time 10 (5 ms/div) 15 300 100 0.1 5 FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. PSRR, CMRR (dB) Input Noise Voltage Density (nV/√Hz) 1,000 0 4.0 Input Offset Voltage vs. -1 3.5 FIGURE 2-7: Output Voltage. VOUT 0 3.0 250 VIN 1 2.5 VDD = 5.5V 2 2.0 300 3 1.5 350 4 1.0 VDD = 1.4V 400 VDD = 5.0V G = +11 V/V 5 0.5 450 0.0 Input Offset Voltage (µV) 500 70 100 1k 100 1,000 Frequency (Hz) CMRR, PSRR vs. 10k 10,000 -50 -25 FIGURE 2-12: Temperature. 0 25 50 75 100 Ambient Temperature (°C) 125 CMRR, PSRR vs. Ambient © 2009 Microchip Technology Inc. MCP6141/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. 1k 1000 10000 10k VDD = 5.5V VCM = VDD 100 Input Bias, Offset Currents (pA) Input Bias and Offset Currents (pA) 10k 10000 IB 10 | IOS | 1 1 55 65 75 85 95 105 Ambient Temperature (°C) 115 125 FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. 10 | IOS | TA = +85°C 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. 0 130 100 -30 120 80 Phase -60 -90 60 40 Gain -120 20 -150 0 -180 -20 -210 DC Open-Loop Gain (dB) 120 Open-Loop Phase (°) Open-Loop Gain (dB) IB TA = +125°C 100 0.1 0.1 45 -40 -240 0.01 0.1 1.E+ 1 1.E+ 10 1.E+ 100 1.E+ 1k 1.E+ 10k 100k 1.E- 1.E1.E+ 02 01 00 Frequency 01 02(Hz)03 04 05 FIGURE 2-14: Frequency. Open-Loop Gain, Phase vs. 100 80 70 120 110 100 RL = 50 kΩ VOUT = 0.1V to VDD – 0.1V 80 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. © 2009 Microchip Technology Inc. VOUT = 0.1V to VDD – 0.1V 5.5 1k 10k 1.E+03 1.E+04 Load Resistance (Ω) FIGURE 2-17: Load Resistance. DC Open-Loop Gain (dB) 130 1.5 VDD = 1.4V 90 140 90 VDD = 5.5V 110 60 100 1.E+02 140 DC Open-Loop Gain (dB) 1k 1000 0.1 0.1 1.0 VDD = 5.5V 130 100k 1.E+05 DC Open-Loop Gain vs. RL = 50 kΩ 120 VDD = 5.5V 110 100 VDD = 1.4V 90 80 70 0.00 0.05 0.10 0.15 0.20 Output Voltage Headroom; VDD – VOH or VOL – VSS (V) 0.25 FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. DS21668D-page 9 MCP6141/2/3/4 FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). 90 90 80 80 70 70 60 60 50 50 GBWP 40 40 30 30 20 20 10 10 VDD = 1.4V 0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 50 0.6 0.5 0.4 0.3 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. DS21668D-page 10 5.0 4.5 4.0 3.5 5.5 60 50 40 40 30 30 20 10 20 10 VDD = 5.5V -50 -25 0 25 50 75 100 Ambient Temperature (°C) 0 125 FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. Output Short Circuit Current Magnitude (mA) Quiescent Current (µA/Amplifier) 0.7 70 PM (G = +10) 60 35 0.8 80 70 0 0 125 FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. 90 GBWP Phase Margin (°) PM (G = +10) 80 Common Mode Input Voltage FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Phase Margin (°) Gain Bandwidth Product (kHz) 90 3.0 10k 1.E+04 Frequency (Hz) Gain Bandwidth Product (kHz) 80 1k 1.E+03 VDD = 5.0V -0.5 Input Referred 2.5 90 2.0 100 PM (G = +10) 1.5 110 120 110 100 90 80 70 60 50 40 30 20 10 0 GBWP 1.0 120 0.5 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0.0 Gain Bandwidth Product (kHz) Channel-to-Channel Separation (dB) 140 Phase Margin (°) Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. 30 25 TA = -40°C TA = +25°C TA = +85°C TA = +125°C 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. © 2009 Microchip Technology Inc. MCP6141/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. Output Voltage Headroom, VDD – V OH or V OL – V SS (mV) Output Voltage Headroom; VDD – V OH or V OL – V SS (mV) 1000 100 VDD – VOH 10 VOL – VSS 1 0.01 0.1 1 Output Current Magnitude (mA) 10 FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. VDD = 5.5V RL = 50 kΩ VOL – VSS VDD – VOH -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. 10 Maximum Output Voltage Swing (VP-P) 40 35 Slew Rate (V/ms) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 30 High-to-Low 25 VDD = 5.5V 20 15 Low-to-High 10 VDD = 1.4V 5 0 -50 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-26: Temperature. 100 10k 1.E+04 80 G = -10 V/V RL = 50 kΩ 60 Voltage (20 mV/div) Output Voltage (20 mV/div) 1k 1.E+03 Frequency (Hz) FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. G = +11 V/V RL = 50 kΩ 60 VDD = 1.4V 1 0.1 100 1.E+02 125 Slew Rate vs. Ambient 80 VDD = 5.5V 40 40 20 20 0 0 -20 -20 -40 -40 -60 -60 -80 -80 0.0 0.1 0.2 0.3 Time 0.4 (100 0.5 µs/div) 0.6 0.7 FIGURE 2-27: Pulse Response. 0.8 0.9 1.0 Small Signal Non-inverting © 2009 Microchip Technology Inc. 0.0 0.1 0.2 FIGURE 2-30: Response. 0.3 Time 0.4 (100 0.5 µs/div) 0.6 0.7 0.8 0.9 1.0 Small Signal Inverting Pulse DS21668D-page 11 MCP6141/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low. 5.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0 FIGURE 2-31: Pulse Response. 25.0 20.0 2 2 5.0 On 4.5 4.0 17.5 3.5 15.0 3.0 VOUT High-Z 12.5 2.5 10.0 2.0 7.5 1.5 5.0 1.0 CS 2.5 2 Large Signal Non-inverting VDD = 5.0V G = +11 V/V VIN = +3.0V On 22.5 1 Time 1 (200 1 µs/div) 1 1 0.5 0.0 0.0 0 1 2 3 Time 4 (15 ms/div) 6 7 8 9 10 FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). Input Current Magnitude (A) 1.E-02 10m 1m 1.E-03 100µ 1.E-04 10µ 1.E-05 1µ 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 0 0 0 FIGURE 2-34: Response. Internal CS Switch Output (V) 0 Output Voltage (V) 0 CS Voltage (V) VDD = 5.0V G = -10 V/V RL = 50 kΩ 4.5 Output Voltage (V) Output Voltage (V) 5.0 VDD = 5.0V G = +11 V/V RL = 50 kΩ 4.5 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 Time 1 (200 1 µs/div) 1 1 2 2 2 Large Signal Inverting Pulse VOUT On Hysteresis CS High-to-Low CS Low-to-High VOUT High-Z VDD = 5.0V G = +11 V/V VIN = 3.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CS Voltage (V) FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). +125°C +85°C +25°C -40°C 10p 1.E-11 1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). DS21668D-page 12 © 2009 Microchip Technology Inc. MCP6141/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6141 MCP6142 MCP6143 MCP6144 MSOP, PDIP, SOIC SOT-23-5 MSOP, PDIP, SOIC MSOP, PDIP, SOIC SOT-23-6 MSOP, PDIP, SOIC Symbol 6 1 1 6 1 1 VOUT, VOUTA Analog Output (op amp A) 2 4 2 2 4 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) Description Positive Power Supply 7 5 8 7 6 4 VDD — — 5 — — 5 VINB+ Non-inverting Input (op amp B) — — 6 — — 6 VINB– Inverting Input (op amp B) — — 7 — — 7 VOUTB Analog Output (op amp B) — — — — — 8 VOUTC Analog Output (op amp C) — — — — — 9 VINC– Inverting Input (op amp C) — — — — — 10 VINC+ Non-inverting Input (op amp C) 4 2 4 4 2 11 VSS Negative Power Supply — — — — — 12 VIND+ Non-inverting Input (op amp D) — — — — — 13 VIND– Inverting Input (op amp D) — — — — — 14 VOUTD Analog Output (op amp D) — — — 8 5 — CS Chip Select 1, 5, 8 — — 1, 5 — — NC No Internal Connection 3.1 Analog Outputs The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.3 CS Digital Input 3.4 Power Supply Pins The positive power supply pin (VDD) is 1.4V to 6.0V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. © 2009 Microchip Technology Inc. DS21668D-page 13 MCP6141/2/3/4 NOTES: DS21668D-page 14 © 2009 Microchip Technology Inc. MCP6141/2/3/4 4.0 APPLICATIONS INFORMATION The MCP6141/2/3/4 family of op amps is manufactured using Microchip’s state of the art CMOS process These op amps are stable for gains of 10 V/V and higher. They are suitable for a wide range of general purpose, low power applications. See Microchip’s related MCP6041/2/3/4 family of op amps for applications needing unity gain stability. 4.1 dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 Rail-to-Rail Input 4.1.1 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad Input Stage Bond V – IN Pad VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Absolute Maximum Ratings † at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and © 2009 Microchip Technology Inc. VOUT R2 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-33. Applications that are high impedance may need to limit the usable voltage range. 4.1.3 VIN+ Bond Pad MCP604X V2 PHASE REVERSAL The MCP6141/2/3/4 op amps are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-10 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 D2 NORMAL OPERATION The input stage of the MCP6141/2/3/4 op amps uses two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS – 0.3V and VDD + 0.3V to ensure proper operation. There are two transitions in input behavior as VCM is changed. The first occurs, when VCM is near VSS + 0.4V, and the second occurs when VCM is near VDD – 0.5V (see Figure 2-3 and Figure 2-6). For the best distortion performance with non-inverting gains, avoid these regions of operation. DS21668D-page 15 MCP6141/2/3/4 4.2 Rail-to-Rail Output There are two specifications that describe the output swing capability of the MCP6141/2/3/4 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load condition. Thus, the output voltage swings to within 10 mV of either supply rail with a 50 kΩ load to VDD/2. Figure 2-10 shows how the output voltage is limited when the input goes beyond the linear region of operation. The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Range. This specification defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. To verify linear operation in this range, the large signal DC Open-Loop Gain (AOL) is measured at points inside the supply rails. The measurement must meet the specified AOL condition in the specification table. 4.3 Output Loads and Battery Life The MCP6141/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This prevents excessive current draw, and reduced battery life, when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 kΩ load resistor will cause the supply current to increase by 25 µA, depleting the battery 43 times as fast as IQ (0.6 µA, typical) alone. High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 µF capacitor at the output presents an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 VP-P sinewave (1.77 Vrms), under these conditions, is: EQUATION 4-1: PSupply = (VDD - VSS) (IQ + VL(p-p) f CL ) = (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF) = 3.0 µW + 50 µW This will drain the battery 18 times as fast as IQ alone. DS21668D-page 16 4.4 Stability 4.4.1 NOISE GAIN The MCP6141/2/3/4 op amp family is designed to give high bandwidth and slew rate for circuits with high noise gain (GN) or signal gain. Low gain applications should be realized using the MCP6041/2/3/4 op amp family; this simplifies design and implementation issues. Noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all other voltage sources are zeroed (shorted out). Noise gain is independent of signal gain and depends only on components in the feedback loop. The amplifier circuits in Figure 4-3 and Figure 4-4 have their noise gain calculated as follows: EQUATION 4-2: RF G N = 1 + ------- ≥ 10 V/V RG In order for the amplifiers to be stable, the noise gain should meet the specified minimum noise gain. Note that a noise gain of GN = +10 V/V corresponds to a non-inverting signal gain of G = +10 V/V, or to an inverting signal gain of G = -9 V/V. RIN VIN MCP614X RG VOUT RF FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. RG RF VOUT VIN RIN MCP614X FIGURE 4-4: Noise Gain for Inverting Gain Configuration. © 2009 Microchip Technology Inc. MCP6141/2/3/4 Figure 4-5 shows three example circuits that are unstable when used with the MCP6141/2/3/4 family. The unity gain buffer and low gain amplifier (non-inverting or inverting) are at gains that are too low for stability (see Equation 4-2).The Miller integrator’s capacitor makes it reach unity gain at high frequencies, causing instability. Note: The three circuits shown in Figure 4-5 are not to be used with the MCP6141/2/3/4 op amps. They are included for illustrative purposes only. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +10), a small series resistor at the output (RISO in Figure 4-6) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG RF RISO VOUT VA CL MCP614X Unity Gain Buffer VB VOUT VIN Low Gain Amplifier RG RF VOUT V1 RN MCP614X V2 FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-7 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -9 V/V gives GN = +10 V/V). 100,000 100k RF 1 + ------- < 10 RG Recommended R ISO (Ω) MCP614X 10k 10,000 Miller Integrator R C VOUT VIN GN = +10 GN = +20 GN ≥ +50 1k 1,000 1p 10p 100p 1n 1.E+00 1.E+01 1.E+02 1.E+03 Normalized Load Capacitance; CL/GN (F) MCP614X FIGURE 4-7: Recommended RISO Values for Capacitive Loads. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. 4.4.2 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. © 2009 Microchip Technology Inc. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6141/2/3/4 SPICE macro model are helpful. 4.5 MCP6143 Chip Select The MCP6143 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 50 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. DS21668D-page 17 MCP6141/2/3/4 4.6 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor is not required for most applications and can be shared with other nearby analog parts. 4.7 Unused Op Amps Guard Ring FIGURE 4-9: for Inverting Gain. 1. An unused op amp in a quad package (MCP6144) should be configured as shown in Figure 4-8. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp near its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6144 (A) ¼ MCP6144 (B) VDD VDD R1 VDD R 10R R2 Example Guard Ring Layout Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain (convert current to voltage, such as photo detectors) amplifiers: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. VREF R2 V REF = V DD ⋅ -------------------R1 + R2 FIGURE 4-8: 4.8 2. VIN– VIN+ Unused Op Amps. PCB Surface Leakage In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6141/2/3/4 family’s bias current at +25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-9. DS21668D-page 18 © 2009 Microchip Technology Inc. MCP6141/2/3/4 4.9 4.9.1 Application Circuits 4.9.2 BATTERY CURRENT SENSING The MCP6141/2/3/4 op amps’ Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current sensing applications. The very low quiescent current (0.6 µA, typical) help prolong battery life, and the rail-to-rail output supports detection low currents. Figure 4-10 shows a high side battery current sensor circuit. The 1 kΩ resistor is sized to minimize power losses. The battery current (IDD) through the 1 kΩ resistor causes its top terminal to be more negative than the bottom terminal. This keeps the common mode input voltage of the op amp below VDD, which is within its allowed range. When no current is flowing, the output will be at its Maximum Output Voltage Swing (VOH), which is virtually at VDD. . IDD INVERTING SUMMING AMPLIFIER The MCP6141/2/3/4 op amp is well suited for the inverting summing amplifier shown in Figure 4-11 when the resistors at the input (R1, R2, and R3) make the noise gain at least 10 V/V. The output voltage (VOUT) is a weighted sum of the inputs (V1, V2, and V3), and is shifted by the VREF input. The necessary calculations follow in Equation 4-3. . R1 V1 R2 V2 RF V3 MCP614X VREF FIGURE 4-11: 1.4V to 6.0V VOUT R3 Summing Amplifier. VDD 1 kΩ EQUATION 4-3: MCP6141 VOUT Noise Gain: 1- + ----1- + ----1-⎞ ≥ 10 V/V G N = 1 + R F ⎛ ----⎝R R 2 R 3⎠ 1 100 kΩ 1 MΩ V OUT = V DD – ( 1 kΩ ) ( 11 V/V )I DD FIGURE 4-10: Sensor. High Side Battery Current © 2009 Microchip Technology Inc. Signal Gains: G1 = –RF ⁄ R1 G2 = –RF ⁄ R2 G3 = –RF ⁄ R3 Output Signal: V OUT = V 1 G 1 + V 2 G 2 + V 3 G 3 + V REF G N DS21668D-page 19 MCP6141/2/3/4 NOTES: DS21668D-page 20 © 2009 Microchip Technology Inc. MCP6141/2/3/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6141/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6141/2/3/4 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Simulation Tool Microchip’s Mindi™ simulation tool aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online simulation tool available from the Microchip web site at www.microchip.com/mindi. This interactive simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi simulation tool can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Two of our boards that are especially useful are: • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV 5.6 Application Notes The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip.com/appnotes and are recommended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884: “Driving Capacitive Loads With Op Amps”, DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 These application notes and others are listed in the design guide: • “Signal Chain Design Guide”, DS21825 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. © 2009 Microchip Technology Inc. DS21668D-page 21 MCP6141/2/3/4 NOTES: DS21668D-page 22 © 2009 Microchip Technology Inc. MCP6141/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP6141) Device XXNN MCP6141 E-Temp Code Example: 6-Lead SOT-23 (MCP6143) Device XXNN MCP6143 E-Temp Code AW25 AWNN Note: Applies to 6-Lead SOT-23 Example: 8-Lead MSOP XXXXXX 6143I YWWNNN 918256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN * e3 Example: MCP6141 I/P256 0918 8-Lead SOIC (150 mil) Note: AS25 ASNN Note: Applies to 5-Lead SOT-23 OR MCP6141 E/P e3 256 0918 Example: MCP6142 I/SN0918 256 OR MCP6142E SN e3 0918 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS21668D-page 23 MCP6141/2/3/4 Package Marking Information (Continued) Example: 14-Lead PDIP (300 mil) (MCP6144) MCP6144-I/P XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 0918256 MCP6144 I/P e3 0918256 OR 14-Lead SOIC (150 mil) (MCP6144) Example: MCP6144ISL XXXXXXXXXX XXXXXXXXXX YYWWNNN 0918256 MCP6144 e3 I/SL^^ 0918256 OR Example: 14-Lead TSSOP (MCP6144) XXXXXXXX YYWW 6144ST 0918 NNN 256 OR 6144EST 0918 256 DS21668D-page 24 © 2009 Microchip Technology Inc. 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MCP6141/2/3/4 " # $%## .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 3# 4# 5$8 %1 44"" 5 5 =()* 6, 9 # / # !%% 6, <!# ! !1 / 6, 4 # 7 ; 1# ! !1 / 56 : : ( ;( ( : ( " <!# )* " )* )* .#4 # 4 .# # 4 .# > : ;> 4 ; : !/ = ; (". 4 !<!# 8 : 1, $ ! &% #$ , 08$#$ #8 # !-## # ! !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * ) © 2009 Microchip Technology Inc. DS21668D-page 27 MCP6141/2/3/4 " & ' ()) *+ &' .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 3# 4# 5$8 %1 5*9" 5 5 56 7 ; 1# )* # # 1 : : ( ( ( : : $! #$! <!# " ( ! !1 / ! !1 / ) # / # 1 " ( ; 6, 4 # ; =( # 4 ( ( ; ( 4 3 <!# # 1 !/ 4 !<!# 8 = 4- 4 !<!# 8 ; ) : : 6, - ? 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !@ !# "'( )*+) # & #, $ --#$## ! - * ;) DS21668D-page 28 © 2009 Microchip Technology Inc. MCP6141/2/3/4 ,- & ' ()) *+ &' .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 3# 4# 5$8 %1 5*9" 5 5 56 7 1# )* # # 1 : : ( ( ( : : $! #$! <!# " ( ! !1 / ! !1 / ) # / # 1 " ( ; 6, 4 # ( ( ( # 4 ( ( ; ( 4 3 <!# # 1 !/ 4 !<!# 8 ( = 4- 4 !<!# 8 ; ) : : 6, - ? 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !@ !# "'( )*+) # & #, $ --#$## ! - * () © 2009 Microchip Technology Inc. DS21668D-page 29 MCP6141/2/3/4 " (./01)*+' .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 3# 4# 5$8 %1 44"" 5 5 7 )* 6, 9 # / # !%%? 6, <!# ! !1 / 56 ; 1# ! !1 / β : : ( : : : ( " <!# 6, 4 # ( =)* " )* )* * % A # B ( : ( .#4 # 4 : .# # 4 .# > : ;> 4 !/ : ( 4 !<!# ". 8 : ( ! %# (> : (> ! %# )## (> : (> 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * () DS21668D-page 30 © 2009 Microchip Technology Inc. MCP6141/2/3/4 ,- (./01)*+' .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 3 e h b A2 A c φ L A1 β L1 3# 4# 5$8 %1 44"" 5 5 7 )* 6, 9 # / # !%%? 6, <!# ! !1 / 56 1# ! !1 / α h : : ( : : : ( " <!# 6, 4 # ( =)* " )* ;=()* * % A # B ( : ( .#4 # 4 : .# # 4 .# > : ;> 4 !/ : ( 4 !<!# ". 8 : ( ! %# (> : (> ! %# )## (> : (> 1, $ ! &% #$ , 08$#$ #8 # !-## # ! ? % #* # # !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * =() © 2009 Microchip Technology Inc. DS21668D-page 31 MCP6141/2/3/4 ,- 2 2 $ (-0-*+ .# #$ # / ## +22--- 2 ! - / 0 # 1 / % # # ! # D N E E1 NOTE 1 1 2 e b A2 A c A1 φ L L1 3# 4# 5$8 %1 44"" 5 5 7 1# =()* 6, 9 # ! !1 / 56 / # !%% 6, <!# : : ; ( ( : ( " =)* ! !1 / <!# " ! !1 / 4 # ( ( .#4 # 4 ( = ( .# # 4 .# > : ;> 4 : !/ ( ". 4 !<!# 8 : 1, $ ! &% #$ , 08$#$ #8 # !-## # ! !"!#$! !% #$ !% #$ # & !( !# "'( )*+ ) # & #, $ --#$## ".+ % 0$ $ -#$## 0%% # $ ! - * ;) DS21668D-page 32 © 2009 Microchip Technology Inc. MCP6141/2/3/4 APPENDIX A: REVISION HISTORY Revision D (May 2009) Revision A (September 2002) The following is the list of modifications: • Original Release of this Document. 1. 2. 3. 4. DC Electrical Charactistics table: Corrected formatting issue in Output section. AC Electrical Characteristics table: Slew Rate - changed typical value from 3.0 to 24. Changed Phase Margin from 65 to 60. Changed Phase Margin Condition from G=+1 to G=+10 V/V. Updated Package Outline Drawings Updated Revision History. Revision C (December 2007) • Updated Figures 2.4 and 2.5 • Expanded Analog Input Absolute Max Voltage Range (applies retroactively) • Expanded maximum operating VDD (going forward) • Section 1.0 “Electrical Characteristics” updated • Section 2.0 “Typical Performance Curves” updated • Section 4.0 “Applications Information” - Updated input stage explanation • Section 5.0 “Design Aids” updated Revision B (November 2005) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Added the following: a) SOT-23-5 package for the MCP6141 single op amps. b) SOT-23-6 package for the MCP6143 single op amps with Chip Select. c) Extended Temperature (-40°C to +125°C) op amps. Updated specifications in Section 1.0 “Electrical Characteristics” for E-temp parts. Corrected and updated plots in Section 2.0 “Typical Performance Curves”. Added Section 3.0 “Pin Descriptions”. Updated Section 4.0 “Applications Information” and added section on unused op amps. Updated Section 5.0 “Design Aids” to include FilterLab. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information in Section 6.0 “Packaging Information”. Added Appendix A: “Revision History”. © 2009 Microchip Technology Inc. DS21668D-page 33 MCP6141/2/3/4 NOTES: DS21668D-page 34 © 2009 Microchip Technology Inc. MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X / XX Examples: a) Device Device: Temperature Range MCP6141: MCP6141T: MCP6142: MCP6142T: MCP6143: MCP6143T: MCP6144: MCP6144T: Package Single Op Amp Single Op Amp (Tape and Reel for SOT-23, SOIC, MSOP) Dual Op Amp Dual Op Amp (Tape and Reel for SOIC and MSOP) Single Op Amp w/ CS Single Op Amp w/ CS (Tape and Reel for SOT-23, SOIC, MSOP) Quad Op Amp Quad Op Amp (Tape and Reel for SOIC and TSSOP) Temperature Range: I E = -40°C to +85°C (industrial) = -40°C to +125°C (extended) Package: = Plastic Small Outline Transistor (SOT-23), 6-lead (Tape and Reel - MCP6143 only) = Plastic Micro Small Outline (MSOP), 8-lead = Plastic Small Outline Transistor (SOT-23), 5-lead (Tape and Reel - MCP6141 only) = Plastic DIP (300 mil body), 8-lead, 14-lead = Plastic SOIC (3.9 mm body), 14-lead = Plastic SOIC (3.9 mm body), 8-lead = Plastic TSSOP (4.4 mm body), 14-lead CH MS OT P SL SN ST © 2009 Microchip Technology Inc. MCP6141-I/P: b) Industrial Temperature 8 lead PDIP package. MCP6141T-E/OT: Tape and Reel, Extended Temperature 5 lead SOT-23 package. a) MCP6142-I/SN: b) Industrial Temperature 8 lead SOIC package. MCP6142T-E/MS: Tape and Reel, Extended Temperature 8 lead MSOP package. a) MCP6143-I/P: b) Industrial Temperature, 8 lead PDIP package. MCP6143T-E/CH: Tape and Reel, Extended Temperature 6 lead SOT-23 package. a) MCP6144-I/SL: b) Industrial Temperature 14 lead PDIP package. MCP6144T-E/ST: Tape and Reel, Extended Temperature 14 lead TSSOP package. DS21668D-page 35 MCP6141/2/3/4 NOTES: DS21668D-page 36 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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