Siemens C504 8-bit cmos microcontroller Datasheet

Microcomputer Components
8-Bit CMOS Microcontroller
C504
Data Sheet 05.96
C504
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© Siemens AG 1996.
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8-Bit CMOS Microcontroller
C504
Advance Information
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Fully compatible to standard 8051 microcontroller
Up to 40 MHz operating frequency
16 K×8 ROM (C504-2R only, optional ROM protection)
256×8 RAM
256×8 XRAM
Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)
Three 16-bit timers/counters (timer 2 with up/down counter feature)
Capture/compare unit for PWM signal generation and signal capturing
- 3-channel, 16-bit capture/compare unit
- 1-channel, 10-bit compare unit
Compare unit
USART
10-bit A/D Converter with 8 multiplexed inputs
Twelve interrupt sources with two priority levels
On-chip emulation support logic (Enhanced Hooks Technology TM)
Programmable 15-bit Watchdog Timer
Oscillator Watchdog
Fast Power On Reset
Power Saving Modes
M-QFP-44 package
Temperature ranges: SAB-C504 TA : 0 to 70°C
SAF-C504
TA : – 40 to 85°C
SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD)
SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz)
Semiconductor Group
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05.96
C504
The C504 with its capture compare unit (CCU) especially provides a functionality, which allows to
use the microcontroller in motor control applications. Further, the C504 is functionally upward
compatible with the SAB 80C52/C501 microcontroller and can replace it in existing applications.
The C504-2R contains a non-volatile 16K×8 read-only program memory, a volatile on-chip 512×8
read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/
compare unit with compare timer, a 10-bit compare timer, a twelve source, two priority level interrupt
structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a
genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the
program memory on chip. Therefore, the term C504 refers to all versions within this data sheet
unless otherwise noted.
Ordering Information
Type
Ordering Code
Package
Description
(8-Bit CMOS microcontroller)
SAB-C504-LM
Q67120-C1048
P-MQFP-44 for external memory (12 MHz)
SAB-C504-L24M
Q67120-C1049
P-MQFP-44 for external memory (24 MHz)
SAB-C504-L40M
Q67120-C1050
P-MQFP-44 for external memory (40 MHz)
SAB-C504-2RM
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (12 MHz)
SAB-C504-2R24M
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz)
SAB-C504-2R40M
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz)
Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to
125 ˚C (SAK-C504) are available on request.
The ordering number of ROM types (DXXXX extensions) is defined after program release
(verification) of the customer.
Semiconductor Group
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C504
Figure 1
Logic Symbol
Semiconductor Group
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C504
Figure 2
Pin Configuration (top view)
Semiconductor Group
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C504
Table 1
Pin Definitions and Functions
Symbol
P1.0-P1.7
Pin Number
(P-MQFP-44)
40-44,
1-3
I/O
*)
Function
I/O
Port 1
is an 8-bit bidirectional port. Port pins can be used for
digital input/output. P1.0 - P1.3 can also be used as analog
inputs of the A/D-converter. As secondary digital functions,
port 1 contains the timer 2 pins and the capture/compare
inputs/outputs. Port 1 pins are assigned to be used as
analog inputs via the register P1ANA.
The functions are assigned to the pins of port 1 as follows:
P1.0 / AN0 / T2
Analog input channel 0 /
input to counter 2
P1.1 / AN1 / T2EX
Analog input channel 1 /
capture/reload trigger of timer 2 /
up-down count
P1.2 / AN2 / CC0
Analog input channel 2 /
input/output of capture/compare
channel 0
P1.3 / AN3 / COUT0 Analog input channel 3 /
output of capture/compare
channel 0
P1.4 / CC1
Input/output of capture/compare
channel 1
P1.5 / COUT1
Output of capture/compare
channel 1
P1.6 / CC2
Input/output of capture/compare
channel 2
P1.7 / COUT2
Output of capture/compare
channel 2
I
RESET
A high level on this pin for one machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to VSS permits power-on reset using only an
external capacitor to VCC.
40
41
42
43
44
1
2
3
RESET
*)
4
I = Input
O = Output
Semiconductor Group
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C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
P3.0-P3.7
Pin Number
(P-MQFP-44)
5, 7-13
I/O
*)
Function
I/O
Port 3
is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D)
operate as defined for the C501. P3.2 to P3.7 contain the
external interrupt inputs, timer inputs, input and as an
additional optinal function four of the analog inputs of the
A/D-converter. Port 3 pins are assigned to be used as
analog inputs via the bits of SFR P3ANA.
P3.6/WR can be assigned as a third interrupt input. The
functions are assigned to the pins of port 3 as follows:
P3.0 / RxD
Receiver data input (asynch.) or data
input/output (synch.) of serial
interface
P3.1 / TxD
Transmitter data output (asynch.) or
clock output (synch.) of serial
interface
P3.2 / AN4 / INT0 Analog input channel 4 / external
interrupt 0 input / timer 0 gate control
input
P3.3 / AN5 / INT1 Analog input channel 5 / external
interrupt 1 input / timer 1 gate control
input
P3.4 / AN6 / T0
Analog input channel 6 / timer 0
counter input
P3.5 / AN7 / T1
Analog input channel 7 / timer 1
counter input
P3.6 / WR / INT2 WR control output; latches the data
byte from port 0 into the external data
memory /
external interrupt 2 input
RD control output; enables the
P3.7 / RD
external data memory
I
CCU Trap Input
With CTRAP = low the compare outputs of the CAPCOM
unit are switched to the logic level as defined in the COINI
register (if they are enabled by the bits in SFR TRCON).
CTRAP is an input pin with an internal pullup resistor. For
power saving reasons, the signal source which drives the
CTRAP input should be at high or floating level during
power-down mode.
5
7
8
9
10
11
12
13
CTRAP
*)
6
I = Input
O = Output
Semiconductor Group
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C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
(P-MQFP-44)
I/O
*)
Function
XTAL2
14
–
XTAL2
Output of the inverting oscillator amplifier.
XTAL1
15
–
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. There
are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
divided down by a divide-by-two flip-flop. Minimum and
maximum high and low times as well as rise/fall times
specified in the AC characteristics must be observed.
P2.0-P2.7
18-25
I/O
Port 2
is a bidirectional I/O port with internal pullup resistors. Port
2 pins that have 1s written to them are pulled high by the
internal pullup resistors, and in that state can be used as
inputs. As inputs, port 2 pins being externally pulled low
will source current (IIL, in the DC characteris-tics) because
of the internal pullup resistors. Port 2 emits the high-order
address byte during fetches from external program
memory and during accesses to external data memory that
use 16-bit addresses (MOVX @DPTR). In this application
it uses strong internal pullup resistors when issuing 1s.
During accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of the
P2 special function register.
PSEN
26
O
The Program Store Enable
output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every six oscillator periodes except during
external data memory accesses. Remains high during
internal program execution.
ALE
27
O
The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every six oscillator periodes except during an external data
memory access. When instructions are executed from
internal ROM (EA=1) the ALE generation can be disabled
by bit EALE in SFR SYSCON.
*)
I = Input
O = Output
Semiconductor Group
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C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
(P-MQFP-44)
I/O
*)
Function
COUT3
28
O
10-Bit compare channel output
This pin is used for the output signal of the 10-bit compare
timer 2 unit. COUT3 can be disabled and set to a high or
low state.
EA
29
I
External Access Enable
When held at high level, instructions are fetched from the
internal ROM (C504-2R only) when the PC is less than
4000 H .When held at low level, the C504 fetches all
instructions from external program memory.
For the C504-L this pin must be tied low.
P0.0-P0.7
37-30
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float, and in that state can be used
as high-impendance inputs.Port 0 is also the multiplexed
low-order address and data bus during accesses to
external program or data memory. In this application it
uses strong internal pullup resistors when issuing 1 s.
Port 0 also outputs the code bytes during program
verification in the C504-2R. External pullup resistors are
required during program (ROM) verification.
VAREF
38
–
Reference voltage for the A/D converter.
VAGND
39
–
Reference ground for the A/D converter.
VSS
16
–
Ground (0V)
VCC
17
–
Power Supply (+5V)
*)
I = Input
O = Output
Semiconductor Group
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C504
Functional Description
The C504 basic architecture is fully compatible to the standard 8051 microcontroller family. While
maintaining all architectural and operational characteristics of the SAB 80C52 / C501, the C504
incorporates some enhancements such as on-chip XRAM, A/D converter, fail save mechanisms,
and a versatile capture/compare unit.
Figure 3 shows a block diagram of the C504.
Figure 3
Block Diagram of the C504
Semiconductor Group
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C504
CPU
The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % threebyte instructions. With a 12 MHz crystal, 58 % of the instructions are executed in 1.0µs (24 MHz:
500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0H)
Reset Value : 00H
Bit No. MSB
D0H
LSB
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
PSW
RS1
RS0
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
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C504
Memory Organization
The C504 CPU manipulates operands in the following four address spaces:
– up to 64 Kbyte of external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 256 bytes of internal XRAM data memory
– a 128 byte special function register area
Figure 4 illustrates the memory address spaces of the C504.
Figure 4
C504 Memory Map
The XRAM in the C504 is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX instructions) must be used for accessing
the XRAM. The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register.
ROM Protection
The C504-2R ROM version allows to protect the content of the internal ROM against read out by
non authorized people. The type of ROM protection (protected or unprotected) is fixed with the
ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM
protection has to be selected or not.
Semiconductor Group
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C504
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the
special function register area.
The 63 special function register (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits
within the SFR area.
The SFRs of the C504 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Semiconductor Group
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C504
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address Contents after
Reset
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
SYSCON System Control Register
E0H 1)
F0H 1)
83H
82H
D0H 1)
81H
B1H
00H
00H
00H
00H
00H
07H
XX10XXX0B 3)
Interrupt
System
IEN0
IEN1
CCIE 2)
IP0
IP1
ITCON
Interrupt Enable Register 0
Interrupt Enable Register 1
Capture/Compare Interrupt Enable Reg.
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Trigger Condition Register
A8H1)
A9H
D6H
B8H 1)
B9H
9AH
0X000000B 3)
XX000000B 3)
00H
XX000000B 3)
XX000000B 3)
00101010B
Ports
P0
P1
P1ANA 2)
P2
P3
P3ANA 2)
Port 0
Port 1
Port 1 Analog Input Selection Register
Port 2
Port 3
Port 3 Analog Input Selection Register
80H 1)
90H 1)
90H 1) 4)
A0H 1)
B0H 1)
B0H 1) 4)
FFH
FFH
XXXX1111B 3)
FFH
FFH
XX1111XXB 3)
A/DConverter
ADCON0
ADCON1
A/D Converter Control Register 0
A/D Converter Control Register 1
ADDATH A/D Converter Data Register High Byte
ADDATL A/D Converter Data Register Low Byte
P1ANA 2) Port 1 Analog Input Selection Register
P3ANA 2) Port 3 Analog Input Selection Register
D8H 1
DCH
D9H
DAH
90H 4)
B0H 4)
XX000000B 3)
01XXX000B 3)
00H
00XXXXXXB 3)
XXXX1111B 3)
XX1111XXB 3)
Serial
Channels
PCON 2)
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
87H
99H
98H 1)
000X0000B
XXH 3)
00H
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
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C504
Table 2
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address Contents after
Reset
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2 High Byte
Timer 2 Low Byte
C8H 1)
C9H
CBH
CAH
CDH
CCH
00H
XXXXXXX0B 3)
00H
00H
00H
00H
Capture /
Compare
Unit
CT1CON
CCPL
CCPH
CT1OFL
CT1OFH
CMSEL0
CMSEL1
COINI
TRCON
CCL0
CCH0
CCL1
CCH1
CCL2
CCH2
CCIR
CCIE 2)
CT2CON
CP2L
CP2H
CMP2L
CMP2H
BCON
Compare timer 1 control register
Compare timer 1 period register, low byte
Compare timer 1 period register, high byte
Compare timer 1 offset register, low byte
Compare timer 1 offset register, high byte
Capture/compare mode select register 0
Capture/compare mode select register 1
Compare output initialization register
Trap enable control register
Capture/compare register 0, low byte
Capture/compare register 0, high byte
Capture/compare register 1, low byte
Capture/compare register 1, high byte
Capture/compare register 2, low byte
Capture/compare register 2, high byte
Capture/compare interrupt request flag reg.
Capture/compare interrupt enable register
Compare timer 2 control register
Compare timer 2 period register, low byte
Compare timer 2 period register, high byte
Compare timer 2 compare register, low byte
Compare timer 2 compare register, high byte
Block commutation control register
E1H
DEH
DFH
E6H
E7H
E3H
E4H
E2H
CFH
C2H
C3H
C4H
C5H
C6H
C7H
E5H
D6H
C1H
D2H
D3H
D4H
D5H
D7H
00010000B
00H
00H
00H
00H
00H
00H
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00010000B
00H
XXXXXX00B 3)
00H
XXXXXX00B 3))
00H
Watchdog
WDCON Watchdog Timer Control Register
WDTREL Watchdog Timer Reload Register
C0H 1)
86H
XXXX0000B 3)
00H
87H
88H
000X0000B 3)
0XXXXXXXB 3)
Power
PCON 2)
Save Mode PCON1
Power Control Register
Power Control Register 1
4)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
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C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H 2) P0
81H SP
FFH
.7
.6
.5
.4
.3
.2
.1
.0
07H
.7
.6
.5
.4
.3
.2
.1
.0
82H
83H
DPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
DPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
86H
WDTREL 00H
WDT
PSEL
.6
.5
.4
.3
.2
.1
.0
87H
PCON
000X0000B
SMOD PDS
IDLS
–
GF1
GF0
PDE
IDLE
88H 2) TCON
88H 3) PCON1
00H
0XXXXXXXB
TF1
TF0
TR0
IE1
IT1
IE0
IT0
EWPD –
–
–
–
–
–
–
89H
8AH
TMOD
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
TL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8BH
8CH
TL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
TH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
8DH
TH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
90H2) P1
90H 2)3) P1ANA
FFH
.7
.6
.5
.4
.3
.2
T2EX
T2
XXXX1111B
–
–
–
–
EAN3
EAN2
EAN1
EAN0
98H 2) SCON
99H SBUF
00H
XXH
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
.7
.6
.5
.4
.3
.2
.1
.0
9AH
00101010B
IT2
IE2
I2ETF
I2ETR
I1ETF
I1ETR
I0ETF
I0ETR
A0H2) P2
FFH
.7
.6
.5
.4
.3
.2
.1
.0
A8H2) IEN0
0X000000B
EA
–
ET2
ES
ET1
EX1
ET0
EX0
A9H
XX000000B
–
–
ECT1
ECCM ECT2
ECEM EX2
EADC
FFH
RD
WR
T1
T0
INT0
RxD
ITCON
IEN1
B0H2) P3
TR1
INT1
TxD
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
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C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B0H2)3) P3ANA
EAN5
EAN4
–
–
B1H
XX1111XXB
–
–
EAN7
EAN6
SYSCON XX10XXX0B
–
–
EALE
RMAP –
–
–
XMAP
PX1
PT0
PX0
B8H2) IP0
XX000000B
–
–
PT2
PS
B9H
XX000000B
–
–
PCT1
PCCM PCT2
XXXX0000B
–
–
–
–
OWDS WDTS WDT
SWDT
IP1
C0H2) WDCON
PT1
PCEM PX2
PADC
C1H
CT2CON 00010000B
CT2P
ECT2O STE2
CT2
RES
CT2R
CLK2
CLK1
CLK0
C2H
C3H
CCL0
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH0
00H
.7
.6
.5
.4
.3
.2
.1
.0
C4H
C5H
CCL1
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH1
00H
.7
.6
.5
.4
.3
.2
.1
.0
C6H
C7H
CCL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
C8H2) T2CON
00H
TF2
EXF2
RCLK
TCLK
EXEN2 TR2
C/T2
CP/
RL2
C9H
T2MOD
XXXXXXX0B
–
–
–
–
–
–
–
DCEN
CAH
RC2L
00H
.7
.6
.5
.4
.3
.2
.1
.0
CBH
RC2H
00H
.7
.6
.5
.4
.3
.2
.1
.0
CCH
TL2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CDH
TH2
00H
.7
.6
.5
.4
.3
.2
.1
.0
CFH
TRCON
00H
TRPEN TRF
TREN5 TREN4 TREN3 TREN2 TREN1 TREN0
00H
00H
CY
AC
F0
RS1
RS0
OV
F1
P
.7
.6
.5
.4
.3
.2
.1
.0
D0H2) PSW
D2H
CP2L
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
18
C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr Register Content Bit 7
after
Reset1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D3H
CP2H
XXXX.
XX00B
–
–
–
–
–
–
.1
.0
D4H
CMP2L
00H
.7
.6
.5
.4
.3
.2
.1
.0
D5H
CMP2H
XXXX.
XX00B
–
–
–
–
–
–
.1
.0
D6H
CCIE
00H
ECTP
ECTC
CC2
FEN
CC2
REN
CC1
FEN
CC1
REN
CC0
FEN
CC0
REN
D7H
BCON
00H
BCMP PWM1 PWM0 EBCE
BCEM
BCERR BCEN
BCM1
BCM0
D8H2) ADCON0 XX000000B
–
–
IADC
BSY
ADM
MX2
MX1
MX0
D9H
DAH
ADDATH 00H
ADDATL 00XXXXXXB
.9
.8
.7
.6
.5
.4
.3
.2
.1
.0
–
–
–
–
–
–
DCH
ADCON1 01XXX000B
ADCL1 ADCL0 –
–
–
MX2
MX1
MX0
DEH
CCPL
00H
.7
.6
.5
.4
.3
.2
.1
.0
DFH
CCPH
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
E1H
00H
CT1CON 00010000B
CTM
ETRP
STE1
CT1
RES
CT1R
CLK2
CLK1
CLK0
E2H
COINI
COUT
3I
COUTX COUT
I
2I
CC2I
COUT
1I
CC1I
COUT
0I
CC0I
E3H
CMSEL0 00H
CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL
13
12
11
10
03
02
01
00
E4H
CMSEL1 00H
0
E5H
CCIR
E6H
CT1OFL 00H
CT1OFH 00H
E0H
2)
E7H
ACC
F0H2) B
FFH
00H
00H
0
0
0
CMSEL CMSEL CMSEL CMSEL
23
22
21
20
CT1FP CT1FC CC2F
CC2R
CC1F
CC1R
CC0F
CC0R
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
Semiconductor Group
19
C504
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4.
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
Gate
C/T
M1
M0
internal
external (max)
0
8-bit timer/counter with a
divide-by-32 prescaler
X
X
0
0
fOSC/12 × 32
fOSC/24 × 32
1
16-bit timer/counter
X
X
1
1
fOSC/12
fOSC/24
2
8-bit timer/counter with
8-bit autoreload
X
X
0
0
fOSC/12
fOSC/24
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
X
X
1
1
fOSC/12
fOSC/24
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 5 illustrates the
input clock logic.
Figure 5
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
20
C504
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Table 5
Timer/Counter 2 Operating Modes
T2CON
Mode
T2MOD T2CON
R×CLK
or
T×CLK
CP/
RL2
TR2
0
0
0
16-bit
Autoreload
16-bit
Capture
Input Clock
P1.1/
Remarks
T2EX
DCEN
EXEN
1
0
0
X
0
1
0
1
↓
0
0
0
0
1
1
1
1
X
X
0
1
0
1
1
X
0
X
0
1
1
X
1
↓
Baud
Rate
Generator
1
X
1
X
0
X
1
X
1
X
1
↓
off
X
X
0
X
X
X
Note: ↓ =
falling edge
Semiconductor Group
21
internal
external
(P1.0/T2)
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
fOSC/12
max
fOSC/24
16 bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
fOSC/12
max
fOSC/24
no overflow
interrupt
request (TF2)
extra external
interrupt
(“Timer 2”)
fOSC/2
max
fOSC/24
Timer 2 stops
–
–
C504
Capture/Compare Unit
The Capture / Compare Unit (CCU) of the C504 is built up by a 16-bit 3-channel capture/compare
unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit
provides two output signals per channel, which can have inverted signal polarity and nonoverlapping pulse transitions. The COMP unit can generate a single PWM output signal and is
further used to modulate the CAPCOM output signals. In capture mode, the value of the compare
timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx. Figure 6 shows
the block diagram of the CCU.
Figure 6
Block Diagram of the CCU
Semiconductor Group
22
C504
The compare timer 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers which
have each a count rate with a maximum of fOSC/2 up to fOSC/256. The compare timer operations with
its possible compare output signal waveforms are shown in figure 7.
Figure 7
Basic Operating Modes of the CAPCOM Unit
Compare timer 1 runs only in operating mode 1 with one output signal of selectable signal polarity
at the pin COUT3.
Semiconductor Group
23
C504
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 6.
Table 6
USART Operating Modes
Mode
SCON
Baudrate
Description
SM0
SM1
0
0
0
fOSC/12
1
0
1
Timer 1/2 overflow rate
2
1
0
fOSC/32 or fOSC/64
3
1
1
Timer 1/2 overflow rate
Serial data enters and exits through R×D.
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
9-bit UART
Like mode 2 except the variable baud rate
Figure 8
Block Diagram of Baud Rate Generation for the Serial Interface
Semiconductor Group
24
C504
The possible baudrates can be calculated using the formulas given in table 7.
Table 7
Formulas for Calculating Baudrates
Baud Rate
derived from
Interface Mode
Oscillator
0
2
Baudrate
f
(2
/12
OSC
SMOD
× fOSC) / 64
Timer 1 (16-bit timer)
(8-bit timer with
8-bit autoreload)
1,3
1,3
× timer 1 overflow rate) /32
(2
SMOD
(2
× fOSC) / (32 × 12 × (256-TH1))
Timer 2
1,3
fOSC / (32 × (65536-(RC2H, RC2L))
Semiconductor Group
SMOD
25
C504
10-Bit A/D Converter
The C504 has a high performance 10-bit A/D converter (figure 9) with 8 inputs included which uses
successive approximation technique for the conversion of analog input voltages.
Figure 9
A/D Converter Block Diagram
Semiconductor Group
26
C504
The A/D converter uses two clock signals for operation : the conversion clock fADC (= 1/ tADC) and
the input clock fIN (= 1/ tIN). Both clock signals are derived from the C504 system clock fOSC which
is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the fIN
clock signal. The table in figure 10 shows the prescaler ratios and the resulting A/D conversion
times which must be selected for typical system clock rates.
MCU System Clock fIN
Rate (fOSC)
[MHz]
Prescaler
ADCL0
fADC
[MHz]
A/D Conversion
Time [µs]
Ratio
ADCL1
3.5 MHz
1.75
÷4
0
0
.438
48 x tIN = 27.4
12 MHz
6
÷4
0
0
1.5
48 x tIN = 8
16 MHz
8
÷4
0
0
2
48 x tIN = 6
24 MHz
12
÷8
0
1
1.5
96 x tIN = 8
32 MHz
16
÷8
0
1
2
96 x tIN = 6
40 MHz
20
÷ 16
1
0
1.25
192 x tIN = 9.6
Figure 10
A/D Converter Clock Selection
The analog inputs are located at port 1 and port 3 (4 lines on each port). The corresponding port 1
and port 3 pins have a port structure, which allows to use it either as digital I/Os or analog inputs.
The analog input function of these mixed digital/analog port lines is selected via the registers
P1ANA and P3ANA.
Semiconductor Group
27
C504
Interrupt System
The C504 provides 12 interrupt sources with two priority levels. Figure 11 and 12 give a general
overview of the interrupt sources and illustrate the interrupt request and control flags.
Figure 11
Interrupt Request Sources (Part 1)
Semiconductor Group
28
C504
Figure 12
Interrupt Request Sources (Part 2)
Semiconductor Group
29
C504
Table 8
Interrupt Vector Addresses
Request Flags
Interrupt Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
IADC
IE2
TRF, BCERR
CT2P
CC0F-CC2F, CC0R-CC2R
CT1FP, CT1FC
–
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
A/D converter interrupt
External interrupt 2
CAPCOM emergency interrupt
Compare timer 2 interrupt
Capture / compare match interrupt
Compare timer 1 interrupt
Power-down interrupt
0003H
000BH
0013H
001BH
0023H
002BH
0043H
004BH
0053H
005BH
0063H
006BH
007BH
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 9
Interrupt Source Structure
Interrupt Source
High Priority
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Channel
Timer 2 Interrupt
Semiconductor Group
Priority
Low Priority
A/D Converter
External Interrupt 2
CCU Emergency Interrupt
Compare Timer 2 Interrupt
Capture / Compare Match Interrupt
Compare Timer 1 Interrupt
30
High h
Low
C504
Fail Save Mechanisms
The C504 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure.
– 15-bit reloadable watchdog timer
– Oscillator Watchdog
Watchdog Timer
The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either fSOC/
12 or fCYCLE/32. From the 15-bit watchdog timer count value only the upper 7 bits can be
programmed. Figure 5 shows the block diagram of the programmable watchdog timer.
Figure 13
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be
stopped during active mode of the device. If the software fails to refresh the running watchdog timer
an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog)
can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer
is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction
sequence has been implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and power down
mode of the processor. Therefore, it is possible to use the idle mode in combination with the
watchdog timer function.
Semiconductor Group
31
C504
Oscillator Watchdog
The oscillator watchdog of the C504 serves for three functions :
– Monitoring of the on-chip oscillator's function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504
is put into reset state; if the failure condition again disappears, the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.
– Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.
– Control of external wake-up from software power-down mode
When the power-down mode is left by a low level at the INT0 pin, the oscillator watchdog unit
assures that the microcontroller resumes operation (execution of the power-down wake-up
interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the onchip oscillator are stopped. Both oscillators are started again when power-down mode is
released. When the on-chip oscillator has a higher frequency than the RC oscillator, the
microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip
oscillator to stabilize.
Figure 14
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
32
C504
Power Saving Modes
Two power down modes are available, the idle mode and power down mode.
– In the idle mode the oscillator of the C504 continues to run, but the CPU is gated off from the
clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers
with the exception of the watchdog timer are further provided with the clock. The CPU status
is preserved in its entirety: the stack pointer, program counter, program status word,
accumulator, and all other registers maintain their data during idle mode.
– In the power down mode, the RC oscillator and the on-chip oscillator which operates with the
XTAL pins is stopped. Therefore all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are
controlled by their port latches, output the values that are held by their SFR's.
Table 10 gives a general overview of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Power-Down
Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillator is stopped;
Wake-up from power contents of on-chip RAM and
SFR’s are maintained;
down
In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC
is restored to its normal operating level, before the power down mode is terminated.
The idle mode can be terminated by activating any enabled peripheral interrupt or by resetting the
C504. The power down mode can be terminated using an interrupt by a short low pulse at the pin
P3.2/AN4/INT0 or by resetting the C504. If a power saving mode is left through an interrupt, the
microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by
a reset operation, the microcontroller state is disturbed and replaced by the reset state of the C504.
Semiconductor Group
33
C504
Absolute Maximum Ratings
Ambient temperature under bias (TA) .............................................................. 0 ˚C to + 70 ˚C
Storage temperature (TST)................................................................................– 65 ˚C to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS) ..............................................– 0.5 V to VCC + 0.5 V
Input current on any pin during overload condition ..........................................– 10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..........................| 100 mA |
Power dissipation.............................................................................................TBD
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
34
C504
DC Characteristics
TA = 0 to 70 °C
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
VCC = 5 V + 10%, – 15%; VSS = 0 V
Parameter
Symbol
Limit Values
min.
max.
for the SAB-C504
for the SAF-C504
for the SAH-C504
for the SAK-C504
Unit
Test Condition
Input low voltage (except EA,
RESET, CTRAP)
VIL
– 0.5
0.2 VCC –
0.1
V
–
Input low voltage (EA)
VIL1
– 0.5
0.2 VCC –
0.3
V
–
Input low voltage (RESET,
CTRAP)
VIL2
– 0.5
0.2 VCC +
0.1
V
–
0.2 VCC +
0.9
VCC + 0.5
V
–
Input high voltage (except XTAL1, VIH
RESET and CTRAP)
Input high voltage to XTAL1
VIH1
0.7 VCC
VCC + 0.5
V
–
Input high voltage to RESET and
CTRAP
VIH2
0.6 VCC
VCC + 0.5
V
–
Output low voltage (ports 1, 2, 3,
COUT3)
VOL
–
0.45
V
IOL = 1.6 mA 1)
Output low voltage (port 0, ALE,
PSEN)
VOL1
–
0.45
V
IOL = 3.2 mA 1)
2.4
0.9 VCC
–
–
V
IOH = – 80 µA,
IOH = – 10 µA
Output high voltage (ports 1, 2, 3) VOH
Output high voltage (ports 1,3 pins
in push-pull mode and COUT3)
VOH1
0.9 VCC
–
V
IOH = – 800 µA
Output high voltage (port 0 in
external bus mode, ALE, PSEN)
VOH2
2.4
0.9 VCC
–
–
V
IOH = – 800 µA 2),
IOH = – 80 µA 2)
Logic 0 input current (ports 1, 2, 3) IIL
– 10
– 50
µA
VIN = 0.45 V
Logical 1-to-0 transition current
(ports 1, 2, 3)
ITL
– 65
– 650
µA
VIN = 2 V
Input leakage current (port 0, EA)
ILI
–
±1
µA
0.45 < VIN < VCC
Pin capacitance
CIO
–
10
pF
fc = 1 MHz,
TA = 25 °C
Overload current
IOV
–
±5
mA
Semiconductor Group
35
7) 8)
C504
Parameter
Power supply current:
Active mode, 12 MHz 4)
Idle mode, 12 MHz 5)
Active mode, 24 MHz 4)
Idle mode, 24 MHz 5)
Active mode, 40 MHz 4)
Idle mode, 40 MHz 5)
Power-down mode
Symbol
ICC
ICC
ICC
ICC
ICC
ICC
IPD
Limit Values
typ. 9)
max.
16
8
25
13
38
17
1
TBD
TBD
TBD
TBD
TBD
TBD
50
Unit Test Condition
mA
mA
mA
mA
mA
mA
µA
VCC = 5 V, 4)
VCC = 5 V, 5)
VCC = 5 V, 4)
VCC = 5 V, 5)
VCC = 5 V, 4)
VCC = 5 V, 5)
VCC = 2…5.5 V 3)
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the
0.9 VCC specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = Port0 = VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; all other pins are disconnected.
4) ICC (active mode) is measured with:
XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = Port1 = RESET = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal
oscillator is used (appr. 1 mA).
5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected.
6) ICC max at other frequencies is given by:
active mode:
TBD
idle mode:
TBD
where fosc is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VCC and VSS
must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50
mA.
8) Not 100 % tested, guaranteed by design characterization.
9) The typical ICC values are periodically measured at TA = +25 ˚C but not 100% tested.
Semiconductor Group
36
C504
A/D Converter Characteristics
TA = 0 to 70 °C
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
VCC = 5 V + 10%, – 15%; VSS = 0 V
4V ≤ VAREF ≤ VCC + 0.1 V;
VSS – 0.1 V ≤ VAGND ≤ VSS + 0.2 V;
Parameter
Symbol
Limit Values
min.
max.
for the SAB-C504
for the SAF-C504
for the SAH-C504
for the SAK-C504
Unit
Test Condition
1)
Analog input voltage
VAIN
VAGND
VAREF
V
Sample time
tS
–
64 x tIN
32 x tIN
16 x tIN
8 x tIN
ns
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4 2)
Conversion cycle time
tADCC
–
384 x tIN
192 x tIN
96 x tIN
48 x tIN
ns
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4 3)
Total unadjusted error
TUE
–
±2
LSB
VSS + 0.5V ≤ VIN ≤ VCC – 0.5V 4)
–
±4
LSB
VSS < VIN < VSS + 0.5V
VCC – 0.5V < VIN < VCC
Internal resistance of
RAREF
reference voltage source
–
Internal resistance of
analog source
RASRC
–
ADC input capacitance
CAIN
tADC / 250 kΩ
tS / 500
kΩ
tS in [ns]
pF
6)
– 0.25
–
50
Clock calculation table :
ADCL1, 0
tADC
tS
tADCC
÷ 32
1
1
32 x tIN
64 x tIN
384 x tIN
÷ 16
1
0
16 x tIN
32 x tIN
192 x tIN
÷8
0
1
8 x tIN
16 x tIN
96 x tIN
÷4
0
0
4 x tIN
8 x tIN
48 x tIN
Further timing conditions : tADC min = 500 ns
tIN = 2 / fOSC = 2 tCLCL
Semiconductor Group
5) 6)
– 0.25
Notes see next page.
Clock Prescaler
Ratio
tADC in [ns]
37
2) 6)
4)
C504
Notes:
1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
3) This parameter includes the sample time tS, the time for determining the digital result and the time for the
calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on
the previous page.
4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100 % tested, but guaranteed by design characterization.
Semiconductor Group
38
C504
AC Characteristics for C504-L / C504-2R
TA = 0 to 70 °C
for the SAB-C504
TA = – 40 to 85 °C
for the SAF-C504
TA = – 40 to 110 °C
for the SAH-C504
TA = – 40 to 125 °C
for the SAK-C504
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
VCC = 5 V + 10%, – 15%; VSS = 0 V
Program Memory Characteristics
Parameter
Symbol
Limit Values
12-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
12 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
127
–
2tCLCL – 40
–
ns
Address setup to ALE
tAVLL
43
–
tCLCL – 40
–
ns
Address hold after ALE
tLLAX
30
–
tCLCL – 23
–
ns
ALE low to valid instr in
tLLIV
–
233
–
4tCLCL – 100 ns
ALE to PSEN
tLLPL
58
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
215
–
3tCLCL – 35
–
ns
PSEN to valid instr in
tPLIV
–
150
–
3tCLCL – 100 ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
63
–
tCLCL – 20
ns
Address valid after PSEN
tPXAV *)
75
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
–
302
–
5tCLCL – 115 ns
Address float to PSEN
tAZPL
0
–
0
–
*)
ns
Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
39
C504
AC Characteristics for C504-L / C504-2R (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
12-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
12 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
400
–
6tCLCL – 100 –
ns
WR pulse width
tWLWH
400
–
6tCLCL – 100 –
ns
Address hold after ALE
tLLAX2
114
–
2tCLCL – 53
–
ns
RD to valid data in
tRLDV
–
252
–
5tCLCL – 165 ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
97
–
2tCLCL – 70
ns
ALE to valid data in
tLLDV
–
517
–
8tCLCL – 150 ns
Address to valid data in
tAVDV
–
585
–
9tCLCL – 165 ns
ALE to WR or RD
tLLWL
200
300
3tCLCL – 50
3tCLCL + 50
Address valid to WR or RD
tAVWL
203
–
4tCLCL – 130 –
ns
WR or RD high to ALE high
tWHLH
43
123
tCLCL – 40
tCLCL + 40
ns
Data valid to WR transition
tQVWX
33
–
tCLCL – 50
–
ns
Data setup before WR
tQVWH
433
–
7tCLCL – 150 –
ns
Data hold after WR
tWHQX
33
–
tCLCL – 50
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
ns
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
max.
Oscillator period
tCLCL
83.3
294
ns
High time
tCHCX
20
tCLCL – tCLCX
ns
Low time
tCLCX
20
tCLCL – tCHCX
ns
Rise time
tCLCH
–
20
ns
Fall time
tCHCL
–
20
ns
Semiconductor Group
40
C504
AC Characteristics for C504-L24 / C504-2R24
TA = 0 to 70 °C
for the SAB-C504
TA = – 40 to 85 °C
for the SAF-C504
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
Program Memory Characteristics
Parameter
Symbol
Limit Values
24-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
24 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
43
–
2tCLCL – 40
–
ns
Address setup to ALE
tAVLL
17
–
tCLCL – 25
–
ns
Address hold after ALE
tLLAX
17
–
tCLCL – 25
–
ns
ALE low to valid instr in
tLLIV
–
80
–
4tCLCL – 87
ns
ALE to PSEN
tLLPL
22
–
tCLCL – 20
–
ns
PSEN pulse width
tPLPH
95
–
3tCLCL – 30
–
ns
PSEN to valid instr in
tPLIV
–
60
–
3tCLCL – 65
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
32
–
tCLCL – 10
ns
Address valid after PSEN
tPXAV *)
37
–
tCLCL – 5
–
ns
Address to valid instr in
tAVIV
–
148
–
5tCLCL – 60
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*)
Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
41
C504
AC Characteristics for C504-L24 / C504-2R24 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
24-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
24 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
180
–
6tCLCL – 70
–
ns
WR pulse width
tWLWH
180
–
6tCLCL – 70
–
ns
Address hold after ALE
tLLAX2
56
–
2tCLCL – 27
–
ns
RD to valid data in
tRLDV
–
118
–
5tCLCL – 90
ns
Data hold after RD
tRHDX
0
0
–
ns
Data float after RD
tRHDZ
–
63
–
2tCLCL – 20
ns
ALE to valid data in
tLLDV
–
200
–
8tCLCL – 133 ns
Address to valid data in
tAVDV
–
220
–
9tCLCL – 155 ns
ALE to WR or RD
tLLWL
75
175
3tCLCL – 50
3tCLCL + 50
ns
Address valid to WR
tAVWL
67
–
4tCLCL – 97
–
ns
WR or RD high to ALE high
tWHLH
17
67
tCLCL – 25
tCLCL + 25
ns
Data valid to WR transition
tQVWX
5
–
tCLCL – 37
–
ns
Data setup before WR
tQVWH
170
–
7tCLCL – 122 –
ns
Data hold after WR
tWHQX
15
–
tCLCL – 27
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min.
max.
Oscillator period
tCLCL
41.7
294
ns
High time
tCHCX
12
tCLCL – tCLCX
ns
Low time
tCLCX
12
tCLCL – tCHCX
ns
Rise time
tCLCH
–
12
ns
Fall time
tCHCL
–
12
ns
Semiconductor Group
42
C504
AC Characteristics for C504-L40 / C504-2R40
TA = 0 to 70 °C
for the SAB-C504
TA = – 40 to 85 °C
for the SAF-C504
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
Program Memory Characteristics
Parameter
Symbol
Limit Values
40-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
40 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
35
–
2tCLCL – 15
–
ns
Address setup to ALE
tAVLL
10
–
tCLCL – 15
–
ns
Address hold after ALE
tLLAX
10
–
tCLCL – 15
–
ns
ALE low to valid instr in
tLLIV
–
55
–
4tCLCL – 45
ns
ALE to PSEN
tLLPL
10
–
tCLCL – 15
–
ns
PSEN pulse width
tPLPH
60
–
3tCLCL – 15
–
ns
PSEN to valid instr in
tPLIV
–
25
–
3tCLCL – 50
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ *)
–
20
–
tCLCL – 5
ns
Address valid after PSEN
tPXAV *)
20
–
tCLCL – 5
–
ns
Address to valid instr in
tAVIV
–
65
–
5tCLCL – 60
ns
Address float to PSEN
tAZPL
–5
–
–5
–
ns
*)
Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
43
C504
AC Characteristics for C504-L40 / C504-2R40 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
40-MHz clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to
40 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
120
–
6tCLCL – 30
–
ns
WR pulse width
tWLWH
120
–
6tCLCL – 30
–
ns
Address hold after ALE
tLLAX2
35
–
2tCLCL – 15
–
ns
RD to valid data in
tRLDV
–
75
–
5tCLCL – 50
ns
Data hold after RD
tRHDX
0
0
–
ns
Data float after RD
tRHDZ
–
38
–
2tCLCL – 12
ns
ALE to valid data in
tLLDV
–
150
–
8tCLCL – 50
ns
Address to valid data in
tAVDV
–
150
–
9tCLCL – 75
ns
ALE to WR or RD
tLLWL
60
90
3tCLCL – 15
3tCLCL + 15
ns
Address valid to WR
tAVWL
70
–
4tCLCL – 30
–
ns
WR or RD high to ALE high
tWHLH
10
40
tCLCL – 15
tCLCL + 15
ns
Data valid to WR transition
tQVWX
5
–
tCLCL – 20
–
ns
Data setup before WR
tQVWH
125
–
7tCLCL – 50
–
ns
Data hold after WR
tWHQX
5
–
tCLCL – 20
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min.
max.
Oscillator period
tCLCL
25
294
ns
High time
tCHCX
10
tCLCL – tCLCX
ns
Low time
tCLCX
10
tCLCL – tCHCX
ns
Rise time
tCLCH
–
10
ns
Fall time
tCHCL
–
10
ns
Semiconductor Group
44
C504
Figure 15
Program Memory Read Cycle
Figure 16
Data Memory Read Cycle
Semiconductor Group
45
C504
Figure 17
Data Memory Write Cycle
Figure 18
External Clock Cycle
Semiconductor Group
46
C504
ROM Verification Characteristics for C504-2R
ROM Verification Mode 1
Parameter
Symbol
Limit Values
min.
max.
Unit
Address to valid data
tAVQV
–
48tCLCL
ns
ENABLE to valid data
tELQV
–
48tCLCL
ns
Data float after ENABLE
tEHQZ
0
48tCLCL
ns
Oscillator frequency
1/tCLCL
4
6
MHz
Figure 19
ROM Verification Mode 1
Semiconductor Group
47
C504
ROM Verification Mode 2
Parameter
Symbol
Limit Values
Unit
min.
typ
max.
ALE pulse width
tAWD
–
2 tCLCL
–
ns
ALE period
tACY
–
12 tCLCL
–
ns
Data valid after ALE
tDVA
–
–
4 tCLCL
ns
Data stable after ALE
tDSA
8 tCLCL
–
–
ns
P3.5 setup to ALE low
tAS
–
tCLCL
–
ns
Oscillator frequency
1/tCLCL
4
–
6
MHz
Figure 20
ROM Verification Mode 2
Semiconductor Group
48
C504
AC Inputs during testing are driven at VCC – 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
Figure 21
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 22
AC Testing : Float Waveforms
Figure 23
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
49