Renesas HD404328 Microcomputer designed to increase program productivity Datasheet

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Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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these changes do not constitute any alteration to the contents of the document itself.
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Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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contained therein.
HD404054 Series/HD404094 Series
Rev. 6.0
Sept. 1998
Description
The HD404054 Series and HD404094 Series are HMCS400-series microcomputers designed to increase
program productivity with large-capacity memory. Each microcomputer has three timers, one serial
interface, comparator, input capture circuit.
The HD404054 Series includes three chips: the HD404052 with 2-kword ROM; the HD404054 with 4kword ROM; and the HD4074054 with 4-kword PROM (ZTAT version). Also, the HD404094 Series
includes three chips: the HD404092 with 2-kword ROM; the HD404094 with 4-kword ROM; and the
HD4074094 with 4-kword PROM (ZTAT version).
The HD4074054 and HD4074094 are PROM version (ZTAT microcomputers). Program can be written
to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth
the process from debugging to mass production. (The ZTATversion is 27256-compatible.)
Features
• The differences between HD404054 Series and HD404094 Series
I/O pins
•
•
•
•
•
•
•
•
HD404054 Series
HD404094 Series
10 large-current output pins: Six 15-mA sinks
and four 10-mA sources
•
6 largecurrent output pins: Two 15-mA
sinks and four 10-mA sources
•
4 intermediate voltage output pins
27 I/O pins and 8 dedicated input pins
Three timer/counters
Eight-bit input capture circuit
Two timer outputs (including two PWM outputs)
One event counter inputs (including one double-edge function)
One clock-synchronous 8-bit serial interface
Comparator (2 channels)
Built-in oscillators
 Main clock: Ceramic or crystal oscillator (an external clock is also possible)
HD404054 Series/HD404094 Series
• Six interrupt sources
 Two by external sources
 Four by internal sources
• Subroutine stack up to 16 levels, including interrupts
• Two low-power dissipation modes
 Standby mode
 Stop mode
• One external input for transition from stop mode to active mode
• Instruction cycle time: 1 µs (fOSC = 4 MHz at 1/4 division ratio)
 1/4, or 1/32 division ratio can be selected by hardware
• Two operating modes
 MCU mode
 MCU/PROM mode (HD4074054, HD4074094)
Ordering Information
Product Name
Type
HD404054 Series
HD404094 Series
ROM (words)
RAM (digit)
Package
Mask ROM
HD404052H
HD404092H
2,048
512
FP-44A
HD404052S
HD404092S
ZTAT
HD40A4052H
FP-44A
HD40A4052S
DP-42S
HD404054H
HD404094H
HD404054S
HD404094S
4,096
FP-44A
DP-42S
HD40A4054H
FP-44A
HD40A4054S
DP-42S
HD4074054H
HD4074094H
HD4074054S
HD4074094S
ZTAT: Zero Turn Around Time
2
DP-42S
4,096
ZTAT is a trademark of Hitachi, Ltd.
FP-44A
DP-42S
HD404054 Series/HD404094 Series
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DP-42S
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
SEL
R43 /SO1
R42 /SI 1
R41 /SCK1
R40 /EVND
R33
R32 /TOD
R31 /TOC
R30
R23
R22
R21
R20
R13
R12
R11
R10
R00 /INT1
D13 /INT0
D12 /STOPC
FP-44A
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
R40 /EVND
R33
R32 /TOD
R31 /TOC
R30
R23
R22
R21
R20
R13
R12
D5
D6
D7
D8
D9
D12 /STOPC
D 13 /INT0
R0 0 /INT1
R10
R11
NC
RE0/VCref
TEST
OSC1
OSC2
RESET
GND
D0
D1
D2
D3
D4
44
43
42
41
40
39
38
37
36
35
34
NC
RC0
RD3
RD2
RD1 /COMP1
RD0 /COMP0
VCC
SEL
R4 3 /SO 1
R4 2 /SI1
R4 1 /SCK 1
RD 0 /COMP0
RD 1 /COMP1
RD2
RD3
RC0
RE 0 /VCref
TEST
OSC1
OSC2
RESET
GND
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Top view
3
HD404054 Series/HD404094 Series
Pin Description
Pin Number
Item
Symbol
DP-42S
FP-44A
42
38
Applies power voltage
GND
11
6
Connected to ground
Test
TEST
7
2
I
Used for factory testing only: Connect this pin to VCC
Reset
RESET
10
5
I
Resets the MCU
Oscillator
OSC 1
8
3
I
OSC 2
9
4
O
D0–D 9
12–21
7–16
I/O*
Power supply VCC
Port
I/O
Function
Input/output pins addressed by individual bits; pins
D0–D 3 are high-current source pins that can each
supply up to 10 mA.
The HD404054 Series: pins D 4–D 9are high-current
sink pins that can each supply up to 15mA.
The HD404094 Series: D 4–D 7 are intermediate
voltage (12 V) NMOS open-drain pins, and D8, D9 are
high-current sink pins that can each supply up to 15
mA.
D12,D13
22, 23
17, 18
I
Input pins addressable by individual bits
R0 0–R4 3
24–40
19–36
I/O
Input/output pins addressable in 4-bit units
RD0–RD3,
1–6
39–43,1 I
Input pins addressable in 4-bit units
RC0, RE 0
Interrupt
INT0, INT1
23, 24
18, 19
I
Input pins for external interrupts
Stop clear
STOPC
22
17
I
Input pin for transition from stop mode to active mode
Serial
SCK 1
38
34
I/O
Serial clock input/output pin
SI 1
39
35
I
Serial receive data input pin
SO1
40
36
O
Serial transmit data output pin
TOC, TOD 34, 35
30, 31
O
Timer output pins
EVND
37
33
I
Event count input pins
COMP0,
1, 2
39, 40
I
Analog input pins for voltage comparator
6
1
41
37
Timer
Comparator
COMP1
VC ref
Division rate SEL
Reference voltage pin for inputting the threshold
voltage of the analog input pin.
I
Input pin for selecting system clock division rate after
RESET input or after stop mode cancellation.
1/4 division rate: Connect it to V CC
1/32 division rate: Connect it to GND
Note: * D4–D 7 of the HD404094 Series are output pins.
4
HD404054 Series/HD404094 Series
GND
V CC
SEL
OSC 2
OSC 1
STOPC
TEST
RESET
Block Diagram
System control
External
interrupt
RAM
(512 × 4bit)
Timer
A
D port
INT0
INT1
W (2bit)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
High
current
source
pins
High
current
sink pins
Intermediate
voltage NMOS
open-drain
output pins*
X (4bit)
SI1
SO1
SCK1
VCref
COMP0
COMP1
Y (4bit)
Timer
D
Serial
1
Comparator
SPY (4bit)
ALU
CPU
ST
CA
(1bit) (1bit)
A (4bit)
Internal data bus
TOD
SPX (4bit)
Internal address bus
EVND
Timer
C
Internal data bus
TOC
RE port RC port RD port R4 port R3 port R2 port R1 port R0 port
D 12
D 13
R0 0
R10
R11
R12
R13
R2 0
R2 1
R2 2
R2 3
R3 0
R3 1
R3 2
R3 3
R4 0
R4 1
R4 2
R4 3
RD0
RD1
RD2
RD3
RC0
RE 0
B (4bit)
SP (10bit)
Instruction
decoder
PC (14bit)
ROM
(4,096 × 10bit)
(2,048 × 10bit)
Note: * Only HD404094 Series
: Data bus
: Signal line
5
HD404054 Series/HD404094 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$07FF (HD404052, HD40A4052, HD404092), $0000–$0FFF (HD404054,
HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding.
0
$0000
Vector address
$000F
15
$0010
16
Zero-page subroutine
(64 words)
$003F
63
64
2047
Program & Pattern
2048 words
(HD404052, HD40A4052,
HD404092)
$0040
$07FF
4096 words
(HD404054, HD40A4054,
HD4074054,HD404094,
HD4074094)
4095
0
JMPL instruction
1 (Jump to RESET, STOPC routine)
JMPL instruction
2
(Jump to INT0 routine)
3
JMPL instruction
4
(Jump to INT1 routine)
5
6
7
8
9
JMPL instruction
(Jump to timer A routine)
10
11
12
13
14
15
JMPL instruction
(Jump to timer C, routine)
Not used
JMPL instruction
(Jump to timer D, routine)
JMPL instruction
(Jump to serial 1 routine)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0FFF
Figure 1 ROM Memory Map
RAM Memory Map
The MCU contains a 512-digit × 4-bit RAM area consisting of a memory register area, a data area, and a
stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.
6
HD404054 Series/HD404094 Series
0
$000
RAM-mapped registers
64
Memory registers (MR)
80
$040
$050
Not used
$090
144
0
3
4
5
6
7
8
9
Interrupt control bits area
Port mode register A
(PMRA) W
Serial mode register 1A (SM1A) W
Serial data register 1 lower (SR1L) R/W
Serial data register 1 upper (SR1U) R/W
Timer mode register A
(TMA) W
$000
$003
$004
$005
$006
$007
$008
$009
Not used
Data (432 digits)
$240
576
Not used
960
$3C0
Stack (64 digits)
$3FF
1023
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(MIS)
Miscellaneous register
Timer mode register C1 (TMC1)
(TRCL/TWCL)
Timer C
(TRCU/TWCU)
Timer mode register D1 (TMD1)
(TRDL/TWDL)
Timer D
(TRDU/TWDU)
Not used
Timer mode register C2 (TMC2)
Timer mode register D2 (TMD2)
Not used
Compare data register
(CDR)
(CER)
Compare enable register
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R
W
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
Not used
R:
Read only
W:
Write only
R/W: Read/Write
31
32
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Register flag area
Port mode register B
(PMRB)
(PMRC)
Port mode register C
Not used
W
W
Detection edge select register 2 (ESR2)
(SM1B)
W
W
(DCD0)
(DCD1)
(DCD2)
W
W
W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
W
W
W
W
W
Serial mode register 1B
Not used
Port D0 to D3 DCR
Port D4 to D 7 DCR
Port D8 and D9 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
Not used
Two registers are mapped
on the same area.
63
$03F
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E
15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F
17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011
18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
7
HD404054 Series/HD404094 Series
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$018, $024–$034)
This area is used as mode registers and data registers for external interrupts, serial interface 1,
timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits
can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($090–$23F): 432 digits from $090 to $23F.
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
8
HD404054 Series/HD404094 Series
Bit 3
Bit 2
Bit 1
Bit 0
0
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
$000
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
Not used
Not used
$002
3
IMS1
(IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
Interrupt control bits area
Bit 3
Bit 2
Bit 1
Bit 0
32
Not used
Not used
WDON
(Watchdog
on flag)
Not used
$020
33
RAME
(RAM enable
flag)
Not used
ICEF
(Input capture
error flag)
ICSF
(Input capture
status flag)
$021
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IF
ICSF
ICEF
RAME
RSP
WDON
Not used
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed
Allowed
Not executed
Allowed
Not executed
Not executed
Inhibited
Inhibited
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
If the TM or TDM instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
HD404054 Series/HD404094 Series
Bit 3
Bit 2
$000
$003
: Not used
Interrupt control bits area
R42/SI1
PMRA $004
SM1A $005
Bit 0
Bit 1
R41/SCK1
R43/SO1
Serial transmit clock speed selection 1
SR1L $006
Serial data register 1 (lower digit)
SR1U $007
Serial data register 1 (upper digit)
TMA $008
MIS $00C
TMC1 $00D
Clock source selection (timer A)
*2
*1
SO 1 PMOS control
Clock source selection (timer C)
TRCL/TWCL $00E
Timer C register (lower digit)
TRCU/TWCU $00F
Timer C register (upper digit)
TMD1 $010
*1
Clock source selection (timer D)
TRDL/TWDL $011
Timer D register (lower digit)
TRDU/TWDU $012
Timer D register (upper digit)
$013
Timer-C output mode selection
TMC2 $014
TMD2 $015
*3
Timer-D output mode selection
$016
CDR $017
CER $018
*4
Result of each analog input comparison
*5
$020
Register flag area
$023
R00/INT1
PMRB $024
PMRC $025
D13/INT0
D12/STOPC
R40/EVND
$026
ESR2 $027 EVND detection edge selection
*6
SM1B $028
*7
DCD0 $02C
Port D3 DCR Port D2 DCR
Port D1 DCR Port D0 DCR
DCD1 $02D
Port D7 DCR Port D6 DCR
Port D5 DCR Port D4 DCR
DCD2 $02E
Port D9 DCR Port D8 DCR
DCR0 $030
Port R0 0 DCR
DCR1 $031
Port R13 DCR Port R1 2 DCR Port R1 1 DCR Port R1 0 DCR
DCR2 $032
Port R2 3 DCR Port R2 2 DCR Port R2 1 DCR Port R2 0 DCR
DCR3 $033
Port R3 3 DCR Port R3 2 DCR Port R3 1 DCR Port R3 0 DCR
DCR4 $034
Port R4 3 DCR Port R4 2 DCR Port R4 1 DCR Port R4 0 DCR
$03F
Notes:
1. Auto-reload on/off
2. Pull-up MOS control
3. Input capture selection
4. Comparator switch
5. Port/comparator selection
6. SO1 output level control in idle states
7. Serial clock source selection 1
Figure 5 Special Function Register Area
10
HD404054 Series/HD404094 Series
Memory registers
MR(0) $040
64
MR(1) $041
65
MR(2) $042
66
MR(3)
$043
67
MR(4)
$044
68
MR(5)
$045
69
MR(6)
$046
70
MR(7)
$047
71
MR(8)
$048
72
MR(9)
$049
73
MR(10) $04A
74
MR(11) $04B
75
MR(12) $04C
76
MR(13) $04D
77
MR(14) $04E
78
MR(15) $04F
79
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
1023 Level 1
960
$3C0
$3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC 12
PC11
$3FC
1021
PC 10
PC9
PC 8
PC7
$3FD
1022
CA
PC6
PC 5
PC4
$3FE
1023
PC 3
PC2
PC 1
PC0
$3FF
PC13 –PC0 : Program counter
ST:
Status flag
CA:
Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
11
HD404054 Series/HD404094 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
Initial value: Undefined, R/W
W register
Initial value: Undefined, R/W
0
(B)
1
0
(W)
3
X register
Initial value: Undefined, R/W
0
(X)
3
Y register
0
(Y)
Initial value: Undefined, R/W
3
SPX register
Initial value: Undefined, R/W
SPY register
Initial value: Undefined, R/W
Carry
Initial value: Undefined, R/W
Status
Initial value: 1, no R/W
0
(SPX)
3
0
(SPY)
0
(CA)
0
(ST)
13
Program counter
Initial value: 0,
no R/W
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
1
5
1
1
1
0
(SP)
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
12
HD404054 Series/HD404094 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction-but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN
instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
13
HD404054 Series/HD404094 Series
Table 1
Initial Values After MCU Reset
Item
Abbr.
Initial
Value
Program counter
(PC)
$0000
Indicates program execution point from start
address of ROM area
Status flag
(ST)
1
Enables conditional branching
Stack pointer
(SP)
$3FF
Stack level 0
Contents
Interrupt
Interrupt enable flag
(IE)
0
Inhibits all interrupts
flags/mask
Interrupt request flag
(IF)
0
Indicates there is no interrupt request
Interrupt mask
(IM)
1
Prevents (masks) interrupt requests
Port data register
(PDR)
All bits 1 Enables output at level 1
Data control register
(DCD0 – All bits 0 Turns output buffer off (to high impedance)
DCD2)
I/O
(DCR0–
DCR4)
All bits 0
Port mode register A
(PMRA)
- - 00
Refer to description of port mode register A
Port mode register B
(PMRB)
---0
Refer to description of port mode register B
Port mode register C
bits 3, 2, 1
(PMRC3, 000 PMRC2,
PMRC1)
Refer to description of port mode register C
Detection edge select
register 2
(ESR2)
00 - -
Disables edge detection
Timer/
Timer mode register A
(TMA)
- 000
Refer to description of timer mode register A
counters,
Timer mode register C1 (TMC1)
0000
Refer to description of timer mode register C1
serial
Timer mode register C2 (TMC2)
- 000
Refer to description of timer mode register C2
interface
Timer mode register D1 (TMD1)
0000
Refer to description of timer mode register D1
Timer mode register D2 (TMD2)
0000
Refer to description of timer mode register D2
Serial mode register 1A (SM1A)
0000
Refer to description of serial mode register 1A
Serial mode register 1B (SM1B)
- - X0
Refer to description of serial mode register 1B
Prescaler S
(PSS)
$000
—
Timer counter A
(TCA)
$00
—
Timer counter C
(TCC)
$00
—
Timer counter D
(TCD)
$00
—
Timer write register C
(TWCU,
TWCL)
$X0
—
Timer write register D
(TWDU,
$X0
—
Octal counter
TWDL)
000
—
(CER)
0 - 00
Refer to description of voltage comparator
Comparator Compare enable
register
14
HD404054 Series/HD404094 Series
Item
Bit register
Others
Abbr.
Watchdog timer on flag
Initial
Value
(WDON) 0
Contents
Refer to description of timer C
Input capture status flag (ICSF)
0
Refer to description of timer D
Input capture error flag
(ICEF)
0
Refer to description of timer D
Miscellaneous register
(MIS)
00 - -
Refer to description of operating modes, and
oscillator circuit
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Serial data register
(SRL, SRU)
RAM
RAM enable flag
Status After
Status After
Cancellation of Stop Cancellation of Stop
Mode by STOPC Input Mode by MCU Reset
Pre-stop-mode values are not guaranteed;
values must be initialized by program
Status After all Other
Types of Reset
Pre-MCU-reset values
are not guaranteed;
values must be
initialized by program
Pre-stop-mode values are retained
(RAME)
Port mode register 1 (PMRC12)
bit 2
1
0
0
Pre-stop-mode values
are retained
0
0
Interrupts
The MCU has 6 interrupt sources: Two external signals (INT0, INT1), Three timer/counters (timers A, C,
and D), and one serial interface (serial 1).
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
15
HD404054 Series/HD404094 Series
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 6 interrupt sources are listed in
table 3.
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2
Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
Vector Address
RESET, STOPC*
—
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Not used
4
$0008
Timer C
5
$000A
Timer D
6
$000C
Serial 1
7
$000E
Note: * The STOPC interrupt request is valid only in stop mode.
16
HD404054 Series/HD404094 Series
$ 000,0
IE
INT0 interrupt
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
$ 000,2
IFO
$ 000,3
IMO
Vector
address
Priority control logic
INT1 interrupt
$ 001,0
IF1
$ 001,1
IM1
Timer A interrupt
$ 001,2
IFTA
$ 001,3
IMTA
Not used
Timer C interrupt
$ 002,2
IFTC
$ 002,3
IMTC
Timer D interrupt
$ 003,0
IFTD
$ 003,1
IMTD
$ 003,2
Serial 1 interrupt
IFS1
$ 003,3
IMS1
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
17
HD404054 Series/HD404094 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
INT0
INT1
Timer A
Timer C
Timer D
Serial 1
IE
1
1
1
1
1
1
IF0 · IM0
1
0
0
0
0
0
IF1 · IM1
*
1
0
0
0
0
IFTA · IMTA
*
*
1
0
0
0
IFTC · IMTC
*
*
*
1
0
0
IFTD · IMTD
*
*
*
*
1
0
IFS1 · IMS1
*
*
*
*
*
1
Note: * Can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution *
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
18
Execution of
instruction at
start address
of interrupt
routine
HD404054 Series/HD404094 Series
Power on
RESET = 0?
Yes
No
Interrupt
request?
No
Yes
No
IE = 1?
Yes
Reset MCU
Accept interrupt
Execute instruction
IE ← 0
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ←(PC) + 1
PC← $0002
Yes
INT0
interrupt?
No
PC← $0004
Yes
INT1
interrupt?
No
PC← $0006
Yes
Timer-A
interrupt?
No
PC ← $000A
Yes
Timer-C
interrupt?
No
PC ← $000C
Yes
Timer-D
interrupt?
No
PC ← $000E
(serial 1 interrupt)
Figure 10 Interrupt Processing Flowchart
19
HD404054 Series/HD404094 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4
Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input
to INT0 and INT1 as listed in table 5.
Table 5
External Interrupt Request Flags (IF0, IF1: $000, $001)
IF0, IF1
Interrupt Request
0
No
1
Yes
External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the
corresponding external interrupt request flags, as listed in table 6.
Table 6
ExternalInterrupt Masks (IM0, 1M1: $000, $001)
IM0, IM1
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
Interrupt Request
0
No
1
Yes
20
HD404054 Series/HD404094 Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.
Table 8
Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 9.
Table 9
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC
Interrupt Request
0
No
1
Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 10.
Table 10
Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
11.
Table 11
Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD
Interrupt Request
0
No
1
Yes
21
HD404054 Series/HD404094 Series
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 12.
Table 12
Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD
Interrupt Request
0
Enabled
1
Disabled (masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13
Serial Interrupt Request Flag (IFS1: $003, Bit 2)
IFS1
Interrupt Request
0
No
1
Yes
Serial Interrupt Masks (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14
Serial Interrupt Mask (IMS1: $003, Bit 3)
IMS1
Interrupt Request
0
Enabled
1
Disabled (masked)
22
HD404054 Series/HD404094 Series
Operating Modes
The MCU has Three operating modes as shown in table 15. The operations in each mode are listed in
tables 16 and 17. Transitions between operating modes are shown in figure 11.
Table 15
Operating Modes and Clock Status
Mode Name
Active
Standby
Stop
Activation method
SBY instruction
RESET cancellation,
interrupt request,
STOPC cancellation in
stop mode
STOP instruction
Status
OP
Stopped
System oscillator
OP
RESET input,
RESET input, interrupt RESET input, STOPC
STOP/SBY instruction request
input in stop mode
Cancellation method
Note: OP implies in operation
Table 16
Operations in Low-Power Dissipation Modes
Function
Stop Mode
Standby Mode
CPU
Reset
Retained
RAM
Retained
Retained
Timer A
Reset
OP
Timer C
Reset
OP
Timer D
Reset
OP
Serial interface 1
Reset
OP
Comparator
Reset
Stopped
I/O
Reset*
Retained
Note: OP implies in operation
* Output pins are at high impedance.
Table 17
I/O Status in Low-Power Dissipation Modes
Output
Input
Standby Mode
Stop Mode
Active Mode
D0–D 9
Retained
High impedance
Input enabled
D12, D13, RC0,
—
—
Input enabled
Retained or output of
peripheral functions
High impedance
Input enabled
RD0–RD3, RE 0
R0–R4
23
HD404054 Series/HD404094 Series
Reset by
RESET input or
by watchdog timer
fOSC: Main oscillation
frequency
fcyc: f OSC/4 or or fOSC /32
(hardware selectable)
ø CPU: System clock
ø PER: Clock for other
peripheral functions
RAME = 0
RESET1
RESET2
STOPC
Active
mode
Standby mode
fOSC: Oscillate
ø CPU: Stop
ø PER: fcyc
RAME = 1
SBY
Interrupt
Stop mode
(TMA3 = 0)
fOSC: Oscillate
ø CPU: fcyc
ø PER: fcyc
STOP
fOSC:
ø CPU:
ø PER:
Stop
Stop
Stop
Figure 11 MCU Status Transitions
Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1
and OSC2.
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 12.
24
HD404054 Series/HD404094 Series
Stop
Standby
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
No
RESET = 0?
Yes
No
RESET = 0?
Yes
IF0 • IM0 = 1?
No
No
STOPC = 0?
Yes
IF1 • IM1 = 1?
No
Yes
Yes
IFTA • IMTA
= 1?
No
Yes
RAME = 1
RAME = 0
IFTC •
IMTC = 1?
Yes
No
IFTD •
IMTD = 1?
Yes
No
IFS1 •
IMS1 = 1?
No
Yes
Restart
processor clocks
Restart
processor clocks
Execute
next instruction
No
Reset MCU
IF = 1,
IM = 0, and
IE = 1?
Execute
next instruction
Yes
Accept interrupt
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. The MCU enters
stop mode if the STOP instruction is executed in active mode.
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
25
,
HD404054 Series/HD404094 Series
Stop mode
Oscillator
Internal
clock
STOP
or RESET
tres
STOP instruction execution
tres ≥ tRC (stabilization period)
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by RESET. In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequences shown in figures 14 to 16. It is reset by
an asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
26
HD404054 Series/HD404094 Series
Power on
RESET = 0?
No
Yes
RAME = 0
MCU
operation
cycle
Reset MCU
Figure 14 MCU Operating Sequence (Power On)
27
HD404054 Series/HD404094 Series
MCU operation
cycle
IF = 1?
No
Instruction
execution
Yes
SBY/STOP
instruction?
Yes
No
IM = 0 and
IE = 1?
Yes
IE ← 0
Stack ← (PC),
(CA),
(ST)
No
Low-power mode
operation cycle
IF:
IM:
IE:
PC:
CA:
ST:
PC ← Next
location
PC ← Vector
address
Interrupt request flag
Interrupt mask
Interrupt enable flag
Program counter
Carry flag
Status flag
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
28
HD404054 Series/HD404094 Series
Low-power mode
operation cycle
IF = 1 and
IM = 0?
No
Yes
Stop mode
Standby mode
No
IF = 1 and
IM = 0?
Yes
No
STOPC = 0?
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
PC ← Next
Iocation
PC ← Next
Iocation
Reset MCU
Instruction
execution
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
29
HD404054 Series/HD404094 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 18, a ceramic
oscillator can be connected to OSC 1 and OSC2. The system oscillator can also be operated by an external
clock.
After RESET input or after stop mode has been cancelled, the division ratio of the system clock can be
selected as 1/4 or 1/32 by setting the SEL pin level.
• 1/4 division ratio: Connect SEL to VCC.
• 1/32 division ratio: Connect SEL to GND.
OSC2
OSC1
System fOSC
oscillator
1/4 or
1/32
division
circuit*
fcyc
tcyc
Timing
generator
circuit
φCPU
φPER
Note: * 1/4 or 1/32 division ratio can be selected by SEL pin.
Figure 17 Clock Generation Circuit
RE 0
TEST
OSC 1
OSC 2
RESET
GND
GND
Figure 18 Typical Layout of Ceramic Oscillator
30
CPU with ROM,
RAM, registers,
flags, and I/O
Peripheral
function
interrupt
HD404054 Series/HD404094 Series
Table 18
Oscillator Circuit Examples
Circuit Configuration
External clock
operation
Ceramic oscillator
(OSC1, OSC 2)
Circuit Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator: CSB400P22 (Murata),
C1
OSC1
Ceramic
oscillator
CSB400P (Murata)
Rf = 1 MΩ ± 20%
Rf
C1 = C2 = 220 pF ± 5%
OSC2
C2
GND
Ceramic oscillator: CSB800J122 (Murata),
CSB800J (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 220 pF ± 5%
Ceramic oscillator: CSA2.00MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Ceramic oscillator: CSA4.00MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Ceramic oscillator: CSA3.58MG (Murata)
Rf = 1 MΩ ± 20%
C1 = C2 = 30 pF ± 20%
Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of
the board, the user should consult with the ceramic oscillator manufacturer to determine the
circuit parameters.
2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross
other wiring (see figure 18).
31
HD404054 Series/HD404094 Series
Input/Output
The MCU has 27 input/output pins (D0–D9, R0 0–R4 3) and 8 input pins (D12, D13, RC0, RD0– RD3, RE 0). The
features are described below. Some input/output pins have different features between the HD404054 Series
and HD404094 Series. The differences between the HD404054 Series and HD404094 Series are listed in
table 19.
• A maximum current of 15 mA is allowed for each of the pins D 4 to D9 with a total maximum current of
less than 105 mA. In addition, D0–D3 can each act as a 10-mA maximum current source.
• Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial
interface. For these pins, the peripheral function setting is done prior to the D or R port setting.
Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection
are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R43/SO1 pin can be set to NMOS opendrain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Pins D0–D3 have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs,
which can be individually turned on or off by software.
I/O buffer configuration is shown in figure 19 programmable I/O circuits are listed in table 20, and I/O pin
circuit types are shown in table 21.
Table 19
The differences between HD404054 Series and HD404094 Series
HD404054 Series
HD404094 Series
Large-current source pins (15 mA)
D0–D 3
D0–D 3
Large-current sink pins (10 mA)
D4–D 9
D8, D9
Intermediate voltage NMOS open-drain
pins (12 V)

D4–D 7 (output only)
Pull-down MOS current pins
D0–D 3
D0–D 3
Pull-up MOS current pins
D4–D 9, R0–R4
D8, D9, R0–R4
32
HD404054 Series/HD404094 Series
Table 20-1 Programmable I/O Circuits (with pull-up MOS)
MIS3 (Bit 3 of MIS)
0
DCD, DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS buffer
Pull-up MOS
1
1
0
1
Note: — indicates off status.
Table 20-2 Programmable I/O Circuits (with pull-down MOS)
MIS3 (Bit 3 of MIS)
0
DCD, DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
On
—
On
—
CMOS buffer
Pull-down MOS
1
1
0
1
Note: — indicates off status.
D4–D 9, R port (HD404054 Series)
D8, D9, R port (HD404094 Series)
HLT
Pull-up control signal
VCC
Pull-up
MOS
MIS3
VCC
Buffer control signal
DCD, DCR
Output data
PDR
Input data
Input control signal
Figure 19-1 I/O Buffer Configuration (with pull-up MOS)
33
HD404054 Series/HD404094 Series
D0–D 3 port
Input control signal
VCC
Input data
Buffer control signal
DCD, DCR
Output data
PDR
MIS3
Pull-down control signal
HLT
Figure 19-2 I/O Buffer Configuration (with pull-down MOS)
34
HD404054 Series/HD404094 Series
Table 21
Circuit Configurations of I/O Pins
Pins
HD404054
Series
HD404094
Series
HLT
D4–D 9,
D8, D9,
MIS3
R0–R4
R0–R4
D0–D 3
D0–D 3
R4 3
R4 3
—
D4–D 7
I/O Pin Type Circuit
Input/output
pins
VCC
Pull-up control signal
Buffer control
signal
VCC
DCD, DCR
Output data
PDR
Input data
Input control signal
Input control signal
VCC
Input data
Buffer control signal
DCD, DCR
Output data
PDR
MIS3
Pull-down control
signal
HLT
VCC
HLT
VCC
Pull-up control signal
Buffer control
signal
Output data
MIS3
DCR
MIS2
PDR
Input data
Input control signal
HLT
Output pins
DCD
Output data
PDR
35
HD404054 Series/HD404094 Series
Pins
I/O Pin Type
Circuit
Input data
Input pins
VCC
Input data
VCC
SO1
SO1
TOC, TOD
TOC, TOD
HLT
SI 1, INT1,
SI 1, INT1,
MIS3
EVND
EVND
MIS3
SCK1
SCK1
HLT
VCC
Pull-up control signal
MIS3
PMOS control
signal
Output data
VCC
Pull-up control signal
Output data
Input pins
MIS2
SO1
HLT
VCC
D12, D13, RC0
SCK 1
Pull-up control signal
Output data
Output
pins
D12, D13, RC0
SCK 1
HLT
VCC
HD404094
Series
RD0–RD3, RE 0 RD0–RD3, RE 0
Input control signal
Periphera Input/
l function output pins
pins
HD404054
Series
VCC
MIS3
TOC, TOD
PDR
Input data
Input data
SI1, INT1,
EVND
INT0,
INT0,
STOPC STOPC
INT0,
STOPC
Note: The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal
becomes low, and input/output pins enter high-impedance state.
D Port (D0–D13): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D3 are highcurrent sources, and D12 and D 13 are input-only pins. D4–D9 of the HD404054 Series are high-current sinks.
D4–D7 of the HD404094 Series are middle voltage output-only pins, and D8 and D9 are high-current sink
pins.
Pins D 0–D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D13 are tested by the TD and
TDD instructions.
36
HD404054 Series/HD404094 Series
The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 20).
Pins D12 and D 13 are multiplexed with peripheral function pins S TOP C and INT0, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 22).
R Ports (R0 0–RE0): 17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these
ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output
data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R
ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034) that are mapped to
memory addresses (figure 20).
Pin R0 0 is are multiplexed with peripheral pin INT1 respectively. The peripheral function modes of these
pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21).
Pins R31–R32 are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function
modes of these pins are selected by bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014),
and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24).
Pin R40 is multiplexed with peripheral pin EVND respectively. The peripheral function modes of these
pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22).
Pins R41–R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral
function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and
bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26.
Ports RD0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively. The
function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018)
(figure 27).
Port RE 0 is multiplexed with peripheral function pin VCref. While functioning as VC ref , do not use this pin
as an R port at the same time, otherwise, the MCU may malfunction.
Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS
transistor is provided for each input/output pin other than input-only pins D 12 and D 13. The on/off status of
all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off
status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding
pin—enabling on/off control of that pin alone (table 20 and figure 28).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by
their pull-up MOS transistors or by resistors of about 100 kΩ or pulled down to GND by their pull-down
MOS transistors.
Note: *If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B
register.
37
HD404054 Series/HD404094 Series
Data control register
(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034)
DCD0, DCD1
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
DCD03– DCD02– DCD01– DCD00–
DCD13 DCD12 DCD11 DCD10
DCD2
Bit
3
2
1
0
Initial value
—
—
0
0
—
—
W
Read/Write
Bit name
Not used Not used DCD21
W
DCD20
DCR0
Bit
3
2
1
Initial value
—
—
—
0
Read/Write
—
—
—
W
Bit name
0
Not used Not used Not used DCR00
DCR1 to DCR4
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
DCR13– DCR12– DCR11– DCR10–
DCR43 DCR42 DCR41 DCR40
All Bits
CMOS Buffer On/Off Selection
0
Off (high-impedance)
1
On
Correspondence between ports and DCD/DCR bits
Register Name
Bit 3
Bit 2
Bit 1
Bit 0
DCD0
D3
D2
D1
D0
DCD1
D7
D6
D5
D4
DCD2
—
—
D9
D8
DCR0
—
—
—
R00
DCR1
R13
R12
R11
R10
DCR2
R23
R22
R21
R20
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
Figure 20 Data Control Registers (DCD, DCR)
38
HD404054 Series/HD404094 Series
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
—
—
—
0
—
—
—
W
Read/Write
Bit name
Not used Not used Not used PMRB0
PMRB0
R00/INT1 mode selection
0
R00
1
INT1
Figure 21 Port Mode Register B (PMRB)
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
0
—
Read/Write
W
W
W
—
Bit name
PMRC3 PMRC2*
PMRC1 Not used
PMRC1
R40/EVND mode selection
0
R40
1
EVND
PMRC2
D12/STOPC mode selection
0
D12
1
STOPC
PMRC3
D13/INT0 mode selection
0
D13
1
INT0
Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop
mode, PMRC2 is not reset but retains its value.
Figure 22 Port Mode Register C (PMRC)
39
HD404054 Series/HD404094 Series
Timer mode register C2 (TMC2: $014)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
R/W
R/W
R/W
TMC21
TMC20
Bit name
Not used TMC22
TMC22
TMC21
TMC20
0
0
0
R31
R31 port
1
TOC
Toggle output
0
TOC
0 output
1
TOC
1 output
0
—
Inhibited
TOC
PWM output
1
1
0
R31/TOC mode selection
1
1
0
1
Figure 23 Timer Mode Register C2 (TMC2)
40
HD404054 Series/HD404094 Series
Timer mode register D2 (TMD2: $015)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
TMD23
TMD22
TMD21
TMD20
Bit name
R32/TOD mode selection
TMD23
TMD22
TMD21
TMD20
0
0
0
0
R32
R32 port
1
TOD
Toggle output
0
TOD
0 output
1
TOD
1 output
0
—
Inhibited
1
TOD
PWM output
×
R32
Input capture (R32 port)
1
1
0
1
1
×
1
0
×
× : Don’t care
Figure 24 Timer Mode Register D2 (TMD2)
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
Not used Not used PMRA1 PMRA0
PMRA0
R43/SO1 mode selection
0
R43
1
SO1
PMRA1
R42/SI1 mode selection
0
R42
1
SI1
Figure 25 Port Mode Register A (PMRA)
41
HD404054 Series/HD404094 Series
Serial mode register 1A (SM1A: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM1A3
SM1A2
SM1A1
SM1A0
Bit name
SM1A3
R41/SCK1
mode selection
0
R41
1
SCK1
Prescaler
division
ratio
SM1A2
SM1A1
SM1A0
SCK1
Clock source
0
0
0
Output
Prescaler
÷ 2048
1
Output
Prescaler
÷ 512
0
Output
Prescaler
÷ 128
1
Output
Prescaler
÷ 32
0
Output
Prescaler
÷8
1
Output
Prescaler
÷2
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
Figure 26 Serial Mode Register 1A (SM1A)
Compare enable register (CER: $018)
Bit
3
2
1
0
Initial value
0
—
0
0
Read/Write
W
—
W
W
CER3
Not used
CER1
CER0
Bit name
CER3
Digital/Analog selection
CER1
CER0
Digital input mode:
RD0 /COMP0 and RD1 /COMP1
operate as an R port.
0
0
COMP0
0
0
1
COMP1
1
0
Not used
1
Analog input mode:
RD0 /COMP0 and RD 1 /COMP1
operate as analog input.
1
1
Not used
Figure 27 Compare Enable Register
42
Analog input pin selection
HD404054 Series/HD404094 Series
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
—
—
W
W
—
—
MIS3
MIS2
Read/Write
Bit name
MIS3
Pull-up MOS
on/off selection
Not used Not used
MIS2
CMOS buffer
on/off selection
for pin R43/SO1
0
Off
0
On
1
On
1
Off
Figure 28 Miscellaneous Register (MIS)
43
HD404054 Series/HD404094 Series
Prescalers
The MCU has the following prescaler S.
The prescaler operating conditions are listed in table 22, and the prescaler output supply is shown in figure
29. The timers A, C, D input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset.
Table 22
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Condition
Stop Conditions
Prescaler S
System clock
MCU reset
MCU reset, stop mode
Timer A
Timer C
System
clock
Prescaler S
Timer D
Serial 1
Figure 29 Prescaler Output Supply
44
HD404054 Series/HD404094 Series
Timers
The MCU has three timer/counters (A, C, and D).
• Timer A: Free-running timer
• Timer C: Multifunction timer
• Timer D: Multifunction timer
Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are
listed in table 23. The operating modes are selected by software.
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
The block diagram of timer A is shown in figure 30.
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 31.
45
HD404054 Series/HD404094 Series
Table 23
Timer Functions
Functions
Clock source
Timer functions
Timer outputs
Timer A
Timer C
Timer D
Prescaler S
Available
Available
Available
External event
—
—
Available
Free-running
Available
Available
Available
Event counter
—
—
Available
Reload
—
Available
Available
Watchdog
—
Available
—
Input capture
—
—
Available
Toggle
—
Available
Available
0 output
—
Available
Available
1 output
—
Available
Available
PWM
—
Available
Available
Note: — means not available.
Timer A interrupt
request flag
(IFTA)
Timer
counter A
(TCA) Overflow
Internal data bus
Clock
System
clock
ø PER
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Prescaler S (PSS)
3
Timer mode
register A
(TMA)
Figure 30 Block Diagram of Timer A
46
HD404054 Series/HD404094 Series
Timer mode register A (TMA: $008)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
W
W
W
Not used
TMA2
TMA1
TMA0
Bit name
Source
Input clock
TMA2 TMA1 TMA0 prescaler frequency Operating mode
0
0
1
1
0
1
0
PSS
2048tcyc
1
PSS
1024tcyc
0
PSS
512tcyc
1
PSS
128tcyc
0
PSS
32tcyc
1
PSS
8tcyc
0
PSS
4tcyc
1
PSS
2tcyc
Timer A mode
Note: Timer counter overflow output period (seconds) = input clock period (seconds) × 256.
Figure 31 Timer Mode Register A (TMA)
47
HD404054 Series/HD404094 Series
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle, 0, 1, and PWM outputs)
The block diagram of timer C is shown in figure 32.
System
reset signal
Watchdog on
flag (WDON)
TOC
Timer C interrupt
flag (IFTC)
Watchdog timer
control logic
Timer output
control logic
Timer read register CU (TRCU)
Timer output
control
Timer read
register CL
(TRCL)
Timer counter C
(TCC)
Timer write
register CU
(TWCU)
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
Selector
System øPER
clock
Prescaler S (PSS)
Overflow
Free-running
/reload control
Timer write
register CL
(TWCL)
3
Timer mode
register C1
(TMC1)
3
Timer mode
register C2
(TMC2)
Figure 32 Block Diagram of Timer C
48
Internal data bus
Clock
HD404054 Series/HD404094 Series
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.
• Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).
Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
 Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input
after timer C has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 33.
 PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 33.
 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after
timer C has reached $FF. Note that this function must be used only when the output level is high.
 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer
C has reached $FF. Note that this function must be used only when the output level is low.
49
HD404054 Series/HD404094 Series
Toggle output waveform (timers C, and D)
Free-running timer
256 clock cycles
256 clock cycles
Reload timer
(256 – N) clock cycles (256 – N) clock cycles
PWM output waveform (timers C and D)
T × (N + 1)
TMC13 = 0
TMD13 = 0
T
T × 256
TMC13 = 1
TMD13 = 1
T × (256 – N)
Notes: The waveform is always fixed low when N = $FF.
T: Input clock period to counter (figures 34 and 41)
N: The value of the timer write register
Figure 33 Timer Output Waveform
50
HD404054 Series/HD404094 Series
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.
Timer mode register C1 (TMC1: $00D)
Timer mode register C2 (TMC2: $014)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 34.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C1 (TMC1: $00D)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
TMC13
W
W
W
W
TMC13
TMC12
TMC11
TMC10
Free-running/reload timer selection
0
Free-running timer
1
Reload timer
Input clock period
TMC12
TMC11
TMC10
0
0
0
2048tcyc
1
1024tcyc
0
512tcyc
1
128tcyc
0
32tcyc
1
8tcyc
0
4tcyc
1
2tcyc
1
1
0
1
Figure 34 Timer Mode Register C1 (TMC1)
51
HD404054 Series/HD404094 Series
• Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 35. It is reset to $0 by MCU reset.
Timer mode register C2 (TMC2: $014)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
R/W
R/W
R/W
Not used TMC22
TMC21
TMC20
TMC22
TMC21
TMC20
0
0
0
R31
R31 port
1
TOC
Toggle output
0
TOC
0 output
1
TOC
1 output
0
—
Inhibited
TOC
PWM output
Bit name
1
1
0
R31/TOC mode selection
1
0
1
1
Figure 35 Timer Mode Register C2 (TMC2)
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and an upper digit (TWCU) as shown in figures 36 and 37. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.
Timer C is initialized by writing to timer write register C (TWCL: $00E, TWCU: $00F). In this case,
the lower digit (TWCL) must be written to first, but writing only to the lower digit does not change the
timer C value. Timer C is initialized to the value in timer write register C at the same time the upper
digit (TWCU) is written to. When timer write register C is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer C.
Timer write register C (lower digit) (TWCL: $00E)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TWCL3
TWCL2
TWCL1
TWCL0
Bit name
Figure 36 Timer Write Register C Lower Digit (TWCL)
52
HD404054 Series/HD404094 Series
Timer write register C (upper digit) (TWCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWCU3
TWCU2
TWCU1
TWCU0
Figure 37 Timer Write Register C Upper Digit (TWCU)
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures
38 and 39. The upper digit (TRCU) must be read first. At this time, the count of the timer C upper digit
is obtained, and the count of the timer C lower digit is latched to the lower digit (TRCL). After this, by
reading TRCL, the count of timer C when TRCU is read can be obtained.
Timer read register C (lower digit) (TRCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCL3
TRCL2
TRCL1
TRCL0
Figure 38 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRCU3
TRCU2
TRCU1
TRCU0
Figure 39 Timer Read Register C Upper Digit (TRCU)
53
HD404054 Series/HD404094 Series
Timer D
Timer D Functions: Timer D has the following functions.
•
•
•
•
Free-running/reload timer
External event counter
Timer output operation (toggle, 0, 1, and PWM outputs)
Input capture timer
The block diagram for each operation mode of timer D is shown in figures 40-1 and 40-2.
Timer D Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).
Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port
mode register C (PMRC: $025).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t cyc or longer.
Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.
• Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).
Toggle
0 output
1 output
PWM output
By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by
MCU reset.
 Toggle output: The operation is basically the same as that of timer-C’s toggle output.
 0 output: The operation is basically the same as that of timer-C’s 0 output.
 1 output: The operation is basically the same as that of timer-C’s 1 output.
54
HD404054 Series/HD404094 Series
 PWM output: The operation is basically the same as that of timer-C’s PWM output.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.
By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00.
55
HD404054 Series/HD404094 Series
Timer D interrupt
request flag (IFTD)
Timer output
control logic
TOD
Timer read
register DU (TRDU)
Timer output
control
Timer read
register DL
(TRDL)
Clock
Timer write
register DU
(TWDU)
System
clock
øPER
÷2048
Edge
detection
logic
÷2
÷4
÷8
÷32
÷128
÷512
Selector
EVND
Overflow
Free-running/
reload control
Timer write
register DL
(TWDL)
3
Prescaler S (PSS)
Timer mode
register D1
(TMD1)
3
Timer mode
register D2
(TMD2)
Edge detection control
2
Edge detection
selection register
2 (ESR2)
Figure 40-1 Block Diagram of Timer D (Free-Running/Reload Timer)
56
Internal data bus
Timer counter D
(TCD)
HD404054 Series/HD404094 Series
Input capture
status flag (ICSF)
Input capture
error flag (ICEF)
Timer D interrupt
request flag (IFTD)
Error
control
logic
Timer read
register DU
(TRDU)
Timer read
register DL
(TRDL)
EVND
Edge
detection
logic
Read signal
Clock
Timer counter D
(TCD)
Overflow
Selector
÷2
÷4
÷8
÷32
÷128
÷512
÷2048
3
System
clock
Timer mode
register D1
(TMD1)
Internal data bus
Input capture
timer control
øPER
Prescaler S (PSS)
Timer mode
register D2
(TMD2)
Edge detection control
2
Edge detection
selection register
2 (ESR2)
Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode)
57
HD404054 Series/HD404094 Series
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.
Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)
• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 41.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register D1 (TMD1: $010)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMD13
TMD12
TMD11
TMD10
Bit name
TMD13
Free-running/reload
timer selection
TMD12
TMD11
TMD10
0
Free-running timer
0
0
0
2048tcyc
1
Reload timer
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
R40/EVND (external event input)
1
1
0
1
Input clock period and
input clock source
Figure 41 Timer Mode Register D1 (TMD1)
58
HD404054 Series/HD404094 Series
• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 42. It is reset to $0 by MCU reset.
Timer mode register D2 (TMD2: $015)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
R/W
R/W
R/W
R/W
TMD23
TMD22
TMD21
TMD20
TMD23
TMD22
TMD21
TMD20
0
0
0
0
R32
R32 port
1
TOD
Toggle output
0
TOD
0 output
1
TOD
1 output
0
—
Inhibited
1
TOD
PWM output
×
R32
Input capture (R32 port)
1
1
0
R32/TOD mode selection
1
0
1
1
×
×
× : Don’t care
Figure 42 Timer Mode Register D2 (TMD2)
• Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and an upper digit (TWDU) as shown in figures 43 and 44. The operation of timer write
register D is basically the same as that of timer write register C (TWCL: $00E, TWCU: $00F).
Timer write register D (lower digit) (TWDL: $011)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TWDL3
TWDL2
TWDL1
TWDL0
Bit name
Figure 43 Timer Write Register D Lower Digit (TWDL)
59
HD404054 Series/HD404094 Series
Timer write register D (upper digit) (TWDU: $012)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
W
W
W
W
TWDU3
TWDU2
TWDU1
TWDU0
Figure 44 Timer Write Register D Upper Digit (TWDU)
• Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and an upper digit (TRDU) as shown in figures 45 and 46. The operation of timer read register
D is basically the same as that of timer read register C (TRCL: $00E, TRCU: $00F).
When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.
Timer read register D (lower digit) (TRDL: $011)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRDL3
TRDL2
TRDL1
TRDL0
Figure 45 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012)
Bit
Initial value
Read/Write
Bit name
3
2
1
0
Undefined Undefined Undefined Undefined
R
R
R
R
TRDU3
TRDU2
TRDU1
TRDU0
Figure 46 Timer Read Register D Upper Digit (TRDU)
60
HD404054 Series/HD404094 Series
• Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown
in figure 47. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
0
—
Read/Write
W
W
W
—
Bit name
PMRC3
PMRC2 PMRC1 Not used
PMRC1
R40/EVND mode selection
0
R40
1
EVND
PMRC2
D12/STOPC mode selection
0
D12
1
STOPC
PMRC3
D13/INT0 mode selection
0
D13
1
INT0
Figure 47 Port Mode Register C (PMRC)
• Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 48. It is reset to $0 by MCU reset.
Detection edge register 2 (ESR2: $027)
Bit
3
2
1
0
Initial value
0
0
—
—
W
—
—
Read/Write
W
Bit name
ESR23
ESR22 Not used Not used
EVND detection edge
ESR23
ESR22
0
0
No detection
1
Falling-edge detection
0
Rising-edge detection
1
Double-edge detection *
1
Note: * Both falling and rising edges are detected.
Figure 48 Detection Edge Select Register 2 (ESR2)
61
HD404054 Series/HD404094 Series
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 24. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 24
PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Write Register is Updated during
High PWM Output
Timer write
register
updated to
value N
Free running
Timer Write Register is Updated during
Low PWM Output
Timer write
register
updated to
value N
Interrupt
request
T × (255 – N) T × (N + 1)
Interrupt
request
T × (N' + 1)
T × (255 – N)
Reload
Timer write
register
updated to
value N
T
Interrupt
request
T × (255 – N)
T
Timer write
register
updated to
value N
Interrupt
request
T
T × (255 – N)
62
T × (N + 1)
T
HD404054 Series/HD404094 Series
Serial Interface 1
The MCU has one channel of serial interface. The serial interface serially transfers or receives 8-bit data,
and includes the following features.
• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock
• Output level control in idle states
Serial interface 1
•
•
•
•
•
•
•
Serial data register 1 (SR1L: $006, SR1U: $007)
Serial mode register 1A (SM1A: $005)
Serial mode register 1B (SM1B: $028)
Port mode register A (PMRA: $004)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector
The block diagram of serial interface 1 is shown in figure 49.
63
HD404054 Series/HD404094 Series
Serial interrupt
request flag
(IFS1)
Octal counter
(OC)
Idle control
logic
SO1
Serial data
register
(SR1L/U)
I/O control
logic
SCK1
Transfer
control
1/2
÷2
÷8
÷32
÷128
÷512
÷2048
Selector
System
clock
øPER
1/2
Selector
SI1
3
Serial mode register
1A (SM1A)
Prescaler S (PSS)
Serial mode register
1B (SM1B)
Figure 49 Block Diagram of Serial Interface 1
64
Internal data bus
Clock
HD404054 Series/HD404094 Series
Serial Interface Operation
Selecting and Changing the Operating Mode: Table 25 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial
mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always
initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface
1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for
Serial Interface for details.
Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005).
Pins R42/SI 1 and R4 3/SO 1 are controlled by writing data to port mode register A (PMRA: $004). Refer to
the following section Registers for Serial Interface for details.
Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following
section Registers for Serial Interface for details.
Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data
register 1. The serial data is shifted by the transmit clock and is input from or output to an external system.
The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000
by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When
the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal
counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 is set, and
the transfer stops.
When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock
frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A
(SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 26.
Table 25
Serial Interface 1 Operating Modes
SM1A
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
65
HD404054 Series/HD404094 Series
Table 26
Serial Transmit Clock (prescaler output)
SM1B
SM1A
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Tranamit Clock Frequency
0
0
0
0
÷ 2048
4096t cyc
1
÷ 512
1024t cyc
0
÷ 128
256t cyc
1
÷ 32
64t cyc
0
÷8
16t cyc
1
÷2
4t cyc
0
÷ 4096
8192t cyc
1
÷ 1024
2048t cyc
0
÷ 256
512t cyc
1
÷ 64
128t cyc
0
÷ 16
32t cyc
1
÷4
8t cyc
1
1
1
0
0
0
1
1
0
Operating States: Serial interface 1 has the following operating states; transitions between them are
shown in figure 50.




STS wait state
Transmit clock wait state
Transfer state
Continuous transmit clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface
in transfer state. However, note that if continuous clock output mode is selected in internal clock mode,
the serial interface does not enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
66
HD404054 Series/HD404094 Series
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK 1 pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SM1A write 04
01 STS instruction
00 MCU reset
06 SM1A write (IFS1 ← 1)
02 Transmit clock
Transfer state
(Octal counter ≠ 000)
Transmit clock wait state
(Octal counter = 000)
03
8 transmit clocks
05
STS instruction (IFS1 ← 1)
Internal clock mode
SM1A write
18
Continuous transmit
clock output state
(PMRA 0, 1 = 0, 0)
SM1A write 14
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
13 8 transmit clocks
11 STS instruction
16 SM1A write (IFS1← 1)
Transmit clock 17
12 Transmit clock
Transfer state
(Octal counter ≠ 000)
Transmit clock wait state
(Octal counter = 000)
15
STS instruction (IFS1 ← 1)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 50 Serial Interface State Transitions
Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output
of serial output pin, SO1 can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B:
$028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the
output level cannot be controlled in transfer state.
67
,
HD404054 Series/HD404094 Series
Transmit clock
wait state
State
STS wait state
Transmit clock
wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
External clock selection
SM1A write
Output level control in
idle states
Dummy write for
state transition
Output level control in
idle states
SM1B write
Data write for transmission
SR1L, SR1U
write
STS instruction
SCK1 pin (input)
SO1 pin
Undefined
LSB
MSB
IFS1
External clock mode
Flag reset at transfer completion
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
Internal clock selection
SM1A write
Output level control in
idle states
SM1B write
Output level control in
idle states
Data write for transmission
SR1L, SR1U
write
STS instruction
SCK1 pin (output)
SO1 pin
Undefined
LSB
MSB
IFS1
Internal clock mode
Flag reset at transfer completion
Figure 51 Example of Serial Interface 1 Operation Sequence
68
HD404054 Series/HD404094 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 52.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005)
changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the
serial 1 interrupt request flag is set again, and therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register 1A (SM1A: $005) again.
• Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from
transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS
instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set.
To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution
must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing
the input instruction to port R4.
69
HD404054 Series/HD404094 Series
Transfer completion
(IFS1 ← 1)
Interrupts inhibited
IFS1 ← 0
SM1A write
Yes
IFS1 = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transmit clock wait state
Transfer state
State
SCK 1 pin
(input)
Transfer state
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SM1A is written,
IFS1 is set.
SM1A
write
IFS1
Flag set because octal
counter reaches 000.
Transmit clock error detection procedures
Figure 52 Transmit Clock Error Detection
70
Flag reset at
transfer completion.
HD404054 Series/HD404094 Series
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
•
•
•
•
•
Serial mode register 1A (SM1A: $005)
Serial mode register 1B (SM1B: $028)
Serial data register 1 (SR1L: $006, SR1U: $007)
Port mode register A (PMRA: $004)
Miscellaneous register (MIS: $00C)
Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 53).
•
•
•
•
R4 1/SCK 1 pin function selection
Serial interface 1 transmit clock selection
Serial interface 1 prescaler division ratio selection
Serial interface 1 initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock
to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to
000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
71
HD404054 Series/HD404094 Series
Serial mode register 1A (SM1A: $005)
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
SM1A3
SM1A2
SM1A1
SM1A0
Bit name
SM1A3
R41/SCK1
mode selection
0
R41
1
SCK1
Prescaler
division ratio
SM1A2
SM1A1
SM1A0
SCK1
Clock source
0
0
0
Output
Prescaler
Refer to
table 26
0
Output
System clock
—
1
Input
External clock
—
1
1
0
1
1
0
0
1
1
Figure 53 Serial Mode Register 1A (SM1A)
Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 54).
• Serial interface 1 prescaler division ratio selection
• Serial interface 1 output level control in idle states
Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data
transfer.
By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit
0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is
controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is
written to.
72
HD404054 Series/HD404094 Series
Serial mode register 1B (SM1B: $028)
Bit
3
2
1
0
Initial value
—
—
Undefined
0
Read/Write
—
—
W
W
Bit name
Not used Not used SM1B1
SM1B1
Output level control in idle states
SM1B0
SM1B0
Serial clock division ratio
0
Low level
0
Prescaler output divided by 2
1
High level
1
Prescaler output divided by 4
Figure 54 Serial Mode Register 1B (SM1B)
Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 55
and 56)
• Serial interface 1 transmission data write and shift
• Serial interface 1 receive data shift and read
Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of
the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 57.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register 1(lower digit) (SR1L: $006)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR13
SR12
SR11
SR10
Figure 55 Serial Data Register 1 (SR1L)
Serial data register 1(upper digit) (SR1U: $007)
Bit
3
Initial value
2
1
0
Undefined Undefined Undefined Undefined
Read/Write
R/W
R/W
R/W
R/W
Bit name
SR17
SR16
SR15
SR14
Figure 56 Serial Data Register 1 (SR1U)
73
HD404054 Series/HD404094 Series
Transmit clock
1
Serial output
data
2
3
4
5
6
LSB
7
8
MSB
Serial input data
latch timing
Figure 57 Serial Interface Output Timing
Port Mode Register A (PMRA: $004): This register has the following functions (figure 58).
• R4 2/SI 1 pin function selection
• R4 3/SO 1 pin function selection
Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
Not used Not used PMRA1 PMRA0
PMRA0
R43/SO1 mode selection
0
R43
1
SO1
PMRA1
R42/SI1 mode selection
0
R42
1
SI1
Figure 58 Port Mode Register A (PMRA)
74
HD404054 Series/HD404094 Series
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 59).
• R4 3/SO 1 pin PMOS control
Miscellaneous register (MIS: $00C) is a 2-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
—
—
Read/Write
W
W
—
—
MIS3
MIS2
Bit name
Not used Not used
MIS2
R43/SO1 PMOS on/off selection
0
On
1
Off
MIS3
Pull-up MOS on/off selection
0
Off
1
On
Figure 59 Miscellaneous Register (MIS)
75
HD404054 Series/HD404094 Series
Comparator
The block diagram of the comparator is shown in figure 60. The comparator compares input voltage with
the reference voltage.
COMP0
COMP1
Selector
Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison.
When an input voltage at COMP0, COMP1 is higher than the reference voltage, the TM or TMD command
sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to
COMP 0 and COMP1. On the other hand, when an input voltage at COMP0, COMP1 is lower, the TM or
TMD command clears the ST to 0.
+
Comparator
Comparator data
register (CDR)
Internal data bus
–
VCref
Comparator enable
register (CER)
Figure 60 Block Diagram of Comparator
76
HD404054 Series/HD404094 Series
Compare Enable Register (CER: $018): Three-bit write-only register which enables comparator
operation, and selects the reference voltage and the analog input pin (figure 61).
Compare enable register (CER: $018)
Bit
3
2
Initial value
0
—
0
0
Read/Write
W
—
W
W
Bit name
CER3
0
1
CER3
1
Not used CER1
Digital/Analog selection
0
CER0
CER1
CER0
0
0
COMP0
1
COMP1
0
Not used
1
Not used
Digital input mode:
RD0 /COMP0, RD1 /COMP1
operate as R port
1
Analog input mode:
RD0 /COMP0, RD1 /COMP1
operate as analog input
Analog input pin selection
Figure 61 Compare Enable Register
Compare Data Register (CDR: $017): Two-bit read-only register which latches the result of the
comparison between the analog input pins and the reference voltage. Bits 0 and 1 corresponds the results
of comparison with COMP0 and COMP1, respectively. This register can be read only by the TM or TMD
command. Only bit CER3 corresponds to the analog input pin which the input pin selection is made
through pins CER0 and CER1. After a compare operation, the data in this register is not retained (figure
62).
Compare data register (CDR: $017)
Bit
3
2
Initial value
—
—
Read/Write
—
—
Bit name
Not used Not used
1
0
Undefined Undefined
R
R
CDR1
CDR0
Result of COMP0 comparison
Result of COMP1 comparison
Figure 62 Compare Data Register
Note on Use: During the compare operation pins RD0/COMP0 and RD1/COMP1 operate as analog inputs
and cannot operate as R ports.
The comparator can operate in active mode but is disabled in other modes.
RE0/VC ref cannot operate as an R port when the external input voltage is selected as the reference.
77
HD404054 Series/HD404094 Series
Programmable ROM (HD4074054, HD4074094)
The HD4074054 and HD4074094 are ZTAT microcomputers with built-in PROM that can be
programmed in PROM mode.
PROM Mode Pin Description
Pin No.
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin Name
I/O
Pin Name
I/O
1
39
RD0/COMP0
I
CE
I
2
40
RD1/COMP1
I
OE
I
3
41
RD2
I
4
42
RD3
I
5
43
RC0
I
6
1
RE 0/VCref
I
M1
I
7
2
TEST
I
TEST
I
8
3
OSC 1
I
VCC
9
4
OSC 2
O
10
5
RESET
I
RESET
11
6
GND
I
GND
12
7
D0
I/O
O
13
8
D1
I/O
O
14
9
D2
I/O
VCC
15
10
D3
I/O
VCC
16
11
D4
I/O*
O4
I/O
17
12
D5
I/O*
O5
I/O
18
13
D6
I/O*
O6
I/O
19
14
D7
I/O*
O7
I/O
20
15
D8
I/O
A13
I
21
16
D9
I/O
A14
I
22
17
D12/STOPC
I
A9
I
23
18
D13/INT0
I
VPP
24
19
R0 0/INT1
I/O
M0
I
25
20
R1 0
I/O
A5
I
26
21
R1 1
I/O
A6
I
27
23
R1 2
I/O
A7
I
Note: I/O: Input/output pin, I: Input pin, O: Output pin
* HD404054 Series: I/O, HD404094 Series: O
78
I
HD404054 Series/HD404094 Series
Pin No.
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin Name
I/O
Pin Name
I/O
28
24
R1 3
I/O
A8
I
29
25
R2 0
I/O
A0
I
30
26
R2 1
I/O
A10
I
31
27
R2 2
I/O
A11
I
32
28
R2 3
I/O
A12
I
33
29
R3 0
I/O
A1
I
34
30
R3 1/TOC
I/O
A2
I
35
31
R3 2/TOD
I/O
A3
I
36
32
R3 3
I/O
A4
I
37
33
R4 0/EVND
I/O
O0
I/O
38
34
R4 1/SCK 1
I/O
O1
I/O
39
35
R4 2/SI1
I/O
O2
I/O
40
36
R4 3/SO 1
I/O
O3
I/O
41
37
SEL
I
42
38
VCC
I
–
22
NC
–
–
44
NC
–
VCC
Note: I/O: Input/output pin, I: Input pin, O: Output pin
79
HD404054 Series/HD404094 Series
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and
M1 low, and RESET low as shown in figure 63. In PROM mode, the MCU does not operate, but it can be
programmed in the same way as any other commercial 27256-type EPROM using a standard PROM
programmer and an 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters
of the HD4074054 and HD4074094 are listed in table 27.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that
if, for example, 4-kwords of built-in PROM are to be programmed by a general-purpose PROM
programmer, a 8-kbyte address space ($0000–$7FFF) must be specified.
VCC
VCC
RESET
TEST
M0
VPP
M1
O0 to O7
Data
O0 to O7
A0 to A14
Address
A0 to A14
VPP
HD4074054
HD4074094
VCC
OSC1
D2
D3
OE
OE
CE
CE
GND
Figure 63 PROM Mode Connections
Table 27
Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacturer
Model Name
Package
Model Name
Manufacturer
DATA I/O Corp.
121B
DP-42S
HS4654ESS01H
Hitachi
AVAL Corp.
PKW-1000
FP-44A
HS4654ESH01H
Hitachi
80
HD404054 Series/HD404094 Series
Warnings
1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address
$2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased or reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 28.
Table 28
PROM Mode Selection
Pin
Mode
CE
OE
VPP
O0–O7
Programming
Low
High
VPP
Data input
Verification
High
Low
VPP
Data output
Programming inhibited
High
High
VPP
High impedance
81
HD404054 Series/HD404094 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 64 and described below.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register direct addressing
1st word of Instruction
2nd word of Instruction
Opcode
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct addressing
Instruction
Opcode
0
RAM address
0
0
1
m3 m2
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory register addressing
Figure 64 RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.
82
HD404054 Series/HD404094 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 65 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC 13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 67. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC 5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 66. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
83
HD404054 Series/HD404094 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct addressing
Instruction
[BR]
Program counter
Opcode
b6
b7
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current page addressing
Instruction
[CAL]
0
Program counter
0
0
0
d5
Opcode
0
0
0
d4
d3
d2
d1
d0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero page addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
Program counter
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table data addressing
Figure 65 ROM Addressing Modes
84
B2 B1
Accumulator
HD404054 Series/HD404094 Series
Instruction
[P]
Opcode
p3
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
If RO 9 = 1
Pattern output
Figure 66 P Instruction
85
HD404054 Series/HD404094 Series
256 (n – 1) + 255
BR
AAA
256n
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
NOP
BR
BR
BBB
AAA
NOP
Figure 67 Branching when the Branch Destination is on a Page Boundary
86
HD404054 Series/HD404094 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
Pin voltage
VT
–0.3 to VCC + 0.3 V
Notes
1
–0.3 to +15.0
V
2
Total permissible input current
∑Io
80
mA
3
Total permissible output current
–∑Io
50
mA
4
Maximum input current
Io
4
mA
5, 6
30
mA
5, 7
4
mA
8, 9
20
mA
8, 10
Maximum output current
–I o
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to D 13 (VPP) of HD4074054 and HD4074094.
2. Applies to D 4 to D7 of HD404092, HD404094, and HD4074094.
3. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
4. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
5. The maximum input current is the maximum current flowing from each I/O pin to GND.
6. Applies to D 0–D 3, and R0–R4.
7. Applies to D 4–D 9 .
8. The maximum output current is the maximum current flowing out from V CC to each I/O pin.
9. Applies to D 4–D 9 and R0–R4.
10. Applies to D 0–D 3.
87
HD404054 Series/HD404094 Series
Electrical Characteristics
DC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V,
T a = –20 °C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = –20°C to
+75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pin(s)
Input high
voltage
VIH
RESET, STOPC, 0.9 VCC
INT0, INT1, SCK 1,
SI 1, EVND
OSC 1
Input low
voltage
VIL
Min
Typ
Max
Unit
—
VCC + 0.3 V
VCC – 0.3 —
VCC + 0.3 V
Test Condition
Notes
External clock
RESET, STOPC, –0.3
INT0, INT1, SCK 1,
SI 1, EVND
—
0.10 VCC V
OSC 1
–0.3
—
0.3
V
External clock
Output high
voltage
VOH
SCK 1, SO1,
TOC,TOD
VCC – 1.0 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
SCK 1, SO1,
TOC,TOD
—
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
| IIL |
RESET, STOPC, —
INT0, INT1, SCK 1,
SI 1, SO1, EVND,
OSC 1, TOC, TOD
—
1
µA
Vin = 0 V to VCC
1
Current
dissipation in
active mode
I CC1
VCC
—
5
—
mA
VCC = 5 V,
f OSC = 4 MHz
Digital input mode
2, 4,
—
5
10
mA
VCC = 5 V,
f OSC = 8 MHz
Digital input mode
3, 4,
2, 4,
I CC2
VCC
—
0.6
1.8
mA
VCC = 3 V,
f OSC = 800 kHz
Digital input mode
I CMP1
VCC
—
9
—
mA
VCC = 5 V,
2, 4,
f OSC = 4 MHz
Analog comp. mode
—
9
15
mA
VCC = 5 V,
3, 4,
f OSC = 8 MHz
Analog comp. mode
—
3.1
4.3
mA
VCC = 3 V,
2, 4,
f OSC = 800 kHz
Analog comp. mode
I CMP2
88
VCC
HD404054 Series/HD404094 Series
Item
Symbol Pin(s)
Current dissipation I SBY1
in standby mode
VCC
Min
Typ
Max
Unit
Test Condition
Notes
—
1.2
—
mA
VCC = 5 V,
f OSC = 4 MHz
2, 6,
—
3
6
mA
VCC = 5 V,
f OSC = 8 MHz
3, 6,
I SBY2
VCC
—
0.2
0.7
mA
VCC = 3 V,
f OSC = 800 kHz
2, 6,
Current dissipation I STOP
in stop mode
VCC
—
1
5
µA
VCC = 3 V
2, 7
—
1
10
µA
VCC = 5 V
3, 7
V
Stop mode
retaining voltage
VSTOP
VCC
—
1.3
—
Comparator input
reference voltage
scope
VC ref
VC ref
0
—
VCC – 1.2 V
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
8
Output buffer current is excluded.
Applies to HD404052, HD404054, HD4074054, HD404092, HD404094 and HD4074094.
Applies to HD40A4052 and HD40A4054.
I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset
state. Test conditions: MCU: Reset
Pins: RESET at GND (0 V to 0.3V)
TEST at V CC (VCC – 0.3 to VCC)
RD0 and RD1 pins are analog input mode when no I/O current is flowing.
Test conditions: MCU: Analog input mode
Pins: RD0/COMP0 at GND (0 V to 0.3 V)
RD1/COMP1 at GND (0 V to 0.3 V)
RE 0/VCref at GND (0 V to 0.3 V)
I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is
operating. Test conditions: MCU: I/O reset
Serial interface stopped
Standby mode
Pins: RESET at V CC (VCC – 0.3 to VCC)
TEST at V CC (VCC – 0.3 to VCC)
These are the source currents when no I/O current is flowing.
Test conditions: Pins: RESET at V CC (VCC – 0.3 to VCC)
TEST at V CC (VCC – 0.3 to VCC)
D13* at VCC (VCC – 0.3 to VCC)
Note: * Applies to HD4074054 and HD4074094
RAM data retention.
89
HD404054 Series/HD404094 Series
I/O Characteristics for Standard Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to
6.0 V, GND = 0 V, T a = –20°C to +75°C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V,
T a = –20°C to +75°C; HD4074054, HD4074094: V CC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to
+75°C, unless otherwise specified)
Item
Symbol Pin(s)
Input high
voltage
VIH
Input low
voltage
Typ
Max
D12–D 13 ,
0.7 VCC
R0–RD, RE0
—
VCC + 0.3 V
VIL
D12–D 13 ,
–0.3
R0–RD, RE0
—
0.3 VCC
V
Output high
voltage
VOH
R0–R4
VCC – 1.0 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
R0–R4
—
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
| IIL |
D12, R0–RD, —
RE 0
—
1
µA
Vin = 0 V to VCC
1
D13
—
—
1
µA
Vin = 0 V to VCC
1, 2,
4
—
—
1
µA
Vin = VCC – 0.3 V to VCC 1, 3
—
—
20
µA
Vin = 0 V to 0.3 V
1, 3
—
30
—
µA
VCC = 3 V,
Vin = 0 V
2, 3
20
100
500
µA
VCC = 5 V,
Vin = 0 V
4
Pull-up MOS –I PU
current
R0–R4
Min
Unit
Test Condition
Notes
Input high
voltage
VIHA
COMP0,
COMP1
—
VC ref+0.0 —
5
V
Analog compare
mode
5
Input low
voltage
VILA
COMP0,
COMP1
—
VC ref–0.05 —
V
Analog compare
mode
5
Notes: 1.
2.
3.
4.
5.
90
Output buffer current is excluded.
Applies to HD404052, HD404054, HD404092, HD404094.
Applies to HD4074054, HD4074094.
Applies to HD40A4052, HD40A4054.
The analog input reference voltage should be in the range 0 ≤ VC ref ≤ VCC–1.2.
HD404054 Series/HD404094 Series
I/O Characteristics for High-Current Pins and Intermediate-Voltage Pins (HD404052, HD404054,
HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD40A4052,
HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074054, HD4074094: VCC =
2.7 V to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified)
Pin(s)
Item
Symbol
HD404054 HD404094
Series
Series
Min
Typ
Max
Unit
Input high
voltage
VIH
D0–D 9
D0–D 3,
D8, D9
0.7 VCC
—
VCC + 0.3
V
Input low
voltage
VIL
D0–D 9
D0–D 3,
D8, D9
–0.3
—
0.3 VCC
V
Output high
voltage
VOH
D0–D 9
D0–D 3,
D8, D9
VCC – 1.0 —
—
V
–I OH = 0.5 mA
D0–D 3
D0–D 3
2.0
—
—
V
–I OH = 10 mA,
VCC = 4.5 V to
6.0 V
—
D4–D 7
11.5
—
—
V
500 kΩ at 12 V
D0–D 9
D0–D 9
—
—
0.4
V
I OL = 0.4 mA
D4–D 9
D4–D 9
—
—
2.0
V
I OL = 15 mA,
VCC = 4.5 V to
6.0 V
D0–D 9
D0–D 3,
D8, D9
—
—
1
µA
Vin = 0 V to VCC 1
—
D4–D 7
—
—
20
µA
Vin = 0 V to
12 V
1
D0–D 3
D0–D 3
—
30
—
µA
VCC = 3 V,
Vin = 3 V
3
—
20
100
500
µA
VCC = 5 V,
Vin = 5 V
4
D8, D9
—
30
—
µA
VCC = 3 V,
Vin = 0 V
3
—
20
100
500
µA
VCC = 5 V,
Vin = 0 V
4
Output low
voltage
VOL
I/O leakage
current
| IIL |
Pull-down
I PD
MOS current
Pull-up MOS –I PU
current
Notes: 1.
2.
3.
4.
D4–D 9
Test
Condition
Notes
2
2
Output buffer current is excluded.
When using HD4074054, HD4074094, VCC = 4.5 V to 5.5 V.
Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094.
Applies to HD40A4052, HD40A4054.
91
HD404054 Series/HD404094 Series
AC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V,
T a = –20 °C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, T a = –20°C to
+75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless
otherwise specified)
Item
Symbol Pin(s)
Clock oscillation
frequency
f OSC
Instruction cycle time
Oscillation stabilization
time (ceramic)
OSC 1,
OSC 2
t cyc
t RC
OSC 1,
OSC 2
Min
Typ
Max
Unit
Test Condition
Notes
0.4
—
4
MHz
1
0.4
—
8.5
MHz
2
—
8
—
µs
f OSC = 4 MHz, ÷32
1, 4
—
3.76
—
µs
f OSC = 8.5 MHz, ÷32
2, 4
—
1
—
µs
f OSC = 4 MHz, ÷4
1, 3
—
0.47
—
µs
f OSC = 8.5 MHz, ÷4
2, 3
—
—
7.5
ms
VCC = 2.7 V to 5.5 V:
3, 4
HD4074054, HD4074094
VCC = 2.7 V to 6.0 V:
HD404052, HD404054,
HD404092, HD404094
External clock high
width
t CPH
External clock low width t CPL
External clock rise time t CPr
External clock fall time
t CPf
OSC 1
OSC 1
OSC 1
OSC 1
—
—
60
ms
VCC = 1.8 V to 2.7 V:
HD404052, HD404054,
HD404092, HD404094
—
—
7.5
ms
VCC = 4.0 V to 6.0 V:
5, 6
HD40A4052,HD40A4054
105
—
—
ns
1, 7
49
—
—
ns
2, 7
105
—
—
ns
1, 7
49
—
—
ns
2, 7
—
—
20
ns
1, 7
—
—
10
ns
2, 7
—
—
20
ns
1, 7
—
—
10
ns
2, 7
INT0, INT1, EVND high
width
t IH
INT0, INT1, 2
EVND
—
—
t cyc
8
INT0, INT1, EVND low
width
t IL
INT0, INT1, 2
EVND
—
—
t cyc
8
RESET low width
t RSTL
RESET
2
—
—
t cyc
9
STOPC low width
t STPL
STOPC
1
—
—
t RC
10
RESET rise time
t RSTr
RESET
—
—
20
ms
9
STOPC rise time
t STPr
STOPC
—
—
20
ms
10
92
HD404054 Series/HD404094 Series
Item
Symbol Pin(s)
Input capacitance
Cin
Analog comparator t CSTB
stabilization time
Typ
Max
Unit
Test Condition
All pins except —
D13 D4–D 7
—
15
pF
f = 1 MHz, Vin = 0 V
D4–D 7
—
—
30
pF
f = 1 MHz, Vin = 0 V
D13
—
—
15
pF
f = 1 MHz, Vin = 0 V:
HD404052, HD404054,
HD404092, HD404094,
HD40A4052,HD40A4054
—
—
180
pF
f = 1 MHz, Vin = 0 V:
HD4074054, HD4074094
—
—
2
t cyc
VCC = 2.7 V to 5.5 V:
9
HD4074054, HD4074094
COMP0,
COMP1
Min
Notes
VCC = 2.7 V to 6.0 V:
HD404052, HD404054,
HD404092, HD404094
—
—
4
t cyc
VCC = 4.0 V to 6.0 V:
11
HD40A4052,HD40A4054
—
—
20
t cyc
VCC = 1.8 V to 2.7 V:
HD404052, HD404054,
HD404092, HD404094
Notes: 1.
2.
3.
4.
5.
Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094.
Applies to HD40A4052, HD40A4054.
SEL = 1
SEL = 0
The oscillation stabilization time is the period required for the oscillator to stabilize after V CC
reaches 2.7 (HD4074054, HD4074094)/1.8 (HD404052, HD404054, HD404092, HD404094) /4.0
(HD40A4052, HD40A4054)V at power-on, or after RESET input goes low or STOPC input goes
low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or
STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a
ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since
it will depend on the circuit constants and stray capacitance.
6. Applies to ceramic oscillator only.
7. Refer to figure 68.
8. Refer to figure 69.
9. Refer to figure 70.
10. Refer to figure 71.
11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for
correct data to be read after entering RD 0/COMP0, RD1/COMP1 into analog input mode.
93
HD404054 Series/HD404094 Series
Serial Interface Timing Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V
to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0
V, T a = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to
+75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Test Condition
Note
Transmit clock
cycle time
t Scyc
SCK 1
1
—
—
t cyc
Load shown in
figure 73
1
Transmit clock
high width
t SCKH
SCK 1
0.5
—
—
t Scyc
Load shown in
figure 73
1
Transmit clock
low width
t SCKL
SCK 1
0.5
—
—
t Scyc
Load shown in
figure 73
1
Transmit clock
rise time
t SCKr
SCK 1
—
100
—
ns
Load shown in
figure 73
1, 2
—
—
80
ns
—
100
—
ns
—
—
80
ns
—
—
500
ns
—
—
200
ns
1, 3
300
—
—
ns
1, 2
150
—
—
ns
1, 3
300
—
—
ns
1, 2
150
—
—
ns
1, 3
Transmit clock
fall time
Serial output
data delay time
t SCKf
t DSO
Serial input data t SSI
setup time
Serial input data t HSI
hold time
Note:
94
SCK 1
SO1
SI 1
SI 1
1, 3
Load shown in
figure 73
1, 2
1, 3
Load shown in
figure 73
1. Refer to figure 72.
2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094.
3. Applies to HD40A4052, HD40A4054.
1, 2
HD404054 Series/HD404094 Series
During Transmit Clock Input
Item
Symbol
Pin(s)
Min
Typ
Max
Unit
Transmit clock
cycle time
t Scyc
SCK 1
1
—
—
t cyc
1
Transmit clock
high width
t SCKH
SCK 1
0.5
—
—
t Scyc
1
Transmit clock
low width
t SCKL
SCK 1
0.5
—
—
t Scyc
1
Transmit clock
rise time
t SCKr
SCK 1
—
100
—
ns
1, 2
—
—
80
ns
1, 3
—
100
—
ns
1, 2
—
—
80
ns
1, 3
—
—
500
ns
—
—
200
ns
1, 3
300
—
—
ns
1, 2
150
—
—
ns
1, 3
300
—
—
ns
1, 2
150
—
—
ns
1, 3
Transmit clock
fall time
Serial output
data delay time
t SCKf
t DSO
Serial input data t SSI
setup time
Serial input data t HSI
hold time
Note:
SCK 1
SO1
SI 1
SI 1
Test Condition
Load shown in
figure 73
Note
1, 2
1. Refer to figure72.
2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094.
3. Applies to HD40A4052, HD40A4054.
95
HD404054 Series/HD404094 Series
OSC 1
1/fCP
VCC – 0.3 V
0.3 V
tCPL
tCPH
tCPr
tCPf
Figure 68 External Clock Timing
RESET
0.9 VCC
tRSTL
0.1 V CC
tRSTr
Figure 69 Interrupt Timing
INT0 , INT1, EVND
0.9 VCC
t IL
t IH
0.1 VCC
Figure 70 Reset Timing
STOPC
0.9 VCC
tSTPL
0.1 V CC
tSTPr
Figure 71 STOPC Timing
96
HD404054 Series/HD404094 Series
t Scyc
t SCKf
SCK 1
VCC – VH (0.9 VCC )*
0.4 V (0.1 VCC )*
t SCKr
t SCKL
t SCKH
t DSO
VCC – VH
0.4 V
SO 1
t HSI
t SSI
0.9 V CC
0.1 V CC
SI 1
Note: * VCC – VH and 0.4 V are the threshold voltages for transmit clock output.
VH = 1.0 V : HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094
VH = 2.0 V : HD40A4052, HD40A4054
0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock output.
Figure 72 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test point
C
30 pF
R
12 kΩ
1S2074 H
or equivalent
Figure 73 Timing Load Circuit
97
HD404054 Series/HD404094 Series
Notes On ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions
(HD404054, HD404094 and HD40A4054). A 4-kword data size is required to change ROM data to mask
manufacturing data since the program used is for a 4-kword version.
This limitation apply to the case of using EPROM and the case of using data base.
ROM 2 kwords version:
HD404052, HD404092, HD40A4052
Address $0800 to $0FFF
$0000
Vector address
$000F
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern and program
(2048 words)
$07FF
$0800
Not used
$0FFF
98
Fill this area with all 1s
HD404054 Series/HD404094 Series
HD40(A)4052/HD40(A)4054 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
/
/
Customer
Department
1. ROM size
Name
HD404052: 2-kword
HD40A4052: 2-kword
ROM code name
HD404054: 4-kword
HD40A4054: 4-kword
LSI number
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
3. Oscillator for OSC1 and OSC2
Ceramic oscillator
f=
MHz
Crystal oscillator
f=
MHz
External clock
f=
MHz
4. Stop mode
Used
Not used
5. Package
DP-42S
FP-44A
99
HD404054 Series/HD404094 Series
HD404092/HD404094 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
/
/
Customer
Department
1. ROM size
Name
HD404092: 2-kword
ROM code name
HD404094: 4-kword
LSI number
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
3. Oscillator for OSC1 and OSC2
Ceramic oscillator
f=
MHz
Crystal oscillator
f=
MHz
External clock
f=
MHz
4. Stop mode
Used
Not used
5. Package
DP-42S
FP-44A
100
HD404054 Series/HD404094 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
101