MOTOROLA MCM69R820CZP6 4m late write 2.5 v i/o Datasheet

Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc...
4M Late Write 2.5 V I/O
Order this document
by MCM69R738C/D
MCM69R738C
MCM69R820C
The MCM69R738C/820C is a 4M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R820C
(organized as 256K words by 18 bits) and the MCM69R738C (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is also driven on the rising edge of CK.
The RAM uses 2.5 V inputs and outputs.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
ZP PACKAGE
PBGA
CASE 999–02
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V +10%, –5% Operation
2.5 V I/O (VDDQ)
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69R738C/820C–4 = 4 ns
MCM69R738C/820C–4.4 = 4.4 ns
MCM69R738C/820C–5 = 5 ns
MCM69R738C/820C–6 = 6 ns
• Sleep Mode Operation (ZZ Pin)
• 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
REV 1
8/13/99

Motorola, Inc. 1999
MOTOROLA
FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
1
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
REGISTERS
SA
DATA IN
REGISTER
MEMORY
ARRAY
DQ
DATA OUT
REGISTER
SW
SW
REGISTERS
SBx
CONTROL
LOGIC
CK
Freescale Semiconductor, Inc...
G
SS
REGISTERS
SS
PIN ASSIGNMENTS
TOP VIEW
MCM69R738C
A
B
C
D
MCM69R820C
1
2
3
4
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
NC
DQc
NC
SA
DQc
SA
SA
VSS
NC
VDD
NC
SA
SA
VSS
NC
SA
DQb
NC
NC
DQb
E
DQc
VDDQ DQc
VSS
VSS
SS
G
VSS
VSS
DQb
K
DQb VDDQ
DQc
DQc
DQc
VDDQ VDD
DQd
DQd
SBc
VSS
NC
VSS
NC
NC
VDD
CK
SBb
VSS
NC
VSS
DQb
DQb
DQb
VDD VDDQ
DQa
DQa
DQd
DQd
T
U
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
NC
SA
NC
SA
NC
NC
NC
SA
SA
VDD
SA
SA
NC
DQb
NC
VSS
NC
VSS
DQa
NC
NC
DQb
VSS
SS
VSS
NC
DQa
VDDQ
NC
VSS
G
VSS
DQa VDDQ
H
NC
DQb
SBb
NC
VSS
NC
DQa
J
DQb
NC
VSS
NC
VSS
DQa
NC
K
VDDQ VDD
NC
VDD
NC
SBd
CK
SBa
DQa
DQa
VDD VDDQ
NC
DQb
VSS
CK
VSS
NC
DQa
DQb
NC
VSS
CK
SBa
DQa
NC
VDDQ DQb
VSS
SW
VSS
NC VDDQ
M
VDDQ DQd
R
4
L
M
P
F
DQb
L
N
D
3
G
DQc
J
C
DQb
G
H
B
2
E
DQc
F
A
1
DQd
DQd
NC
NC
DQd
DQd
SA
NC
VDDQ TMS
VSS
VSS
VSS
VSS
SA
TDI
SW
SA
SA
VDD
SA
TCK
MCM69R738C•MCM69R820C
2
VSS
VSS
VSS
VDD
SA
TDO
DQa VDDQ
DQa
DQa
SA
NC
DQa
DQa
NC
ZZ
NC VDDQ
N
P
R
DQb
NC
VSS
SA
VSS
DQa
NC
NC
DQb
VSS
SA
VSS
NC
DQa
NC
SA
VSS
VDD
VDD
SA
NC
NC
SA
SA
NC
SA
SA
ZZ
TDI
TCK
TDO
T
U
VDDQ TMS
For More Information On This Product,
Go to: www.freescale.com
NC VDDQ
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM69R738C PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
4K
CK
Input
Address, data in, and control input register clock. Active high.
4L
CK
Input
Address, data in, and control input register clock. Active low.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
I/O
4F
G
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,
4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge,
active low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
Input
Test Clock (JTAG).
3U
TDI
Input
Test Data In (JTAG).
5U
TDO
Output
2U
TMS
Input
Test Mode Select (JTAG).
7T
ZZ
Input
Enables sleep mode, active high.
Description
Synchronous Data I/O.
Test Data Out (JTAG).
4C, 2J, 4J, 6J, 4R, 5R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N, 3P, 5P, 3R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G,
4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U
NC
—
MOTOROLA FAST SRAM
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM69R820C PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
4K
CK
Input
Address, data in, and control input register clock. Active high.
4L
CK
Input
Address, data in, and control input register clock. Active low.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
Description
Synchronous Data I/O.
4F
G
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C,
4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
Input
Test Clock (JTAG).
Test Data In (JTAG).
3U
TDI
Input
5U
TDO
Output
2U
TMS
Input
Test Mode Select (JTAG).
7T
ZZ
Input
Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 2D, 4D,
7D, 1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H,
3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P,
6P, 1R, 7R, 1T, 4T, 6U
NC
—
MCM69R738C•MCM69R820C
4
Test Data Out (JTAG).
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note)
Rating
Symbol
Value
Unit
VDD
–0.5 to 4.6
V
VDDQ
–0.5 to VDD + 0.5
V
Voltage On Any Pin
Vin
–0.5 to VDD + 0.5
V
Input Current (per I/O)
Iin
±50
mA
Iout
±70
mA
Core Supply Voltage
Output Supply Voltage
Output Current (per I/O)
Operating Temperature
TA
0 to 70
°C
Temperature Under Bias
Tbias
–10 to 85
°C
Tstg
–55 to 125
°C
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
Freescale Semiconductor, Inc...
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Junction to Ambient (Still Air)
Symbol
Max
Unit
Notes
RθJA
53
°C/W
1, 2
1, 2
Junction to Ambient (@200 ft/min)
Single–Layer Board
RθJA
38
°C/W
Junction to Ambient (@200 ft/min)
Four–Layer Board
RθJA
22
°C/W
Junction to Board (Bottom)
RθJB
14
°C/W
3
Junction to Case (Top)
RθJC
5
°C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K
ZZ
SS
SW
SBa
SBb
SBc
SBd
DQ (n)
DQ (n + 1)
Mode
L–H
L
L
H
X
X
X
X
X
Dout 0 – 35
Read Cycle All Bytes
L–H
L
L
L
L
H
H
H
High–Z
Din 0 – 8
Write Cycle 1st Byte
L–H
L
L
L
H
L
H
H
High–Z
Din 9 – 17
Write Cycle 2nd Byte
L–H
L
L
L
H
H
L
H
High–Z
Din 18 – 26
Write Cycle 3rd Byte
L–H
L
L
L
H
H
H
L
High–Z
Din 27 – 35
Write Cycle 4th Byte
L–H
L
L
L
L
L
L
L
High–Z
Din 0 – 35
Write Cycle All Bytes
L–H
L
L
L
H
H
H
H
High–Z
High–Z
Abort Write Cycle
L–H
L
H
H
X
X
X
X
X
High–Z
Deselect Cycle
L–H
L
H
L
X
X
X
X
High–Z
High–Z
Deselect Cycle
X
H
X
X
X
X
X
X
High–Z
High–Z
Sleep Mode
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
5
Freescale Semiconductor, Inc.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Symbol
Min
Max
–4
Max
–4.4
Max
–5
Max
–6
Max
Unit
VDD
3.15
—
—
—
—
3.6
V
VDDQ
2.3
—
—
—
—
2.8
V
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max,
VDD = Max, VDDQ = Max).
Includes Supply Currents for VDD.
IDD1
—
795
775
750
750
—
mA
5
Quiescent Active Power Supply Current
(Device Selected, All Outputs Open,
Freq = 0, VDD = Max, VDDQ = Max).
Includes Supply Currents for VDD.
IDD2
—
540
540
540
540
—
mA
6
Active Standby Power Supply Current
(Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max)
ISB1
—
400
400
400
400
—
mA
7
CMOS Standby Supply Current
(Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs
Static at CMOS Levels)
ISB2
—
390
390
390
390
—
mA
6, 7
IZZ
—
100
100
100
100
—
mA
Parameter
Core Power Supply Voltage
Freescale Semiconductor, Inc...
Output Driver Supply Voltage
Sleep Mode Current (ZZ = VIH,
Freq = Max, VDD = Max, VDDQ = Max)
Notes
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS
bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. 50% read and 50% write; all addresses switching.
6. CMOS levels for I/Os are VIC ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
7. Device deselected as defined by the Clock Truth Table.
MCM69R738C•MCM69R820C
6
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
DC INPUT CHARACTERISTICS
Symbol
Min
Max
Unit
DC Input Logic High
Parameter
VIH (dc)
1.7
VDD + 0.3
V
DC Input Logic Low
VIL (dc)
–0.3
0.7
V
1
Input Leakage Current
Ilkg(1)
—
±5
µA
2
Clock Input Leakage Current
Iclkg(1)
—
±8
µA
2
Vin
–0.3
VDD + 0.3
V
Clock Input Differential Voltage
VDIF (dc)
0.2
VDD + 0.6
V
3
Clock Input Common Mode Voltage Range (See Figure 3)
VCM (dc)
1.1
2.1
V
4
Clock Input Signal Voltage
Notes
Freescale Semiconductor, Inc...
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. 0 V ≤ Vin ≤ VDD.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
DC OUTPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Ilkg(0)
–1
1
µA
Output Low Voltage
VOL
—
0.7
V
1
Output High Voltage
VOH
1.7
—
V
2
Output Leakage Current
Notes
NOTES:
1. IOL ≥ – 8 mA.
2. IOH ≥ 8 mA.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Typ
Max
Unit
Cin
4
5
pF
Input/Output Capacitance
CI/O
7
8
pF
CK, CK Capacitance
CCK
4
5
pF
Characteristic
Input Capacitance
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
7
Freescale Semiconductor, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
RθJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
READ/WRITE CYCLE TIMING
69R738C–4
69R820C–4
69R738C–4.4
69R820C–4.4
69R738C–5
69R820C–5
69R738C–6
69R820C–6
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tKHKH
4
—
4.4
—
5
—
6
—
ns
Clock High Pulse Width
tKHKL
1.5
—
1.5
—
2
—
2.4
—
ns
Parameter
Freescale Semiconductor, Inc...
Clock Low Pulse Width
Notes
tKLKH
1.5
—
1.5
—
2
—
2.4
—
ns
Clock High to Output Low–Z
tKHQX1
0.5
—
1
—
1
—
1
—
ns
Clock High to Output Valid
tKHQV
—
2
—
2.2
—
2.5
—
3
ns
Clock High to Output Hold
tKHQX
0.7
—
0.7
—
1
—
1
—
ns
1
Clock High to Output High–Z
tKHQZ
—
2
—
2.2
—
2.5
—
3
ns
1, 2
Output Enable Low to Output
Low–Z
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to Output
Valid
tGLQV
—
2
—
2.2
—
2.5
—
3
ns
Output Enable to Output Hold
tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output
High–Z
tGHQZ
—
2
—
2
—
2.5
—
3
ns
ZZ High to Sleep Mode
tZZE
—
50
—
50
—
50
—
50
ns
ZZ Low to Recovery
tZZR
200
—
200
—
200
—
200
—
ns
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
tKHAX
tKHDX
tKHSX
tKHWX
0.75
—
0.75
—
1
—
1
—
ns
1, 2
1, 2
NOTES:
1. This parameter is sampled and not 100% tested.
2. Measured at ±200 mV from steady state.
TIMING LIMITS
VDDQ/2
50 Ω
DEVICE
UNDER
TEST
50 Ω
The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
Figure 1. AC Test Load
MCM69R738C•MCM69R820C
8
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
VOH
VSS
50%
100%
20% tKHKH
Freescale Semiconductor, Inc...
Figure 2. Undershoot Voltage
VDDQ
VTR
CROSSING POINT
VDIF
VCP
VCM*
VSS
* VCM, the Common Mode Input Voltage, equals VTR – [(VTR – VCP)/2].
Figure 3. Differential Inputs/Common Mode Input Voltage
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
9
Freescale Semiconductor, Inc.
REGISTER/REGISTER READ–WRITE–READ CYCLES
t KHKH
t KHKL
CK
t AVKH
t KLKH
t KHAX
SA
A0
A1
t SVKH
A2
A3
A4
t KHSX
SS
t WVKH
t KHWX
Freescale Semiconductor, Inc...
SW
SBx
G
VIL
t KHQX1
t KHQZ
t KHQV
t KHDX
t KHQX
t KHQX
DQx
Q–1
MCM69R738C•MCM69R820C
10
Q0
Q1
t DVKH
D2
For More Information On This Product,
Go to: www.freescale.com
Q3
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
REGISTER/REGISTER READ–WRITE–READ
(G Controlled)
t KHKH
t KHKL
CK
t AVKH
t KLKH
t KHAX
SA
A0
A1
A2
A3
A4
SS
VIL
Freescale Semiconductor, Inc...
SW
SBx
G
t GLQV
t GLQX
t GHQZ
DQx
MOTOROLA FAST SRAM
Q–1
Q0
Q1
D2
For More Information On This Product,
Go to: www.freescale.com
t GHQX
Q3
MCM69R738C•MCM69R820C
11
tZZR
NO READS OR
WRITES ALLOWED
I ZZ
IN SLEEP MODE
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
NO NEW READS OR
WRITES ALLOWED
SLEEP MODE TIMING
tZZE
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
MCM69R738C•MCM69R820C
12
For More Information On This Product,
Go to: www.freescale.com
IDD
ZZ
DQ
G
SW
ADDR
CK
NORMAL OPERATION
Freescale Semiconductor, Inc...
NORMAL OPERATION
Freescale Semiconductor, Inc.
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
FUNCTIONAL OPERATION
Freescale Semiconductor, Inc...
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
the output register and available at the outputs at tKHQV.
During this same cycle a new read address can be applied to
the address pins.
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of CK clock has its effect on the
output drivers after the next rising edge of CK. SW low
deselects the output drivers immediately (on the same
cycle). Output selecting via a low on SS and high on SW at a
rising CK clock has its effect on the output drivers after the
next rising edge of CK. Output drive is also controlled directly
by output enable G. G is an asynchronous input. No clock
edges are required to enable/disable the output using G.
Output data will be valid the latter of tGLQV and tKHQV.
Outputs will begin driving at tKHQX1. Outputs will hold previous data until tKHQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW),
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active, is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
MOTOROLA FAST SRAM
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is recommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed
VDD + 0.5 V, whatever the instantaneous value of VDD. Once
supplies have reached specification levels, a minimum dwell
of 1.0 ms with CK clock inputs cycling is required before
beginning normal operations.
SLEEP MODE
This device is equipped with an optional sleep or low
power mode. The sleep mode pin is asynchronous and
active high. During normal operation, the ZZ pin is pulled low.
When ZZ is pulled high, the chip will enter sleep mode where
the device will meet the lowest possible power conditions.
The Sleep Mode Timing diagram shows the following modes
of operation: Normal Operation, No Read/Write Allowed, and
Sleep Mode.
Normal Operation
All inputs must meet setup and hold times prior to sleep
and tZZR nanoseconds after recovering from sleep. Clock
(CK) must also meet cycle high and low times during these
periods. Two cycles prior to sleep, initiation of either a read or
write operation is not allowed.
No Read/Write Allowed
During the period of time just prior to sleep and during
recovery from sleep, the assertion of any write or read signal
is not allowed. If a write or read operation occurs during
these periods, the memory array may be corrupted. Validity
of data out from the RAM can not be guaranteed immediately
after ZZ is asserted (prior to being in sleep). During sleep
mode recovery, the output impedance must be given
additional time above and beyond tZZR in order to match
desired impedance (see explanation in Output Impedance
Circuitry paragraph).
Sleep Mode
The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ).
All outputs will remain in a High–Z state while in sleep mode.
All inputs are allowed to toggle. The RAM will not be
selected, and perform any reads or writes.
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
13
Freescale Semiconductor, Inc.
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture.
The TAP controller is the state machine that controls the TAP
operation and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE
1149.1 compliant TAPs. The TAP operates using conventional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS
logic level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to VDD through a 1 k resistor. TDO should be left unconnected.
Freescale Semiconductor, Inc...
TAP DC OPERATING CHARACTERISTICS
(VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Logic Input Logic High
VIH1
2.0
VDD + 0.3
V
Logic Input Logic Low
VIL1
–0.3
0.8
V
Notes
Ilkg
—
±5
µA
1
CMOS Output Logic Low
VOL1
—
0.2
V
2
CMOS Output Logic High
VOH1
VDD – 0.2
—
V
3
Logic Input Leakage Current
TTL Output Logic Low
VOL2
—
0.4
V
4
TTL Output Logic High
VOH2
2.4
—
V
5
NOTES:
1. 0 V≤ Vin ≤ VDDQ for all logic input pins.
2. IOL1 ≤ 100 µA @ VOL = 0.2 V. Sampled, not 100% tested.
3. |IOH1| ≤ 100 µA @ VDDQ – 0.2 V. Sampled, not 100% tested.
4. IOL2 ≤ 8 mA @ VOL = 0.4 V.
5. |IOH2| ≤ 8 mA @ VOH = 2.4 V.
MCM69R738C•MCM69R820C
14
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Output Test Load . . . . . 50 Ω Parallel Terminated T–Line with 20 pF
Receiver Input Capacitance
Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
TAP CONTROLLER TIMING
Freescale Semiconductor, Inc...
Parameter
Symbol
Min
Max
Unit
Cycle Time
tTHTH
100
—
ns
Clock High Time
tTHTL
40
—
ns
Clock Low Time
tTLTH
40
—
ns
TMS Setup
tMVTH
10
—
ns
TMS Hold
tTHMX
10
—
ns
TDI Valid to TCK High
tDVTH
10
—
ns
TCK High to TDI Don’t Care
tTHDX
10
—
ns
Capture Setup
tCS
10
—
ns
1
Capture Hold
tCH
10
—
ns
1
tTLQX
0
—
ns
20
ns
TCK Low to TDO Unknown
TCK Low to TDO Valid
tTLOV
—
NOTE:
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
Notes
AC TEST LOAD
1.5 V
50 Ω
DEVICE
UNDER
TEST
50 Ω
20 pF
TAP CONTROLLER TIMING DIAGRAM
tTHTH
tTLTH
TEST CLOCK
(TCK)
tTHTL
tTHMX
tMVTH
TEST MODE SELECT
(TMS)
tTHDX
tDVTH
TEST DATA IN
(TDI)
tTLQV
tTLQX
TEST DATA OUT
(TDO)
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
15
Freescale Semiconductor, Inc.
TEST ACCESS PORT PINS
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
Freescale Semiconductor, Inc...
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (see Figure 5). An undriven TDI pin will produce the
same result as a logic 1 input level.
BOUNDARY SCAN REGISTER
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.
The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
IDENTIFICATION (ID) REGISTER
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (see Figure 5). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TRST — TAP RESET
This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic–reset state is entered while
TMS is held high for five rising edges of TCK. Power–on
reset circuitry is included internally. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
TEST ACCESS PORT REGISTERS
OVERVIEW
The various TAP registers are selected (one at a time) via
the sequences of 1s and 0s input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK
and push serial data out on subsequent falling edge of TCK.
When a register is selected, it is “placed” between the TDI
and TDO pins.
INSTRUCTION REGISTER
The ID register is a 32–bit register that is loaded with a
device and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
ID Register Presence Indicator
Bit No.
0
Value
1
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1–1990
Bit No.
11
10
9
8
7
6
5
4
3
2
1
Value
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
17
16
15
14
13
12
Value
x
x
x
x
x
x
Configuration
Bit No.
22
21
20
19
18
128K x 36
Value
0
0
1
0
0
256K x 18
Value
0
0
0
1
1
Configuration
Bit No.
27
26
25
24
23
128K x 36
Value
0
0
1
0
1
256K x 18
Value
0
0
1
1
0
Device Width
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are 3 bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at
power up or whenever the controller is placed in test–logic–
reset state.
Device Depth
BYPASS REGISTER
Revision Number
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
MCM69R738C•MCM69R820C
16
Bit No.
31
30
29
28
Value
x
x
x
x
Figure 4. ID Register Bit Meanings
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM69R738C Bump/Bit Scan Order
Bit
No.
Signal
g
Name
Bump
p
ID
Bit
No.
1
M2
5R
2
SA
4P
3
SA
4
5
MCM69R820C Bump/Bit Scan Order
Signal
g
Name
Bump
p
ID
Bit
No.
Signal
g
Name
Bump
p
ID
Bit
No.
Signal
g
Name
Bump
p
ID
36
SA
3B
1
M2
5R
36
SBb
3G
37
NC
2B
2
SA
6T
37
NC
4D
4T
38
SA
3A
3
SA
4P
38
SS
4E
SA
6R
39
SA
3C
4
SA
6R
39
NC
4G
SA
5T
40
SA
2C
5
SA
5T
40
NC
4H
6
ZZ
7T
41
SA
2A
6
ZZ
7T
41
SW
4M
7
DQa
6P
42
DQc
2D
7
DQa
7P
42
DQb
2K
8
DQa
7P
43
DQc
1D
8
DQa
6N
43
DQb
1L
9
DQa
6N
44
DQc
2E
9
DQa
6L
44
DQb
2M
10
DQa
7N
45
DQc
1E
10
DQa
7K
45
DQb
1N
11
DQa
6M
46
DQc
2F
11
SBa
5L
46
DQb
2P
12
DQa
6L
47
DQc
2G
12
CK
4L
47
SA
3T
13
DQa
7L
48
DQc
1G
13
CK
4K
48
SA
2R
14
DQa
6K
49
DQc
2H
14
G
4F
49
SA
4N
15
DQa
7K
50
DQc
1H
15
DQa
6H
50
SA
2T
16
SBa
5L
51
SBc
3G
16
DQa
7G
51
M1
3R
17
CK
4L
52
NC
4D
17
DQa
6F
18
CK
4K
53
SS
4E
18
DQa
7E
19
G
4F
54
NC
4G
19
DQa
6D
20
SBb
5G
55
NC
4H
20
SA
6A
21
DQb
7H
56
SW
4M
21
SA
6C
22
DQb
6H
57
SBd
3L
22
SA
5C
23
DQb
7G
58
DQd
1K
23
SA
5A
24
DQb
6G
59
DQd
2K
24
NC
6B
25
DQb
6F
60
DQd
1L
25
SA
5B
26
DQb
7E
61
DQd
2L
26
SA
3B
27
DQb
6E
62
DQd
2M
27
NC
2B
28
DQb
7D
63
DQd
1N
28
SA
3A
29
DQb
6D
64
DQd
2N
29
SA
3C
30
SA
6A
65
DQd
1P
30
SA
2C
31
SA
6C
66
DQd
2P
31
SA
2A
32
SA
5C
67
SA
3T
32
DQb
1D
33
SA
5A
68
SA
2R
33
DQb
2E
34
NC
6B
69
SA
4N
34
DQb
2G
35
SA
5B
70
M1
3R
35
DQb
1H
NOTES:
1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.
3. M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. M1 and M2 must be driven to within 100 mV of a VDD
or VSS supply rail to ensure consistent results.
4. ZZ must remain at VIL during boundary scan to ensure consistent results.
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
17
Freescale Semiconductor, Inc.
TAP CONTROLLER INSTRUCTION SET
Freescale Semiconductor, Inc...
OVERVIEW
There are two classes of instructions defined in IEEE Standard 1149.1–1990, the standard (public) instructions and
device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional
public instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all
input and I/O pads, but can not be used to load address,
data, or control signals into the RAM or to preload the I/O
buffers. In other words, the device will not perform IEEE
1149.1 EXTEST, INTEST, or the preload portion of the
SAMPLE/PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state,
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore, this
device is not IEEE 1149.1 compliant. Nevertheless, this RAM
TAP does respond to an all 0s instruction, as follows. With
the EXTEST (000) instruction loaded in the instruction
register, the RAM responds just as it does in response to the
SAMPLE/PRELOAD instruction described above, except the
DQ pins are forced to High–Z any time the instruction is
loaded.
IDCODE
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
into the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
MCM69R738C•MCM69R820C
18
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
If the SAMPLE–Z instruction is loaded in the instruction
register, all DQ pins are forced to an inactive drive state
(High–Z) and the boundary scan register is connected
between TDI and TDO when the TAP controller is moved to
the shift–DR state.
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP
Do not use these instructions; they are reserved for future
use.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
EXTEST
000
IDCODE
001**
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state. NOT IEEE 1149.1 COMPLIANT.
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
Places the bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins to High–Z state.
* Instruction codes expressed in binary; MSB on left, LSB on right.
** Default instruction automatically loaded at power up and in test–logic–reset state.
Freescale Semiconductor, Inc...
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
1
TEST–LOGIC
RESET
0
0
RUN–TEST/
IDLE
1
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–DR
SHIFT–IR
0
0
1
1
EXIT1–DR
1
0
PAUSE–DR
PAUSE–IR
0
1
0
1
EXIT2–DR
0
EXIT2–IR
1
1
UPDATE–DR
1
1
EXIT1–IR
0
0
1
0
0
UPDATE–IR
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69R738C•MCM69R820C
19
Freescale Semiconductor, Inc.
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69R738C
69R820C XX
X
X
Motorola Memory Prefix
R = Tape and Reel, Blank = Tray
Part Number
Speed (4 = 4 ns, 4.4 = 4.4 ns, 5 = 5 ns,
6 = 6 ns)
Package (ZP = PBGA)
Full Part Numbers — MCM69R738CZP4
MCM69R738CZP4.4
MCM69R738CZP5
MCM69R738CZP6
MCM69R820CZP4
MCM69R820CZP4.4
MCM69R820CZP5
MCM69R820CZP6
MCM69R738CZP4R
MCM69R738CZP4.4R
MCM69R738CZP5R
MCM69R738CZP6R
MCM69R820CZP4R
MCM69R820CZP4.4R
MCM69R820CZP5R
MCM69R820CZP6R
Freescale Semiconductor, Inc...
PACKAGE DIMENSIONS
ZP PACKAGE
7 X 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
E
C
B
D
E2
e
6X
M
A B C
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D1
16X
M
0.15
7 6 5 4 3 2 1
D2
b
0.3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
e
E1
TOP VIEW
BOTTOM VIEW
0.25 A
A3
0.35 A
0.20 A
A
A2
A1
SIDE VIEW
SEATING
PLANE
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
e
MILLIMETERS
MIN
MAX
–––
2.40
0.50
0.70
1.30
1.70
0.80
1.00
22.00 BSC
20.32 BSC
19.40
19.60
14.00 BSC
7.62 BSC
11.90
12.10
0.60
0.90
1.27 BSC
A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,
3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
Mfax : [email protected] – TOUCHTONE 1-602-244-6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
Motorola Fax Back System
– US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong.
– http://sps.motorola.com /mfax /
852-26668334
HOME PAGE : http://motorola.com/sps /
CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM69R738C•MCM69R820C ◊For More Information On This Product,
Go to: www.freescale.com
20
MOTOROLAMCM69R738C/D
FAST SRAM