MPQ4415M 1.5A, 36V, 2.2MHz, High-Efficiency, Synchronous, Step-Down Converter AEC-Q100 Qualified DESCRIPTION FEATURES The MPQ4415M is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. The MPQ4415M offers a very compact solution that achieves 1.5A of continuous output current with excellent load and line regulation over a wide input supply range. The MPQ4415M uses synchronous mode operation for higher efficiency over the output current load range. Current-mode operation provides fast transient response and eases loop stabilization. Full protection features include over-current protection (OCP) and thermal shutdown. The MPQ4415M requires a minimal number of readily available, standard, external components and is available in a space-saving QFN-13 (2.5mmx3mm) package. EMI Reduction Technique Wide 4V to 36V Operating Input Range 1.5A Continuous Load Current 90mΩ/50mΩ Low RDS(ON) Internal Power MOSFETs High-Efficiency Synchronous Mode Operation Default 2.2MHz Switching Frequency 450kHz to 2.2MHz Frequency Sync Forced Continuous Conduction Mode (CCM) Internal Soft Start (SS) Power Good (PG) Indicator Over-Current Protection (OCP) with ValleyCurrent Detection and Hiccup Thermal Shutdown Output Adjustable from 0.8V Available in a QFN-13 (2.5mmx3mm) Package CISPR25 Class 5 Compliant Available in a Wettable Flank Package Available in AEC-Q100 Grade 1 APPLICATIONS Automotive Industrial Control Systems Medical and Imaging Equipment Telecom Applications Distributed Power Systems All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 4V-36V BST MPQ4415M EN/SYNC VOUT SW EN/SYNC VCC PG FB PG PGND AGND MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER ORDERING INFORMATION Part Number* MPQ4415MGQB MPQ4415MGQB-AEC1 MPQ4415MGQBE-AEC1** Package QFN-13 (2.5mmx3mm) Top Marking See Below See Below * For Tape & Reel, add suffix –Z (e.g. MPQ4415MGQB–Z) ** Wettable Flank TOP MARKING (MPQ4415MGQB & MPQ4415MGQB-AEC1) ANM: Product code of MPQ4415MGQB and MPQ4415MGQB-AEC1 Y: Year code WW: Week code LLL: Lot number TOP MARKING (MPQ4415MGQBE-AEC1) AXR: Product code of MPQ4415MGQBE-AEC1 Y: Year code WW: Week code LLL: Lot number MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER PACKAGE REFERENCE TOP VIEW IN IN PGND PGND PGND BST 13 12 11 10 9 SW 8 AGND 7 VCC 1 2 3 4 5 6 NC PG EN/ SYNC FB QFN-13 (2.5mmx3mm) ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) Supply voltage (VIN) ....................... -0.3V to 40V Switch voltage (VSW) ............. -0.3V to VIN + 0.3V BST voltage (VBST) ...............................VSW + 6V All other pins ................................ -0.3V to 6V (2) Continuous power dissipation (TA = +25°C) (3) QFN-13 (2.5mmx3mm) ............................ 2.08W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature .................. -65°C to 150°C QFN-13 (2.5mmx3mm) ......... 60 ....... 13 ... °C/W Recommended Operating Conditions Supply voltage (VIN) ........................... 4V to 36V Output voltage (VOUT) ............... 0.8V to VIN*DMAX Operating junction temp. (TJ). .. -40°C to +125°C θJA θJC NOTES: 1) Absolute maximum ratings are rated under room temperature unless otherwise noted. Exceeding these ratings may damage the device. 2) For details on EN/SYNC’s ABS max rating, please refer to the Enable/SYNC section on page 13. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on JESD51-7, 4-layer PCB. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, VEN = 2V, TJ = -40°C to +125°C, unless otherwise noted, typical values are at TJ = +25°C. Parameter Symbol Supply current (shutdown) ISHDN Supply current (quiescent) IQ Condition HS switch on resistance LS switch on resistance RON_HS RON_LS VEN = 0V VEN = 2V, VFB = 1V, no switching VBST-SW = 5V VCC = 5V Switch leakage Current limit (5) Low-side valley current limit Reverse current limit Oscillator frequency Foldback frequency during soft start (5) Maximum duty cycle ISW_LKG ILIMIT VEN = 0V, VSW = 12V 20% duty cycle (5) Minimum on time Synchronous frequency range PG threshold hysteresis PG rising delay PG falling delay PG sink current capability PG leakage current VCC regulator VCC load regulation Soft-start time Thermal shutdown (5) Thermal hysteresis (5) 0.6 0.8 mA 90 50 155 105 mΩ mΩ 1 6.0 3.5 μA A A A kHz 4.0 2.5 1.2 2200 fSW DMAX VFB = 700mV 85 % 46 ns kHz mV mV nA V V TJ = +25°C TJ = -40°C to +125°C VFB = 820mV VEN_RISING VEN_FALLING 450 795 790 1.1 0.7 VEN_HYS IEN lockout μA 0.2 IFB lockout 8 VFB = 200mV Feedback current EN/SYNC rising threshold EN/SYNC falling threshold EN turn off delay VIN under-voltage threshold rising VIN under-voltage threshold hysteresis PG rising threshold PG falling threshold Units fFB τON_MIN fSYNC 1800 Max VFB = 700mV VFB EN/SYNC input current 2.4 1.7 Typ fSW Feedback voltage EN/SYNC threshold hysteresis Min VEN = 2V VEN = 0V INUVRISING 3 INUVHYS 807 807 10 1.45 1 2600 2200 819 824 50 1.8 1.3 450 5 0 3 10 0.2 mV μA μA μs 3.5 3.8 V 330 PGVth_RISING As a percentage of VFB PGVth_FALLING As a percentage of VFB 83 78 88 83 30 30 5 90 55 PGVth_HYS PGTD_RISING PGTD_FALLING VPG IPG_LKG VCC As a percentage of VFB ICC = 0mA ICC = 5mA 4.6 tSS VOUT from 10% to 90% 0.45 Sink 4mA 10 4.9 1.5 1.5 170 30 mV 93 88 % % 160 95 0.4 100 5.2 4 % μs μs V nA V % 3 ms °C °C NOTE: 5) Derived from bench characterization. Not tested in production. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 4 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER PIN FUNCTIONS Package Pin # Name Description Supply voltage. IN supplies power for the internal MOSFET and regulator. The MPQ4415M operates from a 4V to 36V input rail. A low ESR and low-inductance 1, 2 IN capacitor is required to decouple the input rail. Place the input capacitor very close to IN and connect it with wide PCB traces and multiple vias. No connection. Do not connect. 3 NC Power good indicator. The output of PG is an open drain and goes high if the output 4 PG voltage exceeds 88% of the nominal voltage. Enable/synchronize. Pull EN/SYNC high to enable the MPQ4415M. Float EN/SYNC or 5 EN/SYNC connect EN/SYNC to ground to disable the MPQ4415M. If an external sync clock is applied to EN/SYNC, the internal clock follows the sync frequency. Feedback. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. The frequency foldback comparator lowers the oscillator 6 FB frequency when the FB voltage is below 400mV to prevent current limit runaway during a short-circuit fault. Place the resistor divider as close to FB as possible. Avoid placing vias on the FB traces. Internal bias supply. Decouple VCC with a 0.1μF - 0.22μF capacitor. The capacitance 7 VCC should be no more than 0.22μF. Analog ground. AGND is the reference ground of the logic circuit. AGND is connected to 8 AGND PGND internally. There is no need to add external connections to PGND. Switch output. Connect SW using a wide PCB trace. 9 SW Bootstrap. A capacitor connected between SW and BST is required to form a floating 10 BST supply across the high-side switch driver. A 20Ω resistor placed between the SW and BST capacitor is strongly recommended to reduce SW voltage spikes. Power ground. PGND is the reference ground of the power device and requires careful 11, 12, 13 PGND consideration during PCB layout. For best results, connect PGND with copper pours and vias. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 6 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL CHARACTERISTICS (continued) MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 2.2µH, FSW = 2.2MHz, TA = +25°C, unless otherwise noted. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µH, FSW = 2.2MHz, TA = +25°C, unless otherwise noted. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µH, FSW = 2.2MHz, TA = +25°C, unless otherwise noted. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, Vout = 3.3V, IOUT = 1.5A, L = 2.2μH, FSW = 2.2MHz, with EMI filters, TA = +25°C, unless otherwise noted.(6) CISPR25 Class 5 Peak Radiated Emissions (150kHz - 30MHz) Data Class 5 Peak Class 5 Avg 0.15 5.15 10.15 15.15 20.15 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 Amplitude (dBuV/m) Amplitude (dBuV/m) 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 CISPR25 Class 5 Average Radiated Emissions (150kHz - 30MHz) Data Class 5 Peak Class 5 Avg 0.15 25.15 5.15 10.15 Frequency (MHz) Amplitude (dBuV/m) Data Class 5 Peak Class 5 Avg 0 100 200 300 400 500 600 700 800 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 Data Class 5 Peak Class 5 Avg 900 1000 0 100 200 Class 5 Avg 400 500 600 500 600 700 800 900 1000 CISPR25 Class 5 Average Radiated Emissions (Horizontal, 30MHz - 1GHz) Data Class 5 Peak 300 400 700 800 900 1000 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 Amplitude (dBuV/m) Amplitude (dBuV/m) 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 200 300 Frequency (MHz) CISPR25 Class 5 Peak Radiated Emissions (Horizontal, 30MHz - 1GHz) 100 25.15 CISPR25 Class 5 Average Radiated Emissions (Vertical, 30MHz - 1GHz) Frequency (MHz) 0 20.15 Amplitude (dBuV/m) CISPR25 Class 5 Peak Radiated Emissions (Vertical, 30MHz - 1GHz) 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 15.15 Frequency (MHz) Data Class 5 Peak Class 5 Avg 0 100 200 Frequency (MHz) 300 400 500 600 700 800 900 1000 Frequency (MHz) NOTE: 6) The EMC test results are based on the application circuit with EMI filters (see Figure 10 ). MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER BLOCK DIAGRAM Figure 1: Functional Block Diagram MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER OPERATION The MPQ4415M is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs. The MPQ4415M offers a very compact solution that achieves 1.5A of continuous output current with excellent load and line regulation over a 4V to 36V input supply range. The MPQ4415M operates in a fixed-frequency, peak-current-control mode to regulate the output voltage. An internal clock initiates a pulse-width modulation (PWM) cycle. The integrated high-side power MOSFET (HS-FET) turns on and remains on until the current reaches the value set by the COMP voltage (VCOMP). When the power switch is off, it remains off until the next clock cycle begins. If the current in the power MOSFET does not reach the value set by VCOMP within 85% of one PWM period, the power MOSFET is forced off. Internal Regulator A 4.9V internal regulator power most of the internal circuitries. This regulator takes VIN as the input and operates in the full VIN range. When VIN exceeds 4.9V, the output of the regulator is in full regulation. When VIN falls below 4.9V, the output decreases following VIN. A 0.1µF decoupling ceramic capacitor is required at VCC. Continuous Conduction Mode (CCM) Operation The MPQ4415M uses continuous conduction modulation (CCM) mode to ensure that the part works with a fixed frequency from a no-load to a full-load range. The advantage of CCM is the controllable frequency and lower output ripple at light load. Frequency Foldback The MPQ4415M enters frequency foldback when the input voltage is higher than about 21V. The frequency decreases to half the nominal value and changes to 1.1MHz. Frequency foldback also occurs during soft start and short-circuit protection. Error Amplifier (EA) The error amplifier (EA) compares the FB voltage to the internal 0.807V reference (VREF) and outputs a current proportional to the difference between the two. This output current then charges or discharges the internal compensation network to form VCOMP, which controls the power MOSFET current. The optimized internal compensation network minimizes the external component count and simplifies the control loop design. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 3.5V with a 330mV hysteresis. Enable/SYNC EN/SYNC is a control pin that turns the regulator on and off. Drive EN/SYNC high to turn on the regulator; drive EN/SYNC low to turn off the regulator. An internal 500kΩ resistor from EN/SYNC to GND allows EN/SYNC to be floated to shut down the chip. EN/SYNC is clamped internally using a 6.5V series Zener diode (see Figure 2). Connecting the EN/SYNC input through a pull-up resistor to the voltage on VIN limits the EN input current to less than 100µA. For example, with 12V connected to VIN, RPULLUP ≥ (12V - 6.5V) ÷ 100µA = 55kΩ. Connecting EN/SYNC to a voltage source directly without a pull-up resistor requires limiting the amplitude of the voltage source to ≤6V to prevent damage to the Zener diode. Figure 2: 6.5V Zener Diode Connection Connect an external clock with a range of 450kHz to 2.2MHz to synchronize the internal clock rising edge to the external clock rising edge. The pulse width of the external clock signal should be below 350ns; the off time of the external clock signal should be below 1.9µs. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER Internal Soft Start (SS) Soft start (SS) prevents the converter output voltage from overshooting during start-up. When the chip starts up, the internal circuitry generates a soft-start voltage (VSS). When VSS is lower than the internal reference (VREF), VSS overrides VREF, so the error amplifier uses VSS as the reference. When VSS exceeds VREF, the error amplifier uses VREF as the reference. The SS time is set to 1.5ms internally. Power Good (PG) The MPQ4415M has a power good (PG) indicator. PG is the open drain of a MOSFET and should be connected to VCC or another voltage source through a resistor (e.g.: 100kΩ). In the presence of an input voltage, the MOSFET turns on, and PG is pulled low before SS is ready. After VFB reaches 88% x VREF, PG is pulled high after a typical 90μs delay. When VFB drops to 83% x VREF, PG is pulled low. PG is also pulled low if thermal shutdown occurs or EN/SYNC is pulled low. Over-Current Protection (OCP) and Hiccup The MPQ4415M has cycle-by-cycle peak current-limit protection and valley-current detection protection. The inductor current is monitored during the HS-FET on-state. If the inductor current exceeds the current-limit value set by the COMP high-clamp voltage, the HSFET turns off immediately. Then the low-side MOSFET (LS-FET) turns on to discharge the energy, and the inductor current decreases. The HS-FET remains off unless the inductor valley current is lower than a certain current threshold (the valley current limit), even though the internal clock pulses high. If the inductor current does not drop below the valley current limit when the internal clock pulses high, the HS-FET misses the clock, and the switching frequency decreases to half the nominal value. Both the peak and valley current limits assist in keeping the inductor current from running away during an overload or short-circuit condition. If the output voltage drops below the undervoltage (UV) threshold (typically 50% below the reference), the peak current limit is kicked simultaneously, then the MPQ4415M enters hiccup mode to restart the part periodically. This protection mode is useful when the output is dead-shorted to ground and reduces the average short-circuit current greatly to alleviate thermal issues and protect the regulator. The MPQ4415M exits hiccup mode once the overcurrent condition is removed. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the die temperature exceeds 170°C, the entire chip shuts down. When the temperature drops below its lower threshold (typically 140°C), the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. The floating driver has its own UVLO protection with a rising threshold of 2.2V and hysteresis of 150mV. A dedicated internal regulator charges and regulates the bootstrap capacitor voltage to ~5V (see Figure 3). When the voltage between the BST and SW nodes drops below regulation, a PMOS pass transistor connected from VIN to BST turns on. The charging current path is from VIN to BST and then to SW. The external circuit should provide enough voltage headroom to facilitate charging. As long as VIN is higher than SW significantly, the bootstrap capacitor remains charged. When the HS-FET is on, VIN ≈ VSW, so the bootstrap capacitor cannot be charged. When the LS-FET is on, VIN - VSW reaches its maximum for fast charging. When there is no inductor current, VSW = VOUT, so the difference between VIN and VOUT can charge the bootstrap capacitor. A 20Ω resistor placed between the SW and BST capacitor is strongly recommended to reduce SW voltage spikes. Figure 3: Internal Bootstrap Charging Circuit MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER Start-Up and Shutdown If both VIN and EN/SYNC exceed their thresholds, the chip starts up. The reference block starts first, generating a stable reference voltage and current, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: VIN low, EN/SYNC low, and thermal shutdown. During the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider connected to FB sets the output voltage (see Figure 4). The feedback resistor (R1) also sets the feedback loop bandwidth with the internal compensation capacitor. Choose RFB1 to be around 40kΩ when VOUT 1V. RFB2 can then be calculated with Equation (1): R FB2 R FB1 VOUT 1 0.807V (1) The T-type network is highly recommended when VOUT is low (see Figure 4). RT R FB1 FB RT + RFB1 is used to set the loop bandwidth. The lower RT + RFB1 is, the higher the bandwidth. However, a high bandwidth may cause an insufficient phase margin, resulting in loop instability. Therefore, a proper RT value is required to make a trade-off between the bandwidth and phase margin. Table 1 lists the recommended feedback resistor and RT values for common output voltages. Table 1: Resistor Selection for Common Output 3.3 5 ICIN ILOAD VOUT V (1 OUT ) VIN VIN (2) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (3): ICIN ILOAD 2 (3) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current. Figure 4: T-Type Feedback Network RFB1 (kΩ) Since CIN absorbs the input switching current, it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated with Equation (2): VOUT R FB2 VOUT (V) For most applications, use a 4.7µF to 10µF capacitor. It is strongly recommended to use another lower-value capacitor (e.g.: 0.1µF) with a small package size (0603) to absorb highfrequency switching noise. Place the smaller capacitor as close to IN and GND as possible. RFB2 (kΩ) RT (kΩ) 41.2 (1%) 13 (1%) 20 (1%) 41.2 (1%) 7.68 (1%) 20 (1%) Selecting the Input Capacitor The input current to the step-down converter is discontinuous and therefore requires a capacitor to supply AC current to the converter while maintaining the DC input voltage. For the best performance, use low ESR capacitors. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g.: 0.1μF) as close to the IC as possible. When using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by the capacitance can be estimated with Equation (4): VIN ILOAD V V OUT (1 OUT ) fSW CIN VIN VIN (4) Selecting the Output Capacitor The output capacitor maintains the DC output voltage. Use ceramic, tantalum, or low ESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated with Equation (5): V V 1 VOUT OUT (1 OUT ) (RESR ) (5) fSW L VIN 8fSW COUT Where L is the inductor value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 16 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER For ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and the capacitance causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be estimated with Equation (6): VOUT VOUT V (1 OUT ) (6) 8 fSW L COUT VIN 2 VIN UVLO Setting The MPQ4415M has an internal, fixed, undervoltage lockout (UVLO) threshold. The rising threshold is 3.5V, while the falling threshold is about 3.17V. For applications that require a higher UVLO point, an external resistor divider between IN and EN/SYNC can be used to achieve a higher equivalent UVLO threshold (see Figure 5). For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (7): VOUT VOUT V (1 OUT ) RESR fSW L VIN (7) The characteristics of the output capacitor also affect the stability of the regulation system. The MPQ4415M can be optimized for a wide range of capacitance and ESR values. Selecting the Inductor A 1µH to 10µH inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. For higher efficiency, choose an inductor with a lower DC resistance. A larger-value inductor results in less ripple current and a lower output ripple voltage, but also has a larger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductor value is to allow the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (8): L VOUT V (1 OUT ) fSW IL VIN (8) Where ∆IL is the peak-to-peak inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The maximum inductor peak current can be calculated with Equation (9): ILP ILOAD VOUT V (1 OUT ) 2fSW L VIN Figure 5: Adjustable UVLO using EN Divider The UVLO threshold can be calculated with Equation (10) and Equation (11): INUVRISING (1 RUP ) VEN_RISING 500k*RDOWN 500k+RDOWN (10) INUVFALLING (1 RUP ) VEN_FALLING 500k*RDOWN 500k+RDOWN (11) Where VEN_RISING = 1.45V, and VEN_FALLING = 1V. When choosing RUP, ensure that it is large enough to limit the current flowing into EN/SYNC below 100µA. BST Resistor and External BST Diode A 20Ω resistor in series with the BST capacitor is recommended to reduce SW voltage spikes. A higher resistance is better for SW spike reduction, but also compromises efficiency. An external BST diode can enhance the efficiency of the regulator when the duty cycle is high (>65%). A power supply between 2.5V and 5V can be used to power the external bootstrap diode. VCC or VOUT is recommended for this power supply in the circuit (see Figure 6). (9) MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 17 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER VCC External BST diode 1N4148 BST VCC/VOUT RBST CBST L VOUT SW COUT Figure 6: Optional External Bootstrap Diode to Enhance Efficiency Top Layer The recommended external BST diode is IN4148, and the recommended BST capacitor value is 0.1µF to 1μF. PCB Layout Guidelines (7) Efficient PCB layout, especially regarding input capacitor placement, is critical for stable operation. A four-layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 7 and follow the guidelines below. Inner Layer 1 1. Use a large ground plane to connect directly to PGND. If the bottom layer is a ground plane, add vias near PGND. 2. Ensure that the high-current paths at GND and IN have short, direct, and wide traces. 3. Place the ceramic input capacitor, especially the small-sized input bypass capacitor (0603), as close to IN and PGND as possible to minimize high-frequency noise. Inner Layer 2 4. Keep the connection of the input capacitor and IN as short and wide as possible. 5. Place the VCC capacitor to VCC and AGND as close as possible. 6. Route SW and BST away from sensitive analog areas such as FB. Bottom Layer Figure 7: Recommended PCB Layout 7. Place the feedback resistors close to the chip to ensure that the trace connecting to FB is as short as possible. 8. Use multiple vias to connect the power planes to internal layers. NOTE: 7) The recommended layout is based on Figure 8. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 18 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS U1 VIN 4V-36V 1, 2 R1 1MΩ GND C1A 10μF C1B 10μF C1C 0.1μF BST R2 10 20Ω C3 0.1μF L1 MPQ4415M 5 EN/SYNC IN EN/SYNC SW 9 2.2μH R5 41.2kΩ 7 FB 4 PG PG NC 11,12,13 PGND C4 47μF GND R3 6 20kΩ VOUT R4 13kΩ 3 AGND 8 R6 100kΩ VCC C2 0.1μF 3.3V/1.5A Figure 8: VOUT = 3.3V, IOUT = 1.5A U1 VIN GND 4V-36V 1, 2 R1 1MΩ C1A 10μF C1B 10μF C1C 0.1μF BST 10 EN/SYNC SW R2 20Ω MPQ4415M 5 EN/SYNC IN 9 C3 0.1μF L1 2.2μH R5 41.2kΩ 7 PG FB C2 0.1μF 4 PG NC 11,12,13 PGND 6 R3 20kΩ VOUT GND R4 7.68kΩ 3 AGND 8 R6 100kΩ VCC 5V/1.5A C4 47μF Figure 9: VOUT = 5V, IOUT = 1.5A MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 19 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER VIN 4V-36V U1 FB1 1206 VEMI GND CIN1 CIN2 CIN3 1nF 10nF 1uF L1 2.2uH CIN4 10uF 1, 2 CIN5 10uF R1 1M C1A 10μF C1B 10μF IN BST C1C 0.1μF 20 C3 0.1μF L2 MPQ4415M 5 EN/SYNC 10 R2 EN/SYNC SW 9 L3 150nH 3.3V/1.5A 2.2μH R5 41.2k 7 PG FB 6 R3 20k 4 PG NC 11,12,13 PGND VOUT C5 1nF GND R4 13k 3 AGND 8 R6 100k VCC C2 0.1μF C4 47μF Figure 10: VOUT = 3.3V, IOUT = 1.5A, with EMI Filters MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 20 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER PACKAGE INFORMATION QFN-13 (2.5mmx3mm) Non-Wettable Flank PIN 1 ID MARKING PIN 1 ID 0.15X45ºTYP PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW 0.15X45º NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 3) JEDEC REFERENCE IS MO-220. 4) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 21 MPQ4415M – 36V, 1.5A, 2.2MHz, SYNCHRONOUS, STEP-DOWN CONVERTER PACKAGE INFORMATION QFN-13 (2.5mmx3mm) Wettable Flank PIN 1 ID MARKING PIN 1 ID 0.15X45ºTYP PIN 1 ID INDEX AREA TOP VIEW BOTTOM VIEW SIDE VIEW SECTION A-A NOTE: 0.15X45º 1) THE LEAD SIDE IS WETTABLE. 2) ALL DIMENSIONS ARE IN MILLIMETERS. 3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPQ4415M Rev. 1.01 www.MonolithicPower.com 9/30/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 22