Dynex DCR1474SY18 Phase control thyristor Datasheet

DCR1840Y85
Phase Control Thyristor
Preliminary Information
DS5767-1.2 MAY 2005 (LN23936)
FEATURES
•
Double Side Cooling
•
High Surge Capability
KEY PARAMETERS
VDRM
IT(AV)
ITSM
dV/dt*
dI/dt
APPLICATIONS
•
High Power Drives
•
High Voltage Power Supplies
•
Static Switches
8500V
1840A
25000A
1500V/µs
300A/µs
* Higher dV/dt selections available
VOLTAGE RATINGS
Part and
Ordering
Number
Repetitive Peak
Voltages
VDRM and VRRM
V
DCR1840Y85
DCR1840Y80
DCR1840Y75
DCR2220Y70
8500
8000
7500
7000
Conditions
Tvj = -40° C to 125° C,
IDRM = IRRM = 300mA,
VDRM, VRRM tp = 10ms,
VDSM & VRSM =
VDRM & VRRM + 100V
respectively
Lower voltage grades available.
ORDERING INFORMATION
When ordering, select the required part number
shown in the Voltage Ratings selection table.
For example:
Outline type code: Y
DCR1840Y85
(See Package Details for further information)
Note: Please use the complete part number when ordering
and quote this number in any future correspondence
relating to your order.
Fig. 1 Package outline
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DCR1840Y85
SEMICONDUCTOR
CURRENT RATINGS
Tcase = 60° C unless stated otherwise
Parameter
Symbol
Test Conditions
Max.
Units
1840
A
Double Side Cooled
IT(AV)
Mean on-state current
IT(RMS)
RMS value
-
2890
A
Continuous (direct) on-state current
-
2770
A
IT
Half wave resistive load
SURGE RATINGS
Parameter
Symbol
ITSM
2
It
Surge (non-repetitive) on-state current
Test Conditions
Max.
Units
10ms half sine, Tcase = 125° C
25.0
kA
VR = 0
3.125
MA s
Min.
Max.
Units
2
I t for fusing
2
THERMAL AND MECHANICAL RATINGS
Symbol
Rth(j-c)
Rth(c-h)
Tvj
Parameter
Thermal resistance – junction to case
Thermal resistance – case to heatsink
Virtual junction temperature
Test Conditions
Double side cooled
DC
-
0.00835
° C/W
Single side cooled
Anode DC
-
0.0134
° C/W
Cathode DC
-
0.023
° C/W
Clamping force 54.0kN
Double side
-
0.002
° C/W
(with mounting compound)
Single side
-
0.004
° C/W
On-state (conducting)
-
135
°C
Reverse (blocking)
-
125
°C
Tstg
Storage temperature range
-55
125
°C
Fm
Clamping force
48
59
kN
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DCR1840Y85
SEMICONDUCTOR
DYNAMIC CHARACTERISTICS
Symbol
IRRM/IDRM
Parameter
Test Conditions
Min.
Max.
Units
Peak reverse and off-state current
At VRRM/VDRM, Tcase = 125° C
-
300
mA
dV/dt
Max. linear rate of rise of off-state voltage
To 67% VDRM, Tj = 125° C, gate open
-
1500
V/µs
dI/dt
Rate of rise of on-state current
From 67% VDRM to 2x IT(AV)
Repetitive 50Hz
-
150
A/µs
Gate source 30V, 10Ω,
Non-repetitive
-
300
A/µs
tr < 0.5µs, Tj = 125° C
VT(TO)
rT
tgd
Threshold voltage – Low level
100A to1000A at Tcase = 125° C
-
0.9
V
Threshold voltage – High level
1000A to 7200A at Tcase = 125° C
-
1.3
V
On-state slope resistance – Low level
100A to 1000A at Tcase = 125° C
-
0.888
mΩ
On-state slope resistance – High level
1000A to 7200A at Tcase = 125° C
-
0.55
mΩ
TBD
TBD
µs
-
1200
µs
Delay time
VD = 67% VDRM, gate source 30V, 10Ω
tr = 0.5µs, Tj = 25° C
tq
Turn-off time
Tj = 125° C, VR = 200V, dI/dt = 1A/µs,
dVDR/dt = 20V/µs linear
QS
Stored charge
IT = 2000A, Tj = 125° C, dI/dt – 1A/µs,
4800
8000
µC
IL
Latching current
Tj = 25° C, VD = 5V
TBD
TBD
mA
IH
Holding current
Tj = 25° C, RG-K = ∞, ITM = 500A, IT = 5A
TBD
TBD
mA
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DCR1840Y85
SEMICONDUCTOR
GATE TRIGGER CHARACTERISTICS AND RATINGS
Symbol
Parameter
Test Conditions
Max.
Units
VGT
Gate trigger voltage
VDRM = 5V, Tcase = 25° C
1.5
V
VGD
Gate non-trigger voltage
At VDRM, Tcase = 125° C
TBD
V
IGT
Gate trigger current
VDRM = 5V, Tcase = 25° C
250
mA
IGD
Gate non-trigger current
VDRM = 5V, Tcase = 25° C
TBD
mA
CURVES
Instantaneous on-state current IT - (A)
7000
min 125° C
max 125° C
min 25° C
max 25° C
6000
5000
4000
3000
2000
1000
0
0.0
2.0
4.0
6.0
Instantaneous on-state voltage VT - (V)
Fig.2 Maximum & minimum on-state characteristics
VTM EQUATION
VTM = A + Bln (IT) + C.IT+D.√IT
Where
A = 0.398265
B = 0.121095
C = 0.000524
D = -0.000007
these values are valid for Tj = 125° C for IT 500A to 7200A
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DCR1840Y85
SEMICONDUCTOR
10
130
Maximum case temperature, T case ( oC )
Mean power dissipation - (kW)
8
7
6
5
4
180
120
90
60
30
3
2
1
100
90
80
70
60
50
40
30
20
0
0
500
1000
1500
2000
2500
0
500
1000
1500
2000
2500
Mean on-state current, IT(AV) - (A)
Mean on-state current, IT(AV) - (A)
Fig.3 On-state power dissipation – sine wave
Fig.4 Maximum permissible case temperature,
double side cooled – sine wave
130
12
180
120
90
60
30
120
110
100
11
10
Mean power dissipation - (kW)
o
110
10
0
Maximum heatsink temperature, T Heatsink - ( C )
180
120
90
60
30
120
9
90
80
70
60
50
40
30
9
8
7
6
5
4
20
2
10
1
0
0
500
1000
1500
2000
2500
d.c.
180
120
90
60
30
3
0
0
500 1000 1500 2000 2500 3000 3500
Mean on-state current, IT(AV) - (A)
Mean on-state current, IT(AV) - (A)
Fig.5 Maximum permissible heatsink temperature,
double side cooled – sine wave
Fig.6 On-state power dissipation – rectangular wave
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DCR1840Y85
SEMICONDUCTOR
130
d.c.
180
120
90
60
30
120
110
100
90
80
70
60
50
40
30
20
110
100
90
80
70
60
50
40
30
20
10
10
0
0
0
500
d.c.
180
120
90
60
30
120
o
Maximum heatsik temperature T
heatsink - ( C)
Maximum permissible case temperature , T
case - (°C)
130
1000 1500 2000 2500 3000 3500
0
1000 1500 2000 2500 3000 3500
Mean on-state current, IT(AV) - (A)
Mean on-state current, IT(AV) - (A)
Fig.7 Maximum permissible case temperature,
double side cooled – rectangular wave
Fig.8 Maximum permissible heatsink temperature,
double side cooled – rectangular wave
25
Thermal Impedance, Zth(j-c) - ( °C/kW)
500
1
0.612
Double side cooledRi (° C/kW)
Ti (s)
Anode side cooled Ri (° C/kW)
20
Ti (s)
Double Side Cooling
Ri (° C/kW)
Cathode side cooled
Anode Side Cooling
15
4
2.8608
0.010332 0.056415 0.333082
1.6323
3.61
7.1383
0.011328 0.065993 0.419695
9.0612
0.6728
Ti (s)
Cathode Sided Cooling
3
3.1053
0.7009
2
1.7721
1.9388
2.0168
0.010954 0.065544
1.7306 18.6391
0.30379
5.7274
Zth = Σ [Ri x ( 1-exp. (t/ti))] [1]
10
∆Rth(j-c) Conduction
Tables show the increments of thermal resistance R th(j-c) when the device
operates at conduction angles other than d.c.
5
0
0.001
0.01
0.1
1
Time ( s )
10
100
Double side cooling
∆Zth (z)
sine.
rect.
θ°
180
0.94
0.65
120
1.09
0.92
90
1.24
1.07
60
1.38
1.23
30
1.49
1.40
15
1.54
1.49
Anode Side Cooling
∆Zth (z)
sine.
rect.
θ°
180
0.94
0.64
120
1.08
0.91
90
1.23
1.06
60
1.37
1.22
30
1.47
1.38
15
1.52
1.47
Cathode Sided Cooling
∆Zth (z)
sine.
rect.
θ°
180 0.94
0.64
120 1.08
0.91
90
1.24
1.06
60
1.37
1.22
30
1.48
1.39
15
1.53
1.48
Fig.9 Maximum (limit) transient thermal impedance – junction to case (° C/kW)
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DCR1840Y85
SEMICONDUCTOR
70
6
15
50
4
2
40
3
2
30
2
Conditions:
Tcase= 125° C
VR = 0
half-sine wave
20
10
10
1
0
1
10
Number of cycles
Fig.10 Multi-cycle surge current
100
5
I t (MA s)
20
I2t
ITSM
60
Conditions:
Tcase = 125° C
VR =0
Pulse width = 10ms
Surge current, ITSM - (kA)
Surge current, ITSM- (kA)
25
1
10
0
100
Pulse width, tP - (ms)
Fig.11 Single-cycle surge current
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DCR1840Y85
SEMICONDUCTOR
PACKAGE DETAILS
For further package information, please contact Customer Services. All dimensions in mm, unless stated otherwise.
DO NOT SCALE.
3rd ANGLE PROJECTION
DO NOT SCALE
IF IN DOUBT ASK
HOLE Ø3.60 X 2.00
DEEP (IN BOTH
ELECTRODES)
20° OFFSET (NOM.)
TO GATE TUBE
Ø112.5 MAX.
Ø73.0 NOM.
Ø1.5
CATHODE
Device
DCR1474SY18
DCR1475SY28
DCR1476SY42
DCR1478SY48
DCR1574SY28
DCR1575SY42
DCR1576SY52
DCR3910Y22
DCR3650Y28
DCR2930Y42
DCR2630Y52
DCR2220Y65
DCR1840Y85
Maximum Minimum
Thickness Thickness
(mm)
(mm)
35.045
34.395
35.12
34.47
35.35
34.7
35.47
34.82
35.12
34.47
35.35
34.7
35.47
34.82
35.045
34.395
35.12
34.47
35.35
34.7
35.47
34.82
35.73
35.08
36.09
35.44
GATE
ANODE
Ø73.0 NOM.
FOR PACKAGE HEIGHT
SEE TABLE
Lead length: 420mm
Lead terminal connector: M4 ring
Package outline type code: Y
Fig.15 Package outline
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DCR1840Y85
SEMICONDUCTOR
POWER ASSEMBLY CAPABILITY
The Power Assembly group was set up to provide a support service for those customers requiring more than the basic
semiconductor, and has developed a flexible range of heatsink and clamping systems in line with advances in device voltages
and current capability of our semiconductors.
We offer an extensive range of air and liquid cooled assemblies covering the full range of circuit designs in general use today.
The Assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our
customers.
Using the latest CAD methods our team of design and applications engineers aim to provide the Power Assembly Complete
Solution (PACs).
HEATSINKS
The Power Assembly group has its own proprietary range of extruded aluminium heatsinks which have been designed to optimise
the performance of Dynex semiconductors. Data with respect to air natural, forced air and liquid cooling (with flow rates) is
available on request.
For further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or
Customer Services.
Stresses above those listed in this data sheet may cause permanent damage to the device. In extreme conditions, as with all
semiconductors, this may include potentially hazardous rupture of the package. Appropriate safety precautions should always be
followed.
http://www.dynexsemi.com
e-mail: [email protected]
HEADQUARTERS OPERATIONS
DYNEX SEMICONDUCTOR LTD
Doddington Road, Lincoln
Lincolnshire, LN6 3LF. United Kingdom.
Tel: +44(0)1522 500500
Fax: +44(0)1522 500550
CUSTOMER SERVICE
Tel: +44(0)1522 502753 / 502901. Fax: +44(0)1522 500020
 Dynex Semiconductor 2003 TECHNICAL DOCUMENTATION – NOT FOR
RESALE. PRODUCED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or
suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible
methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to
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