ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843021 is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS843021 uses a 25MHz crystal to synthesize 125MHz. The ICS843021 has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The ICS843021 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 22.4MHz - 28MHz, 18pF parallel resonant crystal • Output frequency range: 112MHz - 140MHz • VCO range: 560MHz to 700MHz • Output duty cycle range: 49% - 51% • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.37ps (typical) • RMS phase noise at 125MHz (typical) Offset Noise Power 100Hz ............... -94.2 dBc/Hz 1KHz .............. -122.8 dBc/Hz 10KHz .............. -132.2 dBc/Hz 100KHz .............. -131.3 dBc/Hz • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Lead-Free package fully RoHS compliant FREQUENCY TABLE - TYPICAL APPLICATIONS Inputs Crystal Frequency (MHz) Output Frequency (MHz) 25 12 5 26.6 133 BLOCK DIAGRAM PIN ASSIGNMENT 25MHz XTAL_IN OSC XTAL_OUT Phase Detector VCO nQ0 ÷5 Q0 VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q0 nQ0 nc ICS843021 ÷25 (fixed) 843021AG 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VCCA Power Analog supply pin. 2 Power 5 VEE XTAL_OUT, XTAL_IN nc Unused Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. 6, 7 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core supply pin. 3, 4 Type Input Description TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 843021AG Test Conditions Minimum Typical 4 www.icst.com/products/hiperclocks.html 2 Maximum Units pF REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±10%, TA=0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 85 mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±10%, TA=0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency; NOTE 1 14 50 Ω Shunt Capacitance 7 pF NOTE 1: Input frequency is limited to a range of 22.4MHz - 28MHz due to VCO range. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±10%, TA=0°C TO 70°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter, (Random); NOTE 1 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions Typical 112 125MHz (Intergration Range: 1.875MHz to 20MHz) 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. 843021AG Minimum www.icst.com/products/hiperclocks.html 3 Maximum Units 140 MHz 0.37 ps 250 550 ps 49 51 % REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TYPICAL PHASE NOISE AT 125MHZ ➤ 0 -10 -20 10 Gb Ethernet Filter -30 -40 125MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) -60 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -70 -120 -130 -140 -150 -160 ➤ -170 Phase Noise Result by adding a 10 Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843021AG www.icst.com/products/hiperclocks.html 4 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power V CC LVPECL Phase Noise Mask nQx VEE f1 Offset Frequency f2 -1.3V ± 0.33V RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ0 80% Q0 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843021AG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 843021AG www.icst.com/products/hiperclocks.html 6 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION SCHEMATIC Figure 3A shows a schematic example of the ICS843021. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz VCC output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VCCA VCC R2 10 C3 10uF C4 0.01u R3 133 U1 R5 133 Zo = 50 Ohm Q 1 2 3 4 C2 33pF 25MHz 18pF VCCA VEE XTAL_OUT XTAL_IN VCC Q0 nQ0 NC 8 7 6 5 VCC + Zo = 50 Ohm nQ X1 - ICS843021 ICS843011 R4 82.5 C5 0.1u C1 27pF R6 82.5 VCC=3.3V FIGURE 3A. ICS843021 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS843021 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS843021 PC BOARD LAYOUT EXAMPLE 843021AG www.icst.com/products/hiperclocks.html 7 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843021. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 85mA = 308.6mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.63V, with all outputs switching) = 308.6mW + 30mW = 338.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.339W * 90.5°C/W = 100.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W NOTE: Most modern PCB designs use multi-layered boards. 843021AG www.icst.com/products/hiperclocks.html 8 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843021AG www.icst.com/products/hiperclocks.html 9 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843021 is: 1928 843021AG www.icst.com/products/hiperclocks.html 10 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843021AG www.icst.com/products/hiperclocks.html 11 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843021AG 3021A 8 lead TSSOP tube 0°C to 70°C ICS843021AGT 3021A 8 lead TSSOP 2500 tape & reel 0°C to 70°C ICS843021AGLF 021AL 8 lead "Lead-Free" TSSOP tube 0°C to 70°C ICS843021AGLFT 021AL 8 lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843021AG www.icst.com/products/hiperclocks.html 12 REV. C MARCH 31, 2005 ICS843021 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev B B C C C 843021AG Table Page 1 T4 3 T5 3 T9 T3A 12 3 T6 T7 T9 T9 3 8 10 12 1 12 Description of Change Added Function Table. Features section - updated Cr ystal, Output Frequency & VCO range bullets. Cr ystal Characteristics Table - changed Frequency from 25MHz typical to 14MHz min. and 40MHz max. Added Note 1. AC Characteristics Table - changed Output Frequency from 125MHz typical to 112MHz min. and 140MHz max. Ordering Information Table - corrected count from 154 per tube to 100 Power Supply Table - increased VCC to 3.3V ± 10% from 5% and is reflected throughout the datasheet. Absolute Maximum Ratings - corrected Package Thermal Impedance air flow. Thermal Resistance Table - corrected air flow. Corrected air flow in table. Ordering Information Table - corrected marking. Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number. www.icst.com/products/hiperclocks.html 13 Date 10/6/04 10/15/04 11/3/04 11/30/04 3/31/05 REV. C MARCH 31, 2005