CY25100 Field and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction Features Benefits ■ Wide operating output (SSCLK) frequency range ❐ 3 MHz to 200 MHz ■ Services most PC peripherals, networking, and consumer applications. ■ Programmable spread spectrum with nominal 31.5 kHz modulation frequency ❐ Center spread: ±0.25% to ±2.5% ❐ Down spread: –0.5% to –5.0% ■ Provides wide range of spread percentages for maximum electromagnetic interference (EMI) reduction, to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. ■ Input frequency range ❐ External crystal: 8 to 30 MHz fundamental crystals ❐ External reference: 8 to 166 MHz clock ■ Eliminates the need for expensive and difficult to use higher order crystals. ■ Integrated phase-locked loop (PLL) ■ Internal PLL to generate up to 200 MHz output. Able to generate custom frequencies from an external crystal or a driven source. ■ Field programmable ❐ CY25100SCF and CY25100SIF, 8-pin SOIC ❐ CY25100ZCF and CY25100ZIF, 8-pin TSSOP ■ ■ Programmable crystal load capacitor tuning array ■ Low cycle-to-cycle jitter In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY3690 (TSSOP) or CY3691 (SOIC) socket adapter. Production quantities are available through Cypress’s value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. ■ 3.3V operation ■ ■ Commercial and industrial operation Enables fine tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. ■ Spread spectrum on/off function ■ Suitable for most PC, consumer, and networking applications. ■ Power down or Output Enable function ■ Application compatibility in standard and low power systems. ■ Ability to enable or disable spread spectrum with an external pin. ■ Enables low power state or output clocks to High-Z state. Logic Block Diagram RFB PLL with MODULATION CONTROL 3 XIN C XIN 6 OUTPUT DIVIDERS and MUX PROGRAMMABLE CONFIGURATION 2 XOUT C XOUT REFCLK 7 4 SSCLK PD# or OE 8 SSON# Cypress Semiconductor Corporation Document #: 38-07499 Rev. *F • 1 5 VDD VSS 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 4, 2008 [+] Feedback CY25100 Pinouts Figure 1. CY25100 8-Pin SOIC/TSSOP 1 VDD SSON# 8 2 XOUT SSCLK 7 3 XIN/CLKIN REFCLK 6 4 PD#/OE VSS 5 Pin Description Pin Name Description 1 VDD 3.3V power supply. 2 XOUT Crystal output. Leave this pin floating if external clock is used. 3 XIN/CLKIN Crystal input or reference clock input. 4 PD#/OE Power down pin: Active LOW. If PD# = 0, PLL and Xtal are powered down, and outputs are weakly pulled low. Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the option of choosing either PD# or OE function. 5 VSS Power supply ground. 6 REFCLK Buffered reference output. 7 SSCLK Spread spectrum clock output. 8 SSON# Spread spectrum control. 0 = spread on. 1 = spread off. General Description The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC used to reduce EMI found in today’s high speed digital electronic systems. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25100 uses a factory or field-programmable configuration memory array to synthesize output frequency, spread percentage, crystal load capacitor, reference clock output on/off, spread spectrum on/off function, and PD#/OE options. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.50%. The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread percentage amounts, if required. The input to the CY25100 can either be a crystal or a clock signal. The input frequency range for crystals is 8 to 30 MHz, and for clock signals is 8 to 166 MHz. The CY25100 has two clock outputs, REFCLK and SSCLK. The non spread spectrum REFCLK output has the same frequency as the input of the CY25100. The frequency modulated SSCLK output can be programmed from 3 to 200 MHz. The CY25100 products are available in 8-pin SOIC and TSSOP packages with commercial and industrial operating temperature ranges. Table 1. Pin Function Pin Name Input Frequency Total Xtal Load Capacitance XIN and XOUT XIN and XOUT Output Frequency Spread Percent (0.5% – 5%, 0.25% Intervals) Reference Output SSCLK SSCLK REFOUT Power down or Frequency Output Enable Modulation PD#/OE SSCLK Pin# 3 and 2 3 and 2 7 7 6 4 7 Unit MHz pF MHz % On or Off Select PD# or OE kHz ENTER DATA ENTER DATA ENTER DATA 31.5 Program Value ENTER DATA ENTER DATA ENTER DATA Document #: 38-07499 Rev. *F Page 2 of 13 [+] Feedback CY25100 Programming Description Product Functions Field Programmable CY25100 Input Frequency (XIN, Pin 3 and XOUT, Pin 2) The CY25100 is programmed at the package level, that is, in a programmer socket. The CY25100 is Flash based, so the parts can be reprogrammed up to 100 times. This allows fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. The input to the CY25100 can be a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signals is 8 to 166 MHz. Samples and small prototype quantities can be programmed on the CY3672 programmer with CY3690 (TSSOP) or CY3691 (SOIC) socket adapter. The load capacitors at Pin 1 (CXIN) and Pin 8 (CXOUT) can be programmed from 12 pF to 60 pF with 0.5 pF increments. The programmed value of these on-chip crystal load capacitors are the same (XIN = XOUT = 12 to 60 pF). CyberClocks™ Online Software CyberClocks™ Online Software is a web based software application that allows the user to custom-configure the CY25100. All the parameters in Table 1 given as “Enter Data” can be programmed into the CY25100. CyberClocks Online outputs an industry-standard JEDEC file used for programming the CY25100. CyberClocks Online is available at www.cyberclocksonline.com web site through user registration. To register, fill out the registration form and make sure to check the “non-standard devices” box. For more information on the registration process refer to CY3672 data sheet For information regarding spread spectrum software programming solutions, contact your local Cypress sales representative or Field Application Engineer (FAE). CY3672 FTG Programming Kit and CY3690/CY3691 Socket Adapter The Cypress CY3672 FTG programmer and CY3690 and CY3691 socket adapters are required to program the CY25100. The CY3690 enables users to program CY25100ZCF and CY25100ZIF (TSSOP). CY3691 provides the ability to program CY25100SCF and CY25100SIF (SOIC). Each socket adapter comes with small prototype quantities of CY25100. The CY3690 and CY3691 is a separate orderable item, so the existing users of the CY3672 FTG development kit or CY3672-PRG programmer need to order only the socket adapters to program the CY25100. Factory Programmable CY25100 Factory programming is available for volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. A sample request form (refer to “CY25100 Sample Request Form” at www.cypress.com) must be completed. After the request is processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. Additional information on the CY25100 can be obtained from the Cypress web site at www.cypress.com. CXIN and CXOUT (Pin 3 and Pin 2) The required values of CXIN and CXOUT are calculated using the following formula: CXIN = CXOUT = 2CL – CP where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance. For example, if a fundamental 16 MHz crystal with CL of 16 pF is used and CP is 2 pF, CXIN and CXOUT are calculated as: CXIN = CXOUT = (2 x 16) – 2 = 30 pF If using a driven reference, set CXIN and CXOUT to the minimum value 12 pF. Output Frequency, SSCLK Output (SSCLK, Pin 7) The modulated frequency at the SSCLK output is produced by synthesizing the input reference clock. The modulation can be stopped by SSON# digital control input (SSON# = HIGH, no modulation). If modulation is stopped, the clock frequency is the nominal value of the synthesized frequency without modulation (spread percentage = 0). The range of synthesized clock is from 3 to 200 MHz. Spread Percentage (SSCLK, Pin 7) The SSCLK spread can be programmed at any percentage value from ±0.25% to ±2.5% for center spread and from –0.5% to –5.0% down spread. Reference Output (REFOUT, Pin 6) The reference clock output has the same frequency and the same phase as the input clock. This output can be programmed to be enabled (clock on) or disabled (High-Z, clock off). If this output is not required, it is recommended that users request the disabled (High-Z, Clock Off) option. Frequency Modulation The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 3 to 200 MHz. Contact the factory if a higher modulation frequency is required. Power Down or Output Enable (PD# or OE, Pin 4) The part can be programmed to include either PD# or OE function. PD# function powers down the oscillator and PLL. The OE function disables the outputs. Document #: 38-07499 Rev. *F Page 3 of 13 [+] Feedback CY25100 Absolute Maximum Rating Junction Temperature ................................ –40°C to +125°C Supply Voltage (VDD)........................................ –0.5 to +7.0V DC Input Voltage ......................................–0.5V to VDD + 0.5 Storage Temperature (Non condensing)..... –55°C to +125°C Data Retention at Tj = 125°C ................................> 10 years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) Recommended Crystal Specifications Parameter Description Comments Min Typ Max Unit FNOM Nominal Crystal Frequency Parallel resonance, fundamental mode, AT cut 8 – 30 MHz CLNOM Nominal Load Capacitance Internal load caps 6 – 30 pF Fundamental mode R1 Equivalent Series Resistance (ESR) – – 25 Ω R3/R1 Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much Fundamental Mode ESR less than the maximum spec 3 – – – DL Crystal Drive Level – 0.5 2 mW No external series resistor assumed Operating Conditions Parameter Description VDD Supply Voltage TA Ambient Commercial Temperature Ambient Industrial Temperature Min Typ Max Unit 3.13 3.30 3.45 V 0 – 70 °C –40 – 85 °C CLOAD Maximum Load Capacitance at Pin 6 and Pin 7 – – 15 pF Fref External Reference Crystal (Fundamental tuned crystals only) 8 – 30 MHz External Reference Clock 8 – 166 MHz FSSCLK SSCLK Output Frequency, CLOAD = 15 pF 3 – 200 MHz FREFCLK REFCLK Output Frequency, CLOAD = 15 pF 8 – 166 MHz FMOD Spread Spectrum Modulation Frequency 30.0 31.5 33.0 kHz TPU Power Up Time for all VDDs to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms Min Typ Max Unit 10 12 DC Electrical Characteristics Parameter Description Condition IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V (source) mA IOL Output Low Current VOL = 0.5, VDD= 3.3V (sink) 10 12 VIH Input High Voltage CMOS levels, 70% of VDD 0.7VDD – VDD V VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3VD V mA D IIH Input High Current, PD#/OE and SSON# Pins Vin = VDD – – 10 μA IIL Input Low Current, PD#/OE and SSON# Vin = VSS Pins – – 10 μA IOZ Output Leakage Current Three-state output, PD#/OE = 0 10 μA CXIN or CXOUT[1] Programmable Capacitance at Pin 2 and Pin 3 Capacitance at minimum setting – 12 – pF Capacitance at maximum setting – 60 – pF CIN[1] Input Capacitance at Pin 4 and Pin 8 Input pins excluding XIN and XOUT – 5 7 pF –10 Note 1. Guaranteed by characterization, not 100% tested. Document #: 38-07499 Rev. *F Page 4 of 13 [+] Feedback CY25100 DC Electrical Characteristics Parameter (continued) Description Condition Min Typ Max Unit IVDD Supply Current VDD = 3.45V, Fin = 30 MHz, REFCLK = 30 MHz, SSCLK = 66 MHz, CLOAD = 15 pF, PD#/OE = SSON# = VDD – 25 35 mA IDDS Standby Current VDD = 3.45V, Device powered down with PD# = 0V (driven reference pulled down) – 15 30 μA Min 45 40 Typ 50 50 Max 55 60 Unit % % 0.7 1.1 3.6 V/ns 0.7 1.1 3.6 V/ns 1.0 1.6 4.0 V/ns 1.2 1.6 4.0 V/ns – 90 120 ps – 100 130 ps – 130 170 ps – 100 130 ps – 105 140 ps – 200 260 ps – 80 100 ps – 100 130 ps – 135 180 ps – 150 350 ns – 150 350 ns – 150 350 ns – 3.5 5 ms – 2 3 ms AC Electrical Characteristics [1] Parameter Description DC Output Duty Cycle Output Duty Cycle SR1 Rising Edge Slew Rate SR2 Falling Edge Slew Rate SR3 Rising Edge Slew Rate SR4 Falling Edge Slew Rate TCCJ1[2] Cycle-to-Cycle Jitter SSCLK (Pin 7) TCCJ2[2] TCCJ3[2] tSTP TOE1 TOE2 tPU1 tPU2 Cycle-to-Cycle Jitter SSCLK (Pin 7) Cycle-to-Cycle Jitter REFCLK (Pin 6) Power down Time (pin 4 = PD#) Output Disable Time (pin 4 = OE) Output Enable Time (pin 4 = OE) Power Up Time, Crystal is used Power Up Time, Reference clock is used Condition SSCLK, Measured at VDD/2 REFCLK, Measured at VDD/2 Duty Cycle of CLKIN = 50% at input bias SSCLK from 3 to 100 MHz; REFCLK from 3 to 100 MHz. 20%–80% of VDD SSCLK from 3 to 100 MHz; REFCLK from 3 to 100 MHz. 80%–20% of VDD SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 20%–80% of VDD SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 80%–20% of VDD CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK off CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK off CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK off CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK on CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK on CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on Time from falling edge on PD# to stopped outputs (Asynchronous) Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous), reference clock at correct frequency Note 2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temperature, and output load. Document #: 38-07499 Rev. *F Page 5 of 13 [+] Feedback CY25100 Application Circuit Figure 2. Application Circuit Diagram[3, 4, 5] Pow er 1 VDD 2 XOUT SSON# 8 0 .1 u F SSCLK 7 CY25100 VDD 3 X IN /C L K IN 4 P D # /O E REFCLK 6 VSS 5 Switching Waveforms Figure 3. Duty Cycle Timing (DC = t1A/t1B) OUTPUT t1A t1B Figure 4. Output Rise/Fall Time (SSCLK and REFCLK) VDD OUTPUT 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 5. Power Down and Power Up Timing POWER DOWN VDD 0V VIH VIL tPU High Impedance CLKOUT (Asynchronous) tSTP Notes 3. Because the load capacitors (CXIN and CXOUT) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load capacitor (CL). Only a single 0.1-μF bypass capacitor is required on the VDD pin. 4. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected). 5. If SSON# (pin 8) is LOW (VSS), the frequency modulation is on at SSCLK pin (pin 7). Document #: 38-07499 Rev. *F Page 6 of 13 [+] Feedback CY25100 Switching Waveforms Figure 6. Output Enable/Disable Timing VDD VIH OUTPUT ENABLE VIL 0V TOE2 High Impedance CLKOUT (Asynchronous) TOE1 Informational Graphs [6] 172.5 161.5 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 160.5 162.5 171.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 168.5 167.5 166.5 Fnominal 165.5 164.5 163.5 162.5 159.5 0 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 0 20 68.5 40 60 80 100 120 Time (us) 140 160 180 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 20 40 60 80 200 67.5 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 67.5 67 66.5 66.5 Fnominal 66 Fnominal 66 65.5 65.5 65 64.5 65 64 64.5 63.5 0 20 40 60 80 100 120 Time (us) Document #: 38-07499 Rev. *F 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Page 7 of 13 [+] Feedback CY25100 Informational Graphs (continued)[6] IDD vs. SSCLK Duty Cycle vs. REFCLK Te m pe r atu r e =25C, V DD=3.3V , CLOAD=15p F, SS off, ( C L OA D =1 5 p F ) 60 58 56 54 52 50 48 46 44 42 40 30 25 IDD (m A) Duty Cycle (%) Re fclk = 30M Hz 20 15 10 5 0 50 100 150 0 200 0 50 100 150 200 REFCLK (MHz) SSCLK (M Hz ) Measured Spread% vs. VDD over Tem perature (Target Spread = 0.5%, Fout=100MHz, CLOA D =15pF) Measured Spread% vs. VDD over Tem perature (Target Spread = 5.0%, Fout=100MHz, CLOA D =15pF) 0.55% -40C 0.50% 25C 0.45% 85C 6.00% Spread% Spread% 0.60% 5.50% -40C 5.00% 25C 4.50% 85C 4.00% 0.40% 2.7 3 3.3 3.6 2.7 3.9 3 0 -2 -40C -4 25C -6 85C -8 -10 3.3 VDD (V) 3.9 SSCLK Attenuation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=5.0%, CLOAD=15pF) 3.6 3.9 Attenuation (dB) Attenuation (dB) SSCLK Attenuation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=0.5%, CLOA D =15pF) 3 3.6 VDD (V) VDD (V) 2.7 3.3 -10 -12 -14 -16 -18 -20 -40C 25C 85C 2.7 3 3.3 3.6 3.9 VDD (V) Note 6. The Informational Graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages 4 and 5 for device specifications. Document #: 38-07499 Rev. *F Page 8 of 13 [+] Feedback CY25100 Informational Graphs (continued)[6] Max Cycle-Cycle Jitter on SSCLK vs. Tem perature (SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/2%spread, REFCLK off) 0 200 -2 175 -4 150 Jitter (ps) Attenuation (dB) SSCLK EMI Attenuation vs. Spread% (Measured at 7th Harmonic Temp=25C, VDD=3.3V, SSCLK=100MHz, Measured on Cypress Characterization board w ith CLOAD=15pF) -6 -8 -10 -12 125 100 75 50 25 -14 0 -16 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% Spread % Document #: 38-07499 Rev. *F 3.5% 4.0% 4.5% 5.0% -40 - 20 0 20 40 60 80 100 Tem perature (deg C) Page 9 of 13 [+] Feedback CY25100 Ordering Information Part Number Package Description Product Flow Pb-Free CY25100SXCF 8-Pin Small Outline Integrated Circuit (SOIC) Commercial, 0 to 70°C CY25100SXIF 8-Pin Small Outline Integrated Circuit (SOIC) Industrial, –40 to 85°C CY25100ZXCF 8-Pin Thin Shrunk Small Outline Package (TSSOP) Commercial, 0 to 70°C CY25100ZXIF 8-Pin Thin Shrunk Small Outline Package (TSSOP) Industrial, –40 to 85°C CY25100SXC-xxxw[7] 8-Pin Small Outline Integrated Circuit (SOIC) Commercial, 0 to 70°C CY25100SXC-xxxwT[7] 8-Pin Small Outline Integrated Circuit (SOIC) - Tape and Reel Commercial, 0 to 70°C CY25100SXI-xxxw 8-Pin Small Outline Integrated Circuit (SOIC) Industrial, –40 to 85°C CY25100SXI-xxxwT[7] 8-Pin Small Outline Integrated Circuit (SOIC) -Tape and Reel Industrial, –40 to 85°C CY25100ZXC-xxxw[7] 8-Pin Thin Shrunk Small Outline Package (TSSOP) Commercial, 0 to 70°C CY25100ZXC-xxxwT[7] 8-Pin Thin Shrunk Small Outline Package (TSSOP) - Tape and Reel Commercial, 0 to 70°C CY25100ZXI-xxxw[7] 8-Pin Thin Shrunk Small Outline Package (TSSOP) Industrial, –40 to 85°C CY25100ZXI-xxxwT[7] 8-Pin Thin Shrunk Small Outline Package (TSSOP) -Tape and Reel Industrial, –40 to 85°C [7] CY3672-USB FTG Programmer, for part numbers ending in “F” n/a CY3690 CY25100ZXCF/IF Socket Adapter (TSSOP) for use with CY3672-USB n/a CY3691 CY25100SXCF/IF Socket Adapter (SOIC) for use with CY3672-USB n/a Package Diagrams Figure 6. 8-Pin (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Notes 7. “xxx” denotes the assigned product dash number. “w” denotes the different programmed frequency and spread percentage options. 8. Not recommended for new designs. Document #: 38-07499 Rev. *F Page 10 of 13 [+] Feedback CY25100 Package Diagrams (continued) Figure 7. 8-Pin Thin Shrunk Small Outline Package (4.40 mm Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] 2.90[0.114] 3.10[0.122] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document #: 38-07499 Rev. *F Page 11 of 13 [+] Feedback CY25100 Document History Page Document Title: CY25100 Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07499 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 126578 CKN 06/27/03 New Data Sheet *A 128753 IJATMP 08/29/03 Changes to reflect field programmability *B 130342 RGL 12/02/03 Changes to Application Circuit diagram and correction to the package description listed under the Ordering Information table for CY3690 and CY3691. *C 204121 RGL See ECN Add Industrial Temperature Range Corrected the Ordering Information to match the DevMaster *D 215392 RGL See ECN Added Lead Free devices *E 2513909 AESA 06/10/08 Updated template. Added Note “Not recommended for new designs.” Added part number CY25100KSXCF, CY25100KSXIF, CY25100KSXI-xxx, CY25100KZXC-xxx, CY25100KZXI-xxx, CY25100KSXI-xxxT, CY25100KZXC-xxxT, CY25100KZXI-xxxT, and CY25100KZXIF in ordering information table. Added Pb-Free header in the ordering information table. Removed Pb-Free from Package description in the ordering information table. Changed CY3672-PRG with CY3672-USB in the ordering information table. Removed CY25100SCF, CY25100SIF, CY25100ZCF, CY25100ZIF, and CY3672 in the ordering information table. Changed Lead free to Pb-Free. *F 2601881 KVM/PYRS 11/06/08 Rising edge slew rate (SR3) minimum limit changed from 1.2V/ns to 1.0V/ns. Removed part numbers added in rev *E. Document #: 38-07499 Rev. *F Page 12 of 13 [+] Feedback CY25100 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07499 Rev. *F Revised November 4, 2008 Page 13 of 13 CyberClocks is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback