Preliminary K6F2016R4G Family CMOS SRAM 2Mb(128K x 16 bit) Low Power SRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM Document Title 128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft Draft Date Remark April 25, 2005 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -2- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM 128K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION • • • • • • The K6F2016R4G families are fabricated by SAMSUNG′s advanced full CMOS process technology. The families support industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The family also supports low data retention voltage for battery back-up operation with low data retention current. Process Technology: Full CMOS Organization: 128K x16 bit Power Supply Voltage: 1.65~1.95V Low Data Retention Voltage: 1.0V(Min) Three State Outputs Package Type: 48-FBGA-6.00x7.00 PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) Operating (ICC1, Max) PKG Type K6F2016R4G-F Industrial(-40~85°C) 1.65~1.95V 701)/85ns 0.5µA2) 2mA 48-FBGA-6.00x7.00 1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=1.8V, TA=25°C and not 100% tested. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM 1 2 3 4 5 6 LB OE A0 A1 A2 DNU Clk gen. A Precharge circuit. Vcc Vss B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 DNU A7 I/O4 Vcc E Vcc I/O13 DNU A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 DNU A12 A13 WE I/O8 Row Addresses Row select Data cont I/O1~I/O8 Memory Cell Array I/O Circuit Column select Data cont I/O9~I/O16 Data cont Column Addresses H DNU A8 A9 A10 A11 DNU 48-FBGA: Top View (Ball Down) CS OE Name Function Name Function WE CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) Address Inputs LB Lower Byte(I/O1~8) A0~A16 I/O1~I/O16 Data Inputs/Outputs DNU Control Logic UB LB Do Not Use SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -3- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM PRODUCT LIST Industrial Temperature Products(-40~85°C) Part Name Function 48-FBGA, 70ns, 1.8V 48-FBGA, 70ns, 1.8V, LF1) 48-FBGA, 85ns, 1.8V 48-FBGA, 85ns, 1.8V, LF1) K6F2016R4G-FF70 K6F2016R4G-XF70 K6F2016R4G-FF85 K6F2016R4G-XF85 1. LF : Lead Free Product FUNCTIONAL DESCRIPTION CS OE WE LB UB 1) 1) I/O1~8 I/O9~16 Mode Power H X High-Z High-Z Deselected Standby X1) X1) X1) H H High-Z High-Z Deselected Standby L H H L X1) High-Z High-Z Output Disabled Active L H H X1) L High-Z High-Z Output Disabled Active 1) X 1) X X L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X 1) L L H Din High-Z Lower Byte Write Active L X1) L H L High-Z Din Upper Byte Write Active L 1) L L L Din Din Word Write Active X 1. X means don′t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.3V(Max. 2.6V) V Voltage on Vcc supply relative to Vss VCC -0.2 to 2.6 V Power Dissipation PD 1.0 W TSTG -65 to 150 °C TA -40 to 85 °C Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -4- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 1.65 1.8 1.95 V Ground Vss 0 0 0 V Input high voltage VIH 1.4 - Vcc+0.22) V Input low voltage VIL - 0.4 V -0.2 3) Note: 1. Industrial Product: TA=-40 to 85°C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns. 3. Undershoot: -1.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Test Conditions Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc -1 - 1 µA ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V, LB≤0.2V or/and UB≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 2 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, LB=VIL or/and UB=VIL, VIN=VIL or VIH 85ns - - 12 70ns - - 15 Symbol Average operating current Min Typ1) mA Output low voltage VOL IOL = 0.1mA - - 0.2 V Output high voltage VOH IOH = -0.1mA 1.4 - - V Standby Current (CMOS) ISB1 Other input =0~Vcc 1) CS≥Vcc-0.2V(CS controlled) or 2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled) - 0.5 8 µA 1. Typical value are measured at VCC=1.8V, TA=25°C and not 100% tested. -5- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM VTM3) AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) R12) Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 5ns Input and output reference voltage:0.9V Output load (See right): CL= 30pF+1TTL CL1) R22) 1. Including scope and jig capacitance 2. R1=3070Ω, R2=3150Ω 3. VTM =1.8V AC CHARACTERISTICS ( TA=-40 to 85°C, Vcc=1.65~1.95V ) Speed Bins Parameter List Symbol 70ns Min Read Write Units 85ns Max Min Max Read cycle time tRC 70 - 85 - ns Address access time tAA - 70 - 85 ns Chip select to output tCO - 70 - 85 ns Output enable to valid output tOE - 35 - 40 ns UB, LB Access Time tBA - 70 - 85 ns Chip select to low-Z output tLZ 10 - 10 - ns UB, LB enable to low-Z output tBLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 ns UB, LB disable to high-Z output tBHZ 0 25 0 25 ns Output disable to high-Z output tOHZ 0 25 0 25 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 70 - 85 - ns Chip select to end of write tCW 60 - 70 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 60 - 70 - ns UB, LB Valid to End of Write tBW 60 - 70 - ns Write pulse width tWP 50 - 60 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 30 - 35 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V , VIN≥0V Data retention current IDR Vcc=1.2V, CS≥Vcc-0.2V , VIN≥0V Data retention set-up time tSDR Recovery time tRDR 1) 1) See data retention waveform Min Typ Max Unit 1.0 - 1.95 V 3 µA - 0.5 0 - - tRC - - 2) ns 1. 1) CS≥Vcc-0.2V(CS controlled) or 2) LB=UB≥Vcc-0.2V, CS≤0.2V(LB/UB controlled) 2. Typical value are measured at TA=25°C and not 100% tested. -6- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. -7- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z -8- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS or LB/UB controlled VCC tSDR Data Retention Mode tRDR 1.65V 1.4V VDR CS≥VCC-0.2V or LB=UB≥Vcc-0.2V CS or LB/UB GND -9- Revision 0.0 April 2005 Preliminary K6F2016R4G Family CMOS SRAM PACKAGE DIMENSION Unit: millimeters 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B B1 B 6 5 4 3 2 1 A B #A1 C C C C1 D C1/2 E F G H B/2 Detail A Side View A C Min Typ Y 0.58/Typ. E 0.32/Typ. E1 D Max A - 0.75 - B 5.90 6.00 6.10 1. Bump counts: 48(8 row x 6 column) B1 - 3.75 - 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) C 6.90 7.00 7.10 C1 - 5.25 - D 0.40 0.45 0.50 E - E1 0.25 Y - Notes. 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.10(Max) 1.00 - 0.10 - 10 - Revision 0.0 April 2005