Fairchild FT10001 Reset timer with fixed delay and reset pulse Datasheet

FT10001
Reset Timer with Fixed Delay and Reset Pulse
Features
Description
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The FT10001 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. It has a fixed delay of 10 ±20% seconds. The
DSR pin enables Test Mode operation by immediately
forcing /RST1 LOW for factory testing.
Fixed Reset Delay: 10 Seconds
One Input Reset Pin
Open-Drain Output Pin with Fixed 530ms Pulse
1.8V to 5.0V Operation (TA=-40°C to +85°C)
1.7V to 5.0V Operation (TA=-25°C to +85°C)
1.65V to 5.00V Operation (TA=0°C to +85°C)
<1µA ICCQ Consumption
Zero-Second Test-Mode Enable
The FT10001 has one input for single-button resetting
capability. The device has a single open-drain output
with 0.5mA pull-down drive.
FT10001 draws minimal ICC current when inactive and
functions over a power supply range of 1.65V to 5.00V.
Integrated Pull-Up Resistor on /SRO
Applications
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Cell Phones
Portable Media Players
Tablets
Mobile Devices
Consumer Medical
Ordering Information
Packing
Method
Part Number
Operating
Temperature Range
FT10001L6X
-40C to +85C
6-Lead, MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
5000 Units on
Tape and Reel
FT10001FHX
-40C to +85C
6-Lead, MicroPak2™ 1.0 x 1.0mm Body, .35mm Pitch
5000 Units on
Tape and Reel
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev. 1.0.1
Package
www.fairchildsemi.com
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
January 2012
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Block Diagram
Figure 1.
Block Diagram
Pin Configuration
Figure 2.
Pad Assignments (Top-Through View)
Pin Definitions
Pin #
Name
1
/RST1
2
Description
Normal Operation
Zero-Second Factory-Test Mode
Open-drain output, active LOW
Open-drain output, active LOW
GND
GND
GND
3
/SR0
Reset input with integrated pull-up, active LOW Reset input with integrated pull-up, active LOW
4
VCC
Power supply
5
DSR
Delay selection input; tie to GND during normal Delay selection input. Pull HIGH to enable Zerooperation.(1)
second delay for factory test.
6
TEST
Used for device testing; tie to GND during
normal operation.
Power supply
Used for device testing; tie to GND during normal
operation.
Note:
1. This pin must always be tied to either GND or VCC. It must not float.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
VIN
DC Input Voltage
VOUT
Min.
Max.
Unit
-0.5
7.0
V
/SR0, DSR
-0.5
7.0
V
/RST1
-0.5
7.0
V
IIK
DC Input Diode Current
VIN < 0V
-50
mA
IOK
DC Output Diode Current
VOUT < 0V
-50
mA
IOL
DC Output Sink Current
+50
mA
ICC
DC VCC or Ground Current per Supply Pin
100
mA
+150
C
TSTG
Output Voltage
(2)
Condition
Storage Temperature Range
-65
TJ
Junction Temperature Under Bias
+150
C
TL
Junction Lead Temperature, Soldering 10 Seconds
+260
C
PD
Power Dissipation
5
mW
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22-A114
4
Charged Device Model, JESD22-C101
2
kV
Note:
2. All output current Absolute Maximum Ratings must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Supply Voltage
Condition
Min.
Max.
-40C to +85C
1.8
5.0
-25C to +85C
1.7
5.0
0C to +85C
1.65
5.00
Unit
V
tRFC
VCC Recovery Time After Power Down
VCC=0V After Power Down,
Rising to 0.5V
5
VIN
Input Voltage
/SR0
0
5
V
Output Voltage
/RST1
0
5
V
IOL
DC Output Sink Current
/RST1, VCC=2.0V to 5.0V
+0.5
mA
TA
Free-Air Operating Temperature
+85
C
JA
Thermal Resistance
350
°C/W
VOUT
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
-40
ms
www.fairchildsemi.com
3
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Absolute Maximum Ratings
Conditions of TA=-40°C to 80°C with VCC=1.8V - 5.0V OR TA=-25°C to 85°C with VCC=1.7V – 5.0V OR TA=0°C to
85°C with VCC=1.65V – 5.00V produce the performance characteristics below.
Symbol
Parameter
Condition
VIH
Input High Voltage
DSR, /SR0
VIL
Input Low Voltage
DSR, /SR0
VOL
Low Level Output Voltage
RST, IOL=500µA
RPU
Integrated Pull-Up Resistor on /SR0
IIN
ICC
Min.
Typ.
Max.
0.65 x VCC
Unit
V
0.25 x
VCC
0.3
50
V
kΩ
Input Leakage Current /SR0
VIN= VCC
1
Input Leakage Current DSR
0V  VIN  5.0V
1
Quiescent Supply Current
(Timer Inactive)
/SR0=VCC
1
Dynamic Supply Current (Timer Active) /SR0=0V
V
µA
µA
200
AC Electrical Characteristics
Conditions of TA=-40°C to 80°C with VCC=1.8V - 5.0V OR TA=-25°C to 85°C with VCC=1.7V – 5.0V OR TA=0°C to
85°C with VCC=1.65V – 5.00V produce the performance characteristics below.
Symbol
Parameter
tPHL1
Timer Delay, /SR0 to RST (DSR=0)
tREC
Reset Timeout Delay
Condition
CL=5pF, RL=5K,
See Figure 4
Min.
Typ.
Max.
Unit
8
10
12
s
420
530
635
ms
Typ.
Unit
Capacitance Specifications
TA=+25C.
Symbol
CIN
COUT
Parameter
Condition
Input Capacitance
VCC=GND
4
pF
Output Capacitance
VCC=5.0V
5
pF
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
4
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
DC Electrical Characteristics
Default operation time N is 10s. If the DSR pin is pulled
HIGH prior to VCC ramp, the FT10001 enters Test Mode
and the reset output, /RST1, is immediately pulled LOW
for factory testing. The DSR pin MUST be forced to
GND during normal operation. The DSR pin should
never be driven HIGH or left to FLOAT during normal
operation. The DSR PIN state should never be changed
during device operation; it must be biased prior to
supplying the VCC supply. If there is a need to use the
DSR=VCC Test Mode, the /SR0 must be HIGH when
the DSR pin is moved from LOW to HIGH to enter ZeroSecond Factory-Test Mode. To return to the standard
10-second reset time, the same procedure must be
followed with DSR=GND. The DSR pin should never be
allowed to change state while the /SR0 pin is LOW.
state 530ms after time tREC has expired, regardless of
the state of /SR0. The /RST1 output is an open-drain
driver. When the count time exceeds time 10s, the
/RST1 output pulls LOW.
Short Duration (tW < 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input goes HIGH before 10s has
elapsed, the timer stops counting and resets and no
changes occur on the outputs.
Long Duration (tW > 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input stays LOW for at least 10s, the
RST output is enabled and pulled LOW. The output RST
is held LOW for tREC, 530ms, as soon as the reset time
of 10s is met, regardless of the state of the /SR0 pin.
When the /SR0 input has returned HIGH and tREC has
expired, the internal timer resets and awaits the next
RESET event.
Operation Modes
A low input signal on /SR0 starts the oscillator. There
are two scenarios for counting: short duration and long
duration. In the short-duration scenario, output /RST1 is
not affected. In the long-duration scenario, the output
/RST1 goes LOW after /SR0 has been held LOW for
10s. The /RST1 output returns to its original HIGH
Zero-Second Test Mode
/RST1 goes LOW immediately after /SR0 goes LOW.
N=7.5s
Short-Duration,
Normal Operation
/RST1 never goes LOW because
/SR0 LOW duration does not meet
requirement: Reset Time N=10s
/SR0
RST1
Long-Duration,
Normal Operation
/RST1 goes LOW because
/SR0 LOW duration exceeds
requirement: Reset Time N=10s
/SR0
RST1
tREC=530ms
/SR0
Zero-Second Factory-Test Mode
/RST1 goes LOW immediately
after /SR0 goes LOW
RST1
tREC=530ms
Figure 3.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
Reset Timing Waveforms
www.fairchildsemi.com
5
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Functional Description
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
AC Test Circuit and Waveforms
Figure 4.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
AC Test Circuit and Waveforms for /RST1 Output ST Output
www.fairchildsemi.com
6
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
(0.13)
4X
BOTTOM VIEW
Notes:
0.075 X 45
CHAMFER
DETAIL A
PIN 1 TERMINAL
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 5.
6-Lead MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
7
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Physical Dimensions
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.55MAX
C
0.35
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
0.35
6
5
4
BOTTOM VIEW
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 6.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead MicroPak2™ 1.0 x 1.0mm, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
8
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Physical Dimensions
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
9
Rev 0.0
8/1/11
Sean Ryan
Initial Rev – created from FT7521 datasheet
Rev 0.1
8/11/11
Sean Ryan
Updated the tREC to align with reset time of 10sec.
Rev 0.2
8/24/11
Alvan Lam
Added micropak2 information and marketing drawing
Rev 0.3
8/25/11
Alvan Lam
Updated the NMOS symbol in block diagram
Rev 0.4
9/6/11
Alvan Lam
Created revision table instead of using Hidden Text
Rev 1.0.0
12/6/11
Alvan Lam
Changed ABS Max to 7V, initial datasheet released by
Techdoc
Rev 1.0.1
12/14/11
Alvan Lam
Added 1.7/-25C condition to align FT7521 datasheet
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
10
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
Revisions
FT10001 — Reset Timer with Fixed Delay and Reset Pulse
© 2011 Fairchild Semiconductor Corporation
FT10001 • Rev 1.0.1
www.fairchildsemi.com
11