TI1 ISO7220BDRG4 Dual channel digital isolator Datasheet

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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
ISO722x Dual Channel Digital Isolators
1 Features
•
1
•
•
•
•
•
•
•
•
•
1, 5, 25, and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1-ns Max
– Low Pulse-Width Distortion (PWD); 1-ns Max
– Low Jitter Content; 1 ns Typ at 150 Mbps
50 kV/μs Typical Transient Immunity
Operates with 2.8-V (C-Grade),
3.3-V, or 5-V Supplies
4-kV ESD Protection
High Electromagnetic Immunity
–40°C to 125°C Operating Range
Typical 28-Year Life at Rated Voltage
(see application report High-Voltage Lifetime of
the ISO72x Family of Digital Isolators (SLLA197)
and Figure 22)
VDE Basic Insulation with 4000-VPK VIOTM, 560
VPK VIORM per DIN V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN EN 61010-1 (VDE
0411-1)
2500 VRMS Isolation per UL 1577
CSA Approved for Component Acceptance Notice
5A and IEC 60950-1
2 Applications
•
•
•
•
Industrial Fieldbus
– Modbus
– Profibus™
– DeviceNet™ Data Buses
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
A binary input signal is conditioned, translated to a
balanced signal, then differentiated by the capacitive
isolation barrier. Across the isolation barrier, a
differential comparator receives the logic transition
information, then sets or resets a flip-flop and the
output circuit accordingly. A periodic update pulse is
sent across the barrier to ensure the proper dc level
of the output. If this dc-refresh pulse is not received
every 4 μs, the input is assumed to be unpowered or
not being actively driven, and the failsafe circuit
drives the output to a logic high state.
The small capacitance and resulting time constant
provide fast operation with signaling rates available
from 0 Mbps (DC) to 150 Mbps (The signaling rate of
a line is the number of voltage transitions that are
made per second expressed in the units bps). The Aoption, B-option, and C-option devices have TTL
input thresholds and a noise filter at the input that
prevents transient pulses from being passed to the
output of the device. The M-option devices have
CMOS VCC/2 input thresholds and do not have the
input noise filter and the additional propagation delay.
The ISO7220x and ISO7221x devices require two
supply voltages of 2.8 V (C-Grade), 3.3 V, 5 V, or any
combination. All inputs are 5-V tolerant when supplied
from a 2.8-V or 3.3-V supply and all outputs are 4-mA
CMOS.
The ISO7220x and ISO7221x devices are
characterized for operation over the ambient
temperature range of –40°C to 125°C.
Device Information(1)
PART NUMBER
ISO7220x
SOIC (8)
ISO7221x
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The ISO7220x and ISO7221x devices are dualchannel digital isolators. To facilitate PCB layout, the
channels are oriented in the same direction in the
ISO7220x and in opposite directions in the ISO7221x.
These devices have a logic input and output buffer
separated by TI’s silicon-dioxide (SiO2) isolation
barrier, providing galvanic isolation of up to 4000 VPK
per VDE. Used in conjunction with isolated power
supplies, these devices block high voltage and isolate
grounds, as well as prevent noise currents on a data
bus or other circuits from entering the local ground
and interfering with or damaging sensitive circuitry.
PACKAGE
Simplified Schematic
VCCO
VCCI
Isolation
Capacitor
INx
OUTx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
1
1
1
2
5
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics, 5 V ................................... 7
Electrical Characteristics, 5 V, 3.3 V ........................ 8
Electrical Characteristics: 3.3 V, 5 V......................... 9
Electrical Characteristics, 3.3 V .............................. 10
Electrical Characteristics, 2.8 V ............................. 10
Dissipation Characteristics.................................... 11
Switching Characteristics, 5 V ............................. 11
Switching Characteristics, 5 V, 3.3 V.................... 12
Switching Characteristics, 3.3 V, 5 V ................... 12
Switching Characteristics, 3.3 V ........................... 13
Switching Characteristics, 2.8 V .......................... 14
Typical Characteristics .......................................... 15
7
8
Parameter Measurement Information ................ 17
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (October 2014) to Revision N
Page
•
Changed the VDE Cerification from: DIN EN 60747-5-5 (VDE 0884-5) to: DIN V VDE V 0884-10 (VDE V 088410):2006-12 throughout the document ................................................................................................................................... 1
•
Updated the Simplified Schematic to a higher quality version. .............................................................................................. 1
•
Changed the max value of the IN and OUT voltage from 6 to VCC + 0.5 in the Absolute Maximum Ratings table............... 5
•
Added = 150°C to insulation resistance test condition in the DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics table. ........................................................................................................................................... 19
•
Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table. ........................................................... 19
•
Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table. ........................................................... 19
•
Added the JEDEC package dimensions note in the IEC Package Characteristics table..................................................... 19
•
Changed the DTI test condition From: IEC 60112 / VDE 0303 Part 1 To: DIN EN 60112 (VDE 0303-11); IEC 60112 ...... 20
•
Added the DTI parameter to the IEC Package Characteristics table. .................................................................................. 20
•
Added table row with input side VCC = X to the ISO7220x or ISO7221x Function table...................................................... 21
Changes from Revision L (January 2012) to Revision M
Page
•
Changed the title of this data sheet to ISO722x Dual Channel Digital Isolators ................................................................... 1
•
Added Pin Configuration and Functions section, Handling Rating table, Dissipation Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section, changed Thermal Information table ........................................................... 1
•
Updated the Features section ............................................................................................................................................... 1
•
Added per VDE to 4000 VPK in second sentence of Description .......................................................................................... 1
•
Updated the Regulatory Information Table............................................................................................................................. 5
2
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Product Folder Links: ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
•
Added the min and max values to the Storage temperature parameter in the Absolute Maximum Ratings table. ............... 5
•
Changed in ROC table Max col, VIH row from VCC to 5.5 .................................................................................................... 6
•
Changed the Device Options table, Input Threshold column from ≠ symbol to ~ symbol 6 places .................................... 19
•
Changed the 7.4 title from IEC 60747 ~2 Insulation Characteristics to DIN EN ~ 5 Insulation Characteristics ................. 19
•
Changed Isolation Glossary ................................................................................................................................................ 25
Changes from Revision K (January 2010) to Revision L
Page
•
Changed Feature From: Operates with 3.3-V or 5-V Supplies To: Operates with 2.8-V (C-Grade), 3.3-V or 5-V Supplies . 1
•
Changed Feature From: 4000-Vpeak Isolation, 560 Vpeak VIORM To: 4000-VPK VIOTM, 560 VPK VIORM per IEC 60747-5-2
(VDE 0884, Rev2) ................................................................................................................................................................. 1
•
Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table ................................................... 6
•
Changed Note: (1) in the RECOMMENDED OPERATING CONDITIONS table ................................................................... 6
•
Changed ICC1 and ICC2 test conditions in the 5-V table........................................................................................................... 7
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 5 V, VCC2 at 3.3 V table........................................................................ 8
•
Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3 V, VCC2 at 5 V table........................................................................ 9
•
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table .......................................................................... 10
•
Changed Table Note (1) ....................................................................................................................................................... 10
•
Added ELECTRICAL and Switching CHARACTERISTICS table for VCC1 and VCC2 at 2.8 V (ISO722xC-Only) ................. 10
•
Changed Figure 9................................................................................................................................................................. 15
•
Changed Figure 14............................................................................................................................................................... 17
•
Changed the CTI MIN value From: ≥175 V To: ≥400 V ....................................................................................................... 20
•
Updated the Regulatory Information table............................................................................................................................ 20
Changes from Revision J (May 2009) to Revision K
Page
•
Changed the RECOMMENDED OPERATING CONDITIONS so that Note (2) is associated with all device options in
the Input pulse width and Signaling rate ................................................................................................................................ 6
•
Changed Note (2) From: Typical signaling rate under ideal conditions at 25°C. To: Typical signaling rate and Input
pulse width are measured at ideal conditions at 25°C. .......................................................................................................... 6
•
Changed column 2 of the AVAILABLE OPTIONS table From: Signaling Rate To: Max Signaling Rate ............................. 19
Changes from Revision I (December 2008) to Revision J
•
Page
Changed ISO7221C Marked As column From: TI7221C To: I7221C in the AVAILABLE OPTIONS table ......................... 19
Changes from Revision H (May 2008) to Revision I
•
Page
Added "IEC 61010-1, IEC 60950-1 and CSA Approved" to the UL 1577 FEATURES bullet ................................................ 1
Changes from Revision G (March 2008) to Revision H
Page
•
Added Note: (1) to the RECOMMENDED OPERATING CONDITIONS table ....................................................................... 6
•
Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V.......................................................... 10
Copyright © 2006–2015, Texas Instruments Incorporated
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3
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
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Changes from Revision F (August 2007) to Revision G
Page
•
Added Part Numbers ISO7220B and ISO7221B to the data sheet........................................................................................ 1
•
Added 5-Mbps Signaling rate to the FEATURES list ............................................................................................................. 1
•
Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table ... 7
•
Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3
V table..................................................................................................................................................................................... 8
•
Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5
V table..................................................................................................................................................................................... 9
•
Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V ....... 10
•
Added PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB, Figure 4 ...................................................... 15
•
Added Part Numbers ISO7220B and ISO7221B to the AVAILABLE OPTIONS table......................................................... 19
Changes from Revision E (July 2007) to Revision F
Page
•
Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ....................... 11
•
Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table......................... 11
•
Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table................ 12
•
Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................. 12
•
Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION table................ 12
•
Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION table ................. 13
•
Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS table................................................................................. 13
•
Added tsk(o) footnote to the SWITCHING CHARACTERISTICS table .................................................................................. 13
•
Changed Figure 1 - Re-scaled the Y-axis ............................................................................................................................ 15
•
Changed Figure 2 - New Curves.......................................................................................................................................... 15
Changes from Revision D (June 2007) to Revision E
Page
•
Changed Figure 1 - New Curves.......................................................................................................................................... 15
•
Changed Figure 2- Re-scaled the Y-axis ............................................................................................................................ 15
Changes from Revision C (May 2007) to Revision D
•
Page
Changed Figure 20 - Pin 2 (INA) label From: OUTPUT to INPUT....................................................................................... 23
Changes from Revision B (May 2007) to Revision C
Page
•
Added the Signaling rate values to the RECOMMENDED OPERATING CONDITIONS table.............................................. 6
•
Added Figure 12 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table.. 11
•
Added Figure 12 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table.. 12
•
Added Figure 12 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table.. 13
•
Added Figure 12 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table.. 13
•
Changed the IEC 60664-1 RATINGS TABLE - Specification I-III test conditions From: Rated mains voltage ≤150
VRMS To: Rated mains voltage ≤300 VRMS. Added a row for the I-II specifications......................................................... 20
•
Added Figure 22 - Time Dependent Dielectric Breakdown Test Results ............................................................................. 23
4
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
Changes from Revision A (August 2006) to Revision B
Page
•
Added the TYPICAL CHARACTERISTIC CURVES to the data sheet. ............................................................................... 15
•
Added the PARAMETER MEASUREMENT INFORMATION to the data sheet .................................................................. 17
•
Added the ELECTRICAL CHARACTERISTICS tables to the data sheet ............................................................................ 20
•
Added the APPLICATION INFORMATION section to the data sheet.................................................................................. 22
•
Added the ISOLATION GLOSSARY section to the data sheet ........................................................................................... 25
Changes from Original (July 2006) to Revision A
Page
•
Deleted "and CSA Apporved" from the UL 1577 FEATURES bullet...................................................................................... 1
•
Added option A to the AVAILABLE OPTIONS table ............................................................................................................ 19
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
Pin Configuration and Functions
ISO7220x D Package
8-Pin SOIC
Top View
INA 2
INB 3
8 VCC2
ISOLATION
VCC1 1
ISO7221x D Package
8-Pin SOIC
Top View
GND1 4
VCC1 1
7 OUTA
OUTA 2
6 OUTB
INB 3
5 GND2
GND1 4
8 VCC2
ISOLATION
5
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7 INA
6 OUTB
5 GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
ISO7220x
ISO7221x
INA
2
7
I
Input, channel A
INB
3
3
I
Input, channel B
GND1
4
4
—
Ground connection for VCC1
GND2
5
5
—
Ground connection for VCC2
OUTA
7
2
O
Output, channel A
OUTB
6
6
O
Output, channel B
VCC1
1
1
—
Power supply, VCC1
VCC2
8
8
—
Power supply, VCC2
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5
6
V
VI
Voltage at IN, OUT
–0.5
VCC + 0.5 (3)
V
IO
Output current
–15
15
mA
TJ
Maximum junction temperature
170
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These ratings are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground pin and are peak voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
6
Electrostatic discharge
(1)
VALUE
UNIT
±4000
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1000
V
Machine Model, ANSI/ESDS5.2-1996
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
6.3 Recommended Operating Conditions
MIN
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
ISO722xA, ISO722xB, ISO722xM
ISO722xC
5.5
2.8
5.5
4
(2)
0.67
ISO722xB
200
100
ISO722xC
40
33
ISO722xM
6.67
5
ISO722xA
0
1500
1000
ISO722xB
0
10
5
ISO722xC
0
30
25
ISO722xM
0
200
150
High-level input voltage
Low-level input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification
(1)
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V.
Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C.
ISO722xA, ISO722xB, ISO722xC
ISO722xM
V
mA
μs
1
VIL
UNIT
mA
ISO722xA
VIH
(2)
MAX
–4
Signaling rate (2)
1/tui
NOM
3
ns
kbps
Mbps
2
5.5
V
0
0.8
V
0.7 VCC
VCC
V
0
0.3 VCC
V
–40
150
°C
1000
A/m
6.4 Thermal Information
THERMAL METRIC (1)
ISO7220x
ISO7221x
D (SOIC)
UNIT
8 PINS
Low-K Thermal Resistance (2)
212
High-K Thermal Resistance
122
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
69.1
°C/W
RθJB
Junction-to-board thermal resistance
47.7
°C/W
ψJT
Junction-to-top characterization parameter
15.2
°C/W
ψJB
Junction-to-board characterization parameter
47.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
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6.5 Electrical Characteristics, 5 V
VCC1 and V CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7220x
ISO7221
ICC1
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
ISO7221x
ICC2
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
VOH
High-level output voltage
VOL
Low-level output voltage
Quiescent
VI = VCC or 0 V, no load
1 Mbps
0.5 MHz Input Clock Signal, no load
25 Mbps
12.5 MHz Input Clock Signal, no
load
Quiescent
VI = VCC or 0 V, no load
1 Mbps
0.5 MHz Input Clock Signal, no load
25 Mbps
12.5 MHz Input Clock Signal, no
load
2
3
10
18
4
9
12
22
16
31
8.5
17
17
32
10
18
20
34
12
22
VCC – 0.8
4.6
IOH = –20 μA, See Figure 13
VCC – 0.1
5
0.2
0.4
IOL = 20 μA, See Figure 13
0
0.1
150
High-level input current
IN from 0 V to VCC
IIL
Low-level input current
IN from 0 V to VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 15
mA
mA
mA
mA
mA
V
mV
10
μA
μA
–10
25
mA
V
IOL = 4 mA, See Figure 13
IIH
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2
17
IOH = –4 mA, See Figure 13
VI(HYS) Input voltage hysteresis
8
1
8.5
1
pF
50
kV/μs
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
6.6 Electrical Characteristics, 5 V, 3.3 V
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7220x
ISO7221x
ICC1
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
ISO7221x
ICC2
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
High-level output voltage
1 Mbps
0.5 MHz Input Clock Signal, no
load
2
3
10
18
25 Mbps
12.5 MHz Input Clock Signal,
no load
4
9
12
22
Quiescent
VI = VCC or 0 V, no load
1 Mbps
0.5 MHz Input Clock Signal, no
load
25 Mbps
12.5 MHz Input Clock Signal,
no load
IOH = –4 mA, See Figure 13
ISO7221x (5-V side)
All devices
8
18
4.3
9.5
9
19
5
11
10
20
6
12
IOH = –20 μA, See Figure 13
0.4
0.1
Input voltage hysteresis
IIH
High-level input current
IN from 0 V to VCC
IIL
Low-level input current
IN from 0 V to VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 15
mA
mA
mA
mA
VCC – 0.1
IOL = 20 μA, See Figure 13
VI(HYS)
mA
V
IOL = 4 mA, See Figure 13
Low-level output voltage
mA
VCC – 0.4
VCC – 0.8
VOL
Copyright © 2006–2015, Texas Instruments Incorporated
2
17
VI = VCC or 0 V, no load
ISO7220x, ISO7221x
(3.3-V side)
VOH
1
8.5
Quiescent
150
mV
10
μA
μA
–10
15
V
1
pF
40
kV/μs
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
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6.7 Electrical Characteristics: 3.3 V, 5 V
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7220x
ISO7221x
ICC1
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
ISO7221x
ICC2
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
High-level output voltage
0.5 MHz Input Clock Signal, no
load
1
2
5
11
25 Mbps
12.5 MHz Input Clock Signal,
no load
2
4
6
12
Quiescent
VI = VCC or 0 V, no load
1 Mbps
25 Mbps
ISO7221x
(3.3-V side)
16
31
8.5
17
0.5 MHz Input Clock Signal, no
load
18
32
10
18
12.5 MHz Input Clock Signal,
no load
20
34
12
22
mA
mA
mA
mA
mA
mA
VCC – 0.8
IOH = –4 mA, See Figure 13
VCC – 0.4
V
IOH = –20 μA, See Figure 13
VCC – 0.1
IOL = 4 mA, See Figure 13
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN from 0 V or VCC
IIL
Low-level input current
IN from 0 V or VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 15
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9.5
1 Mbps
All devices
10
1
4.3
VI = VCC or 0 V, no load
ISO7220x,
ISO7221x (5-V side)
VOH
0.6
Quiescent
0.4
IOL = 20 μA, See Figure 13
0
0.1
150
mV
10
15
μA
μA
–10
1
pF
40
kV/μs
Copyright © 2006–2015, Texas Instruments Incorporated
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
6.8 Electrical Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7220x
ISO7221x
ISO7220A, ISO7220B
ICC1
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
ISO7221x
ISO7220A, ISO7220B
ICC2
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
Quiescent
VI = VCC or 0 V, no load
1 Mbps
0.5 MHz Input Clock Signal, no load
25 Mbps
12.5 MHz Input Clock Signal, no load
Quiescent
VI = VCC or 0 V, no load
1 Mbps
0.5 MHz Input Clock Signal, no load
25 Mbps
12.5 MHz Input Clock Signal, no load
1
4.3
9.5
1
2
5
11
2
4
6
12
8
18
4.3
9.5
9
19
5
11
10
20
6
12
IOH = –4 mA, See Figure 13
VCC – 0.4
3
IOH = –20 μA, See Figure 13
VCC – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN from 0 V or VCC
IIL
Low-level input current
IN from 0 V or VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 15
(1)
0.6
IOL = 4 mA, See Figure 13
IOL = 20 μA, See Figure 13
0.2
0.4
0
0.1
150
mA
mA
mA
mA
mA
V
mV
10
μA
μA
–10
15
mA
1
pF
40
kV/μs
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
6.9 Electrical Characteristics, 2.8 V
VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.) 2.8-V operation is only guaranteed
for ISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace Code (YMSLLLLG4)
written on top of each device can be used to identify year and month of production respectively.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
0.9
3.7
7.5
1.5
3.5
4.5
10
UNIT
SUPPLY CURRENT
ISO7220C
ICC1
ISO7221C
ISO7220C
ISO7221C
ISO7220C
ICC2
ISO7221C
ISO7220C
ISO7221C
VOH
Quiescent
VI = VCC or 0 V, no load
25 Mbps
12.5 MHz Input Clock Signal, no load
Quiescent
VI = VCC or 0 V, no load
25 Mbps
12.5 MHz Input Clock Signal, no load
High-level output voltage
IOH = –4 mA, See Figure 13
VCC – 0.6
IOH = –20 μA, See Figure 13
VCC – 0.1
IOL = 4 mA, See Figure 13
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IN from 0 V or VCC
IIL
Low-level input current
IN from 0 V or VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 15
Copyright © 2006–2015, Texas Instruments Incorporated
IOL = 20 μA, See Figure 13
6.8
15
3.7
7.5
9
17
4.5
10
mA
mA
mA
2.55
2.8
0.25
0.6
0
0.1
150
V
mV
10
μA
μA
–10
10
mA
1
pF
30
kV/μs
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
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6.10 Dissipation Characteristics
PARAMETER
PD
Device Power Dissipation
TEST CONDITIONS
ISO722xM
MIN
TYP MAX
UNIT
390
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 150 Mbps 50% duty cycle square wave
6.11 Switching Characteristics, 5 V
VCC1 and VCC2 at 5 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
TEST CONDITIONS
Propagation delay
(1)
PWD
Pulse-width distortion |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
(2)
ISO722xA
ISO722xB
See Figure 13
MIN
TYP
MAX
UNIT
280
405
475
ns
1
14
ns
42
55
70
ns
1
3
ns
32
42
ns
1
2
ns
10
16
ns
0.5
1
ns
22
ISO722xC
6
ISO722xM
ISO722xA
180
ISO722xB
17
ISO722xC
10
ISO722xM
tsk(o)
Channel-to-channel output skew
(3)
tr
Output signal rise time
tf
Output signal fall time
tfs
Failsafe output delay time from input power loss
Peak-to-peak eye-pattern jitter
tjit(pp)
(1)
(2)
(3)
12
3
ISO722xA
3
15
ISO722xB
0.6
3
ISO722xC,
ISO722xM
0.2
1
1
See Figure 13
ISO722xM
ns
ns
ns
1
ns
See Figure 14
3
μs
150 Mbps PRBS NRZ data, 5-bit max
same polarity input, both channels, See
Figure 16, Figure 12
1
150 Mbps unrestricted bit run length
data input, both channels, See Figure 16
2
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
6.12 Switching Characteristics, 5 V, 3.3 V
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10%(over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
ISO722xA
TYP
MAX
UNIT
285
410
480
ns
1
14
ns
58
75
ns
1
3
ns
36
48
ns
1
2
ns
12
20
ns
0.5
1
ns
45
ISO722xB
See Figure 13
25
ISO722xC
7
ISO722xM
(2)
MIN
ISO722xA
180
ISO722xB
17
ISO722xC
10
ISO722xM
tsk(o)
Channel-to-channel output skew
(3)
3
15
ISO722xB
0.6
3
ISO722xC,
ISO722xM
0.2
1
Output signal rise time
tf
Output signal fall time
tfs
Failsafe output delay time from input power loss
Peak-to-peak eye-pattern jitter
tjit(pp)
(1)
(2)
(3)
5
ISO722xA
tr
2
See Figure 13
ISO722xM
ns
ns
ns
2
ns
See Figure 14
3
μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 16,
Figure 12
1
150 Mbps unrestricted bit run length data
input, both channels, See Figure 16
2
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6.13 Switching Characteristics, 3.3 V, 5 V
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
(1)
(2)
Part-to-part skew
(2)
TEST CONDITIONS
ISO722xA
See Figure 13
ISO722xM
TYP
MAX
UNIT
285
395
480
ns
1
18
ns
58
75
ns
1
4
ns
36
48
ns
1
3
ns
12
21
ns
0.5
1
ns
45
ISO722xB
ISO722xC
MIN
25
7
ISO722xA
190
ISO722xB
17
ISO722xC
10
ISO722xM
5
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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Switching Characteristics, 3.3 V, 5 V (continued)
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tsk(o)
Channel-to-channel output skew
TEST CONDITIONS
(3)
TYP
MAX
ISO722xA
3
15
ISO722xB
0.6
3
ISO722xC,
ISO722xM
0.2
1
tr
Output signal rise time
tf
Output signal fall time
tfs
Failsafe output delay time from input power loss
Peak-to-peak eye-pattern jitter
tjit(pp)
(3)
MIN
1
See Figure 13
ISO722xM
UNIT
ns
ns
1
ns
See Figure 14
3
μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 16,
Figure 12
1
150 Mbps unrestricted bit run length data input,
both channels, See Figure 16
2
ns
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6.14 Switching Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew (2)
ISO722xA
MIN
TYP
MAX
UNIT
290
400
485
ns
1
18
ns
62
78
ns
1
4
ns
40
52
ns
1
3
ns
16
25
ns
0.5
1
ns
46
ISO722xB
See Figure 13
26
ISO722xC
8
ISO722xM
ISO722xA
190
ISO722xB
17
ISO722xC
10
ISO722xM
tsk(o)
Channel-to-channel output skew
(3)
3
15
ISO722xB
0.6
3
ISO722xC,
ISO722xM
0.2
1
Output signal rise time
tf
Output signal fall time
tfs
Failsafe output delay time from input power loss
Peak-to-peak eye-pattern jitter
tjit(pp)
(1)
(2)
(3)
14
5
ISO722xA
tr
2
See Figure 13
ISO722xM
ns
ns
ns
2
ns
See Figure 14
3
μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See
Figure 16, Figure 12
1
150 Mbps unrestricted bit run length data
input, both channels, See Figure 16
2
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Submit Documentation Feedback
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
6.15 Switching Characteristics, 2.8 V
VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew (2)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tfs
Failsafe output delay time from input power loss
(1)
(2)
(3)
ISO722xC
See Figure 13
MIN
TYP
MAX
26
45
65
ns
1.5
5
ns
12
ns
5
ns
ISO722xC
(3)
ISO722xC
0.2
See Figure 13
See Figure 14
2
UNIT
ns
2
ns
4.6
μs
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2006–2015, Texas Instruments Incorporated
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6.16 Typical Characteristics
20
30
TA = 25°C,
15 pF Load
18
26
16
ISO7220x ICC2
24
14
ICC - Supply Current - mA
ICC - Supply Current - mA
TA = 25°C,
15 pF Load
28
ISO7220x ICC2
12
10
ISO7221x ICC1&2
8
6
4
ISO7220x ICC1
22
20
ISO7221x ICC1&2
18
16
14
12
10
ISO7220x ICC1
8
6
4
2
2
0
0
0
25
50
75
100
Signaling Rate - Mbps
50
75
Signaling Rate - Mbps
Figure 1. 3.3-V RMS Supply Current vs Signaling Rate
(Mbps)
Figure 2. 5-V RMS Supply Current vs Signaling Rate
(Mbps)
450
25
100
70
TA = 25°C,
15 pF Load
15 pF Load
440
65
Propagation Delay - ns
430
Propagation Delay - ns
0
420
VCC = 3.3 V
tpLH & tpHL
410
400
VCC = 5 V
390
tpLH & tpHL
380
370
tPLH & tPHL
VCC = 3.3 V
60
VCC = 5 V
55
tPLH & tPHL
50
360
350
-40
-15
10
35
60
85
45
-40
110 125
25
Temperature - °C
Temperature - °C
Figure 3. Propagation Delay vs Free-Air Temperature,
ISO722xA
Figure 4. Propagation Delay vs Free-Air Temperature,
ISO722xB
30
20
VCC = 3.3 V
25
VCC = 3.3 V
tpLH & tpHL
15
Propagation Delay - ns
Propagation Delay - ns
125
20
15
tpLH & tpHL
VCC = 5 V
10
tpLH & tpHL
10
tpLH & tpHL
VCC = 5 V
5
5
0
-40
15 pF Load
-15
10
35
60
85
110 125
Temperature - °C
Figure 5. Propagation Delay vs Free-Air Temperature,
ISO722xC
16
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15 pF Load
0
-40
-15
10
35
60
85
110 125
Temperature - °C
Figure 6. Propagation Delay vs Free-Air Temperature,
ISO722xM
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SLLS755N – JULY 2006 – REVISED SEPTEMBER 2015
Typical Characteristics (continued)
2.5
1.4
2.4
5-V Vth+
1.35
5-V Vth+
1.3
Input Voltage Threshold - V
Input Voltage Threshold - V
2.3
3.3-V Vth+
1.25
15 pF Load
1.2
1.15
5-V Vth1.1
2.2
5-V Vth-
2.1
2
15 pF Load
1.9
1.8
3.3-V Vth+
1.7
1.6
1.05
1.5
3.3-V Vth-40 -25 -10
5
20
35
50
65
80
95
3.3-V Vth-
1.4
-40 -25 -10
1
110 125
5
20
35
50
65
80
95
110 125
Temperature - °C
Temperature - °C
Figure 7. ISO722xA, ISO722xB and ISO722xC Input Voltage
Low-to-High Switching Threshold vs Free-Air Temperature
Figure 8. ISO722xM Input Voltage High-to-Low
vs Free-Air Temperature
-80
15 pF Load
TA = 25°C
-70
2.64
-60
VCC = 5 V
VCC Rising
-50
2.6
IOUT - mA
Power Supply Undervoltage Threshold - V
2.68
2.56
-40
-30
VCC Falling
VCC = 3.3 V
-20
2.52
-10
2.48
-40 -25 -10
0
5
20
35
50
65
80
95
110 125
0
2
4
6
Free-Air Temperature - °C
VOUT - V
Figure 9. VCC Undervoltage Threshold vs Free-Air
Temperature
Figure 10. High-Level Output Current vs High-Level Output
Voltage
70
2000
15 pF Load
TA = 25°C
60
VCC = 5 V
1600
50
1400
1200
40
Jitter − ps
IOUT - mA
15 pF Load
TA = 25°C
1800
VCC = 3.3 V
30
VCC1 = VCC2 = 5 V
1000
800
600
20
VCC1 = VCC2 = 3.3 V
400
10
200
0
0
0
1
2
3
4
5
VOUT - V
Figure 11. Low-Level Output Current vs Low-Level Output
Voltage
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0
50
100
150
200
Signaling Rate - Mbps
Figure 12. ISO722xM Jitter vs Signaling Rate
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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ISOLATION BARRIER
7 Parameter Measurement Information
IN
Input
Generator
VI
50 W
NOTE A
VCC
VI
VCC/2
VCC/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 13. Switching Characteristic Test Circuit and Voltage Waveforms
VI
ISOLATION BARRIER
VCC
IN = 0 V
A.
VCC
OUT
VI
VO
2.7 V
0V
VOH
tfs
CL
NOTE A
VO
50%
FAILSAFE HIGH
VOL
CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 14. Failsafe Delay Time Test Circuit and Voltage Waveforms
IN
S1
C = 0.1 μ F ±1%
VCCO
Isolation Barrier
VCCI
GNDI
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
Note A
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 15. Common-Mode Transient Immunity Test Circuit
VCC
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps.
Figure 16. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
18
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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8 Detailed Description
8.1 Overview
The isolator in the Functional Block Diagram is based on a capacitive isolation barrier technique. The I/O channel
of the ISO7220x and ISO7221x devices consists of two internal data channels, a high-frequency channel (HF)
with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100
kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential
signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into
transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a
NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the
flip-flop measures the durations between signal transients. If the duration between two consecutive transients
exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to
switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Isolation Barrier
OSC
LPF
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
0
OUT
1 S
IN
DCL
High t Frequency
Channel
(100 kbps...150 Mbps)
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VREF
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8.3 Feature Description
PRODUCT
MAX SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
DIRECTION
ISO7220A
1 Mbps
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7220B
5 Mbps
≈ 1.5 V (TTL)
(CMOS compatible
ISO7220C
25 Mbps
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7220M
150 Mbps
VCC/ 2 (CMOS)
ISO7221A
1 Mbps
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7221B
5 Mbps
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7221C
25 Mbps
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7221M
150 Mbps
VCC/ 2 (CMOS)
Same direction
Opposite directions
8.3.1 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics (1)
PARAMETER
VIORM
VPR
TEST CONDITIONS
SPECIFICATION
Maximum working insulation
voltage
Input to output test voltage
560
After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
Method a, After environment tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial discharge < 5 pC
896
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s,
Partial discharge < 5 pC
1050
VIOTM
Transient overvoltage
VTEST = VIOTM
t = 60 s (qualification)
t = 1 s (100% production)
4000
RS
Insulation resistance
VIO = 500 V at TS = 150°C
>109
Pollution degree
(1)
UNIT
VPK
Ω
2
Climatic Classification 40/125/21
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Take care to maintain the creepage and
clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the
measurement techniques shown in the Isolation Glossary in the Related Documentation
section. Techniques such as inserting grooves, ribs, or both on a printed circuit board are
used to help increase these specifications.
8.3.2 IEC Package Characteristics
PARAMETER
L(I01)
L(I02)
(1)
20
TEST CONDITIONS
Minimum air gap (Clearance) (1)
Shortest pin-to-pin distance through air
Minimum external tracking (Creepage)
Shortest pin-to-pin distance across the
package surface
(1)
MIN
SOIC-8
TYP MAX
UNIT
4
mm
4
mm
Per JEDEC package dimensions.
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PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
CTI
Tracking resistance (Comparative
Tracking Index)
DIN EN 60112 (VDE 0303-11); IEC 60112
400
DTI
Distance through the insulation
Minimum Internal Gap (Internal Clearance)
0.008
mm
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of
the barrier tied together creating a two-pin device,
TA = 25°C
1012
Ω
Input to output, VIO = 500 V, 100°C ≤ TA ≤ max
1011
RIO
V
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
1
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1
pF
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
Rated mains voltage ≤400 VRMS
I-II
8.3.3 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN EN 61010-1 (VDE 04111)
Approved according to CSA Component Acceptance
Notice 5A and IEC 60950-1
Recognized under UL 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4000 VPK
Maximum Surge Voltage, 4000 VPK
Maximum Working Voltage, 560 VPK
Evaluated to CSA 60950-1-07 and IEC 60950-1 (2nd
Ed.) with 2000 VRMS Isolation rating for products with
working voltages ≤ 125 VRMS for reinforced insulation
and ≤ 390 VRMS for basic insulation
Single Protection, 2500 VRMS (1)
Certificate Number: 40016131
Master Contract Number: 220991
File Number: E181974
(1)
Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
8.3.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or
supply current
SOIC-8
TS
Maximum case temperature
SOIC-8
MIN
TYP
MAX
θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
124
θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
190
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in Absolute Maximum
Ratings. The power dissipation and junction-to-air thermal impedance of the ISO7220x and ISO7221x devices
installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal
resistance in Thermal Information is that of a device installed in the JESD51-3, Low Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the
recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
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250
Safety Limiting Current - mA
225
VCC1,2 at 3.6 V
200
175
150
125
VCC1,2 at 5.5 V
100
75
50
25
0
0
50
100
150
TC - Case Temperature - °C
200
Figure 17. θJC Thermal Derating Curve per VDE
8.4 Device Functional Modes
The ISO7220x and ISO7221x family of devices functional modes are shown in Table 2.
Table 2. ISO7220x or ISO7221x Function Table (1)
(1)
INPUT SIDE VCC
OUTPUT SIDE VCC
PU
PU
INPUT (IN)
OUTPUT (OUT)
H
H
L
L
Open
H
PD
PU
X
H
X
PD
X
Undetermined
PU = Powered Up (VCC ≥ 3.0 V), PD = Powered Down (VCC ≤ 2.5 V), X = Irrelevant, H = High Level,
L = Low Level
Input
VCC1
VCC1
VCC1
Output
VCC2
750 kW
IN
500 W
8W
OUT
13 W
Figure 18. Device I/O Schematics
22
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7220x and ISO7221x devices use single-ended TTL or CMOS-logic switching technology. The supply
voltage range is from 3 V (2.8 V for C-grade) to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, because of the single-ended design structure, digital isolators do not conform to any specific
interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator
is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver,
regardless of the interface type or standard.
9.2 Typical Application
The ISO7221x device can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog
converter, transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VCC1
VCC2
ISO7221
Figure 19. Isolated 4 to 20 mA Current Loop
9.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias (or limit current),
the ISO7220x and ISO7221x devices require only two external bypass capacitors to operate.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
Figure 20 and Figure 21 show the hookup of a typical ISO7220x and ISO7221x circuit. The only external
components are two bypass capacitors.
V CC1
V CC 2
0.1mF
2 mm
max .
from
Vcc 1
INPUT
1
INA 2
INB
INPUT
3
4
8
OUTA
7
OUTB
6
5
2 mm
max .
from
Vcc 2
0.1mF
OUTPUT
OUTPUT
ISO7220
GND 1
GND 2
Figure 20. Typical ISO7220x Circuit Hook-Up
V CC1
V CC2
0.1mF
2 mm
max .
from
Vcc1
OUTPUT
1
OUTA
2
INB
INPUT
3
4
8
INA
7
OUTB
6
5
2 mm
max .
from
Vcc 2
0.1mF
INPUT
OUTPUT
ISO7221
GND 1
GND 2
Figure 21. Typical ISO7221x Circuit Hook-Up
9.2.3 Application Curve
At maximum working voltage, the isolation barrier of the ISO7220x and ISO7221x devices has more than 28
years of life.
WORKING LIFE -- YEARS
100
VIORM at 560 VPK
28
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (V IORM ) -- VPK
Figure 22. Time-Dependent Dielectric Breakdown Test Results
24
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 data
sheet. For such applications, detailed power supply design and transformer selection recommendations are
available in the data sheet, SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0).
11 Layout
11.1 Layout Guidelines
A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 23). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.
• Route the high-speed traces on the top layer to avoid the use of vias (and the introduction of the inductances)
and allow for clean interconnects between the isolator and the transmitter and receiver circuits of the data
link.
• Place a solid ground plane next to the high-speed signal layer to establish controlled impedance for
transmission line interconnects and provide an excellent low-inductance path for the return current flow.
• Place the power plane next to the ground plane to create additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Route the slower speed control signals on the bottom layer to allow for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. Adding a second plane system to the stack makes the stack mechanically
stable and prevents it from warping. The power and ground plane of each power system can be placed closer
together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout
recommendations, see Application Note Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives because of its
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and selfextinguishing flammability characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Transformer Driver for Isolated Power Supplies, SLLSEA0
• Digital Isolator Design Guide, SLLA284
• Isolation Glossary, SLLA353
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7220A
Click here
Click here
Click here
Click here
Click here
ISO7220B
Click here
Click here
Click here
Click here
Click here
ISO7220C
Click here
Click here
Click here
Click here
Click here
ISO7220M
Click here
Click here
Click here
Click here
Click here
ISO7221A
Click here
Click here
Click here
Click here
Click here
ISO7221B
Click here
Click here
Click here
Click here
Click here
ISO7221C
Click here
Click here
Click here
Click here
Click here
ISO7221M
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
DeviceNet is a trademark of Open DeviceNet Vendors Association.
Profibus is a trademark of Profibus.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2015, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7220AD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220A
ISO7220ADG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220A
ISO7220ADR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220A
ISO7220ADRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220A
ISO7220BD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220B
ISO7220BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220B
ISO7220BDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220B
ISO7220BDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220B
ISO7220CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220C
ISO7220CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220C
ISO7220CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220C
ISO7220CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220C
ISO7220MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220M
ISO7220MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220M
ISO7220MDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220M
ISO7220MDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7220M
ISO7221AD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7221ADG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221A
ISO7221ADR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221A
ISO7221ADRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221A
ISO7221BD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221B
ISO7221BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221B
ISO7221BDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221B
ISO7221BDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221B
ISO7221CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221C
ISO7221CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221C
ISO7221CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221C
ISO7221CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221C
ISO7221MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221M
ISO7221MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221M
ISO7221MDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221M
ISO7221MDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7221M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7220A, ISO7221A, ISO7221C :
• Automotive: ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7220ADR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7220BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7220CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7220MDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7221ADR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7221BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7221CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7221MDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7220ADR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7220BDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7220CDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7220MDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7221ADR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7221BDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7221CDR
SOIC
D
8
2500
367.0
367.0
35.0
ISO7221MDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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