LTC4420 18V Dual Input Micropower PowerPath Prioritizer with Backup Supply Monitoring Features n n n n n n n n n n n n n Description Selects Highest Priority Valid Supply from Two Inputs Wide 1.8V to 18V Operating Range Internal Dual 2Ω, 0.5A Switches Low 3.6µA Operating Current Low 320nA V2 Current When V1 Connected to OUT Blocks Reverse and Cross Conduction Currents Reverse Supply Protection to –15V Built-In V2 Test with Optional V2 Disconnect V2 Freshness Seal/Ship Mode ±1.5% Accurate Adjustable Switchover Threshold ±2.3% Accurate V2 Monitor and Comparator Overcurrent and Thermal Protection Thermally Enhanced 12-Pin 3mm × 3mm DFN and 12-Lead Exposed Pad MSOP Packages Applications n n n Low Power Battery Backup Portable Equipment Point-of-Sale (POS) Equipment The LTC®4420 is a dual input monolithic PowerPath™ prioritizer, with low operating current, that provides backup switchover for keeping critical circuitry alive during brownout and power loss conditions. Unlike diode-OR products, little current is drawn from the inactive supply even if its voltage is greater than the active supply. Internal 2Ω, current limited PMOS switches provide power path selection from a primary input (V1) or a backup input (V2) to the output. Two adjustable voltage monitors set via external resistive dividers provide flexibility in setting V1 to V2 switchover and V2 undervoltage thresholds. V1 is monitored continuously while V2 supply monitoring includes controllable low duty cycle UV monitoring. When primary input V1 drops, the ADJ monitor causes OUT to be switched to V2. When V2 drops, it is disconnected from OUT if V2DIS is low. Fast non-overlap switchover circuitry prevents reverse and cross conduction while minimizing output droop. Auxiliary voltage monitor CMP1 provides flexible voltage monitoring and output V2OK provides V2 undervoltage status. Freshness seal mode prevents V2 battery discharge during storage or shipment. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Typical Switchover Waveforms 5V WALL ADAPTER 1M 1M 10µF OUT OUT V1 ADJ CMPOUT1 V1UV V2OK V2OK 1M 237k CMP1 121k + 7.4V Li-Ion V2 2V/DIV V1 2V/DIV LTC4420 V2 V2 MONITORING INTERVAL SWITCHOVER THRESHOLD V2 UNDERVOLTAGE AND DISCONNECT V2DIS 4.02M V2UV V2TEST 280k GNDSW GND TYPICAL VALUES: SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) 4420 TA01a V2OK THRESHOLD: V2 < 6V (V2 FALLING) OUT COUT = 10µF ILOAD = 100mA 20ms/DIV 4420 TA01b 4420f For more information www.linear.com/LTC4420 1 LTC4420 Absolute Maximum Ratings Terminal Voltages V1, V2.......................................................–15V to 24V OUT........................................................ –0.3V to 24V OUT – V2..................................................–24V to 39V OUT – V1..................................................–24V to 39V Input Voltages ADJ, CMP1, V2UV, V2TEST, V2DIS (Note 3) ................................................. –0.3V to 24V Output Voltages CMPOUT1, GNDSW, V2OK (Note 3) ....... –0.3V to 24V (Notes 1, 2) Pin Currents (Note 2) ADJ, CMP1, V2UV, CMPOUT1, GNDSW..............–1mA V2TEST, V2DIS, V2OK .......................................–1mA Operating Ambient Temperature Range LTC4420C................................................. 0°C to 70°C LTC4420I..............................................–40°C to 85°C Junction Temperature (Notes 4, 5)......................... 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP Package.................................................. 300°C Pin Configuration TOP VIEW TOP VIEW V1 1 12 V2 V2TEST 2 11 V2DIS CMP1 3 ADJ 4 13 GND V1 V2TEST CMP1 ADJ GND CMPOUT1 10 V2UV 9 OUT GND 5 8 V2OK CMPOUT1 6 7 GNDSW 1 2 3 4 5 6 12 11 10 9 8 7 13 GND V2 V2DIS V2UV OUT V2OK GNDSW MSE PACKAGE 12-LEAD PLASTIC MSOP DD PACKAGE 12-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB Order Information (http://www.linear.com/product/LTC4420#orderinfo) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4420CDD#PBF LTC4420CDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC4420IDD#PBF LTC4420IDD#TRPBF LGMR 12-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC4420CMSE#PBF LTC4420CMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP 0°C to 70°C LTC4420IMSE#PBF LTC4420IMSE#TRPBF 4420 12-Lead Plastic Exposed Pad MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage and Currents V1, V2 Operating Voltage Range IV1 V1 Current, V1 Powering OUT V1 Current, V2 Powering OUT l IOUT = 0, V1 = 8.4V, V2 = 3.6V V1 = 8.4V, V2 = 3.6V l l 1.8 3.6 500 18 V 6.3 800 µA nA 4420f 2 For more information www.linear.com/LTC4420 LTC4420 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V1 = 3.6V, V2 = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IV2 V2 Current, V2 Powering OUT V2 Current, V1 Powering OUT V2 Current in Freshness Seal Mode IOUT = 0, V1 = 3.6V, V2 = 8.4V V1 = 3.6V, V2 = 8.4V V1 = GND, V2 = 5V l l l 3.3 320 120 6 650 220 µA nA nA RON Switch Resistance V1 = V2 = 5V, IOUT = –100mA l 1 2 5 Ω tVALID(V1) Input Qualification Time V1 Rising, ADJ Rising l 34 64 94 ms Input Comparators VTHA ADJ Threshold ADJ Falling l 1.032 1.047 1.062 VHYSTA ADJ Comparator Hysteresis ADJ Rising l 30 50 70 V VTHC CMP1, V2UV Threshold CMP1, V2UV Falling l 0.378 0.387 0.396 V VHYSTC CMP1, V2UV Comparator Hysteresis CMP1, V2UV Rising l 7.5 10 12.5 mV tPDA ADJ Comparator Falling Response Time 10% Overdrive l 4 7.3 12 µs tPDC CMP1, V2UV Comparator Response Times 20% Overdrive l 30 65 µs 1.1 1.6 A mV Power Path Function ILIM Output Current Limit V1, V2 = 8.4V l 0.5 VREV Reverse Comparator Threshold (V1, V2) – VOUT for Power Path Turn-On l 25 50 75 mV tSWITCH Break-Before-Make Switchover Time V1 = V2 = 5V, IOUT < 10mA l 1 2.5 5 µs tMONL Longest Possible V2UV Monitor Duration V2TEST ≥ VIH l 88 128 168 ms tMONS Shortest Possible V2UV Monitor Duration V2TEST ≥ VIH l 1 2 3 ms 132 180 V2 Monitoring tLTEST Time Between V2UV Monitoring Events V2TEST ≥ VIH l 80 tHV2T Minimum Allowed V2TEST High Time V2TEST Driven Externally l 10 ms s tLV2T Minimum Allowed V2TEST Low Time V2TEST Driven Externally l 10 ms I/O Specifications VOL Output Voltage Low, CMPOUT1, GNDSW and V2OK I = 100µA I = 1mA l l VOH V2OK Output High Voltage I = –1µA, V2 = 5V l IOH V2OK, GNDSW, CMPOUT1 Output High Leakage CMPOUT1, GNDSW, V2OK = 18V l VIL V2DIS, V2TEST Input Low Voltage V1 = V2 = 5V l VIH V2DIS, V2TEST Input High Voltage V1 = V2 = 5V l IV2X(IN,Z) V2DIS, V2TEST Allowable Leakage in Open State IPU(V2OK) V2OK Pull-Up Current V2 = 5V, ADJ = 0V, V2OK = 0V l ILEAK ADJ, CMP1, V2UV Leakage Current ADJ, CMP1, V2UV = 0V, 1.5V l 15 120 1.05 2.3 V ±50 ±150 nA 0.2 V 0.9 –2.7 mV mV 1.65 V 0.5 µA –5 –8 µA ±1 ±5 nA l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: These pins can be tied to voltages down to –5V through a resistor that limits the current to less than –1mA. Note 4: The LTC4420 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction 50 250 temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC4420 is tested under pulsed load conditions such that TJ ≈ TA. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD • θJA) 4420f For more information www.linear.com/LTC4420 3 LTC4420 Typical Performance Characteristics (TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated) 4.5 V1 Current, V1 Powers OUT (IOUT = 0) V2 Current, V2 Powers OUT (IOUT = 0) 4.0 V1 = 1.8V V1 = 3.6V V1 ≥ 6V V2 Current, V1 Powers Out 450 V2 = 1.8V V2 = 3.6V V2 ≥ 6V V1 = V2 400 V2 CURRENT (µA) 3.5 3.5 V2 CURRENT (nA) V1 CURRENT (µA) 4.0 3.0 3.0 –25 0 25 50 75 TEMPERATURE (°C) 100 2.5 –50 125 –25 0 25 50 75 TEMPERATURE (°C) 250 –40°C 25°C 90°C 250 V1 = V2 200 450 150 VOL (mV) 500 400 0 5 10 15 V2 VOLTAGE (V) 0 20 4420 G03 0.995 0 0.5 1 1.5 PULL-DOWN CURRENT (mA) 2 0.990 –50 NORMALIZED VTHA 125 4420 G07 100 VADJ = 0V, 1.5V 2.5 50 40 30 –50 125 ADJ Leakage vs Temperature 3.0 ADJ LEAKAGE (nA) 60 ADJ HYSTERESIS (mV) 1.005 0.995 0 25 50 75 TEMPERATURE (°C) 4420 G06 ADJ Hysteresis vs Temperature 1.000 –25 4420 G05 70 100 20 1.010 50 1.010 0 25 50 75 TEMPERATURE (°C) 10 15 V2 VOLTAGE (V) 1.000 Normalized Falling ADJ Threshold vs Temperature –25 5 1.005 4420 G04 0.990 –50 0 Normalized CMP1 and V2UV Falling Thresholds vs Temperature Open-Drain (CMPOUT1, GNDSW, V2OK) VOL vs Pull-Down Current 100 –40°C 25°C 90°C 350 150 125 NORMALIZED VTHC V1 Current, V2 Powers Out 550 100 4420 G02 4420 G01 V1 CURRENT (nA) 300 200 2.5 –50 300 350 2.0 1.5 1.0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4420 G08 0.5 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4420 G09 4420f 4 For more information www.linear.com/LTC4420 LTC4420 Typical Performance Characteristics (TA = 25°C, V1 = V2 = 3.6V unless otherwise indicated) Output Current IOUT Response for Different Shorting Impedances 3.0 1.30 2.5 1.20 2.0 1.10 IOUT vs VOUT for Different Input Supply Voltages 1.2 1.2Ω 2.2Ω 3.3Ω 3.9Ω 5Ω 1.5 0.4 0.90 0.5 0.2 0 25 50 75 TEMPERATURE (°C) 100 0 125 0 40µs/DIV 4420 G10 5 250 5V 3.6V 2V 200 V2 CURRENT (nA) RON (Ω) 1 2 3 VOUT (V) 4 5 4419 G12 Freshness Seal Current vs V2 Voltage and Temperature 4 3 2 1.8V 3.6V 5V ≥6V V1 = 0V 150 100 50 –25 0 25 50 75 TEMPERATURE (°C) 100 0 –50 125 4419 G13 Switchover from a Higher to a Lower Voltage V2 DISCONNECT FROM V1 V2 CONNECT TO V2 3ms/DIV –25 0 25 50 TEMPERATURE (°C) V1 2V/DIV 100 V1 Reverse Voltage Blocking with V2 Powering Out V2 5V/DIV 10V 6V 10V 6V OUT COUT = 10µF C1= C2 = 10µF ILOAD = 50mA IOUT 0.5A/DIV 4419 G15 75 4420 G14 Output Voltage and Current Waveforms During Switchover COUT = 10µF IOUT = 200mA V1 OUT 2V/DIV 0 4419 G11 Switch RON vs Temperature 1 –50 OHMIC 0.6 1.0 –25 CURRENT LIMIT 0.8 1.00 0.80 –50 VIN = 1.8V VIN = 3.6V VIN = 5V FOLDBACK 1.0 IOUT (A) 1.40 IOUT (A) CURRENT LIMIT (A) Output Current Limit vs Temperature 10µs/DIV 4420 G16 V1 10V/DIV –10V IOUT 0.5A/DIV ILOAD = 50mA 20ms/DIV 4420 G17 4420f For more information www.linear.com/LTC4420 5 LTC4420 Pin Functions ADJ: Adjustable Switchover Threshold Input. ADJ is the noninverting input to the switchover threshold comparator. If V1 ≥ 1.55V and ADJ ≥ 1.097V for at least 64ms, OUT is switched internally to the primary V1 input. When the ADJ input voltage is lower than 1.047V, OUT is switched internally to V2 if conditions in Table 1 of the Applications Information section are met. Otherwise, OUT stays unpowered. Tie ADJ via a resistive divider to V1, in order to set the V1 to V2 switchover voltage. Do not leave open. CMP1: Auxiliary Comparator 1 Monitor Input . CMP1 is the noninverting input to an auxiliary comparator. The inverting input is internally connected to a 0.387V reference. Connect CMP1 to GND when it is not used. CMPOUT1: Auxiliary Comparator Output 1. This open-drain comparator output is pulled low when CMP1 is below 0.387V and during power-up, otherwise it is released. Once released, connecting a resistor between CMPOUT1 and a desired supply voltage up to 18V causes this pin to be pulled high. Leave open if unused. GNDSW: Pulsed GND Output. This open-drain output is pulled low when V2UV is being monitored, otherwise it is released high. Connect a resistive divider between V2, V2UV and GNDSW to set V2 undervoltage threshold. Leave open if unused. Exposed Pad: For best thermal performance, solder the exposed pad to a large PCB area. GND: Device Ground. OUT: Output Voltage Supply. OUT is a prioritized voltage output that is either connected to V1, V2 or is unpowered as indicated in Table 1 of the Applications Information section. Additionally, OUT must be at least 50mV below the input supply for a connection to that supply to be activated. Bypass with a capacitor of 1µF or greater. See Applications Information for bypass capacitor recommendations. V1: Primary Power Supply. OUT is internally switched to V1 if V1 ≥ 1.55V and ADJ ≥ 1.097V. When in freshness seal, applying V1 ≥ 1.55V and ADJ ≥ 1.097V for 32ms disables freshness seal. Bypass with 1µF or greater. Tie to GND if unused. V2: Backup Power Supply. OUT is internally switched to V2 if ADJ < 1.047V or V1 < 1.55V, provided other conditions listed in Table 1 in Applications Information are met. Bypass with 1µF or greater. Tie to GND if unused. V2DIS: V2 Power Path Disable Input. When driven low, this pin disables the V2 to OUT power path if input V2UV drops below 0.387V. Connect a resistor between V2 or OUT and this pin to provide additional pull-up. Leave open if unused. This pin is initialized high during power-up. V2OK: V2OK Logic Output. V2OK is an output that is driven high with a 5µA pull-up if V2UV > 0.387V at the end of the V2UV monitoring period. Otherwise it is driven low. Connect a resistor between OUT and this pin to provide additional pull-up. As this pin is used to enable freshness seal, do not force low or connect a pull-down resistor to this pin. Leave open if unused. V2TEST: V2 Undervoltage Test Enable Input. This pin sets the duty cycle of V2 undervoltage monitoring. When V1 is valid, driving V2TEST low disables V2 monitoring while driving it high enables V2 monitoring with a maximum duty cycle of ~0.1%. When V1 is invalid or not present, V2 is always monitored with V2TEST setting the duty cycle between 0.0015% and 0.1% depending on its own state and previously determined V2 validity. Refer to the state diagram and waveforms in the Applications Information section for details. Leave open or connect a resistor between V2 or OUT and this pin to provide additional pull-up. Connect to GND if unused. This pin is initialized high on power-up. V2UV: V2 Undervoltage Monitor Input. V2UV is the noninverting input to a comparator whose inverting input is internally connected to a 0.387V reference. Connect a resistive divider between V2, V2UV and GNDSW to set V2 undervoltage threshold. See the Applications Information section for details on V2 monitoring. Connect a pull-up resistor to V2 if unused. Do not leave open. 4420f 6 For more information www.linear.com/LTC4420 LTC4420 Functional Diagram CMPOUT1 3 1 12 CMP1 0.397V/ 0.387V + – CP1 V1 V2 OUT FRESHNESS SEAL 50mV EN1 11 ADJ 1.097V/ 1.047V – + + – CUV1 – + CUV2 10 V2UV 7.3µs 5µA V2OK 8 CV2UV D Q E GNDSW EN_GNDSW 2 CREV1 64ms 1M – + CREV2 9 2.5V CADJ V2DIS 0.397V/ 0.387V EN2 + 50mV + – – + – + – CONTROL LOGIC 1.55V/ 1.52V 4 6 7 V2TEST 1M 5 GND 4420 BD 4420f For more information www.linear.com/LTC4420 7 LTC4420 Operation The Functional Diagram shows the major blocks of the LTC4420. The LTC4420 is a PowerPath prioritizer that switches output OUT between primary (V1) and backup (V2) sources depending on their validity and priority with V1 having the highest priority. A resistive divider between V1, ADJ and GND and comparators CUV1 and CADJ are used to monitor V1’s voltage to establish validity. V1 is valid if V1 ≥ 1.55V and ADJ ≥ 1.097V for 64ms after V1 rises above 1.55V. Otherwise V1 is invalid. A resistive divider between V2, V2UV and GNDSW and comparators CUV2 and CV2UV are used to monitor V2’s voltage to establish validity. V2 voltage is monitored periodically in order to minimize current consumption in the divider. V2 is valid if V2 ≥ 1.55V and V2UV ≥ 0.4V at the end of the V2 monitoring period. Otherwise it is invalid. If neither supply is valid, OUT stays unpowered if V2DIS is low. If V2DIS is high and V2 > 1.55V, OUT is connected to V2. Refer to Table 1 in the Applications Information section for details. Switchover threshold is independent of relative V1 and V2 voltages, permitting V1 to be lower or higher than V2 when V1 powers OUT and vice versa. Power connection to the output is made by enhancing backto-back internal P-channel MOSFETs. Current passed by the MOSFETs is limited to typically 1.1A if OUT is greater than 1V. Otherwise it is limited to 250mA. When switching from V1 to V2, the V1 to OUT power path is first disabled and comparator CREV2 is enabled. After the OUT voltage drops 50mV below V2, as detected by CREV2, OUT is then connected to V2. This break-before-make strategy prevents OUT from backfeeding V2. Switchover back to V1 occurs in a similar manner once V1 has been revalidated. The LTC4420 blocks reverse voltages up to –15V when a reverse condition occurs on an inactive channel. The LTC4420 also disables a channel if the corresponding input supply falls below 1.52V. A small ~3µA current is drawn from either the prioritized input supply, or the highest supply if both input supplies are below 1.55V. Very little current (~320nA) is drawn from the unused supply. Pins V2TEST and V2DIS provide flexibility in monitoring and disconnecting the V2 power path using the V2UV monitor input. V2 is monitored by activating the V2-V2UVGNDSW resistive divider. V2TEST allows for adjustability of GNDSW duty cycle to trade off V2 quiescent current with V2 monitoring frequency. When low, V2DIS disables the V2 to OUT power path, if V2 is found to be invalid. Refer to the Applications Information section for details. If V2 is valid at the end of a V2 monitoring interval, output V2OK is latched high. Otherwise it is latched low. V2OK retains its state until the end of the next V2 monitoring interval when it gets updated. V2 monitoring is disabled if V2 < 1.55V or during thermal shutdown. During initial powerup V2 monitoring is disabled and V2OK is initialized low. The LTC4420 provides an additional comparator, CP1, whose open-drain output pulls low either when the CMP1 pin voltage falls below 0.387V or during initial power up. This comparator can be used to monitor supplies to provide early power failure warning and other useful information. The LTC4420 can be put into a V2 freshness seal mode to prevent battery discharge during storage or shipment. The Applications Information section lists the steps to engage and disengage V2 freshness seal. 4420f 8 For more information www.linear.com/LTC4420 LTC4420 Applications Information The LTC4420 is a low quiescent current 2-channel prioritizer that powers both its internal circuitry and its output OUT from a prioritized valid input supply. Unlike an ideal diode-OR, the LTC4420 does not necessarily draw current from the highest supply as long as one supply is greater than 1.8V. Table 1 lists the input supply from which the LTC4420 draws its internal quiescent current ICC and the supply to which OUT is connected after input supplies have been qualified. + 2-CELL Li-Ion 7.4V C1 4.7µF R3 1M R2 150k R1 78.7k + A typical battery backup application is shown in Figure 1. V1 is powered by a 2-cell Li-Ion battery pack whose safe discharge limit is between 5.6V and 6V. V2 is powered by a low self discharge 7.6V Li-Thionyl Chloride (Li-SOCl2) hold-up battery which is completely discharged when its voltage drops to 6V. Li-SOCL2 battery life is maximized as very little current is drawn from V2 during normal operation due to the low duty cycle of V2 monitoring and the LTC4420’s low V2 standby current. To protect the 2-cell Li-Ion battery on V1, switchover threshold is set to be ~5.6V. After switchover to V2, the Li-Ion battery primarily supplies only divider R1-R3’s current as the LTC4420 draws only a small standby current from V1. Monitor CMP1 is configured to provide V1 power failure warning by driving V1UV low when V1 falls below 6V. Monitor input V2UV is configured to set V2’s UV threshold to 6V and V2DIS is tied low to disconnect the V2 to OUT power path when V2 falls below 6V. V2TEST is tied high to monitor V2 once every 132s. Relevant equations used to calculate these component values are discussed in the following subsections. 2-CELL Li-SOCl2 7.4V C2 4.7µF R5 4.02M R4 280k V1 OUT OUT ADJ R6 1M V2TEST CMPOUT1 CMP1 COUT 10µF R8 1M V1UV V2OK V2UV SWITCHOVER THRESHOLD: V1 < 5.6V (V1 FALLING) V1UV: V1 < 6V (V1 FALLING) V2UV: V2 < 6V (V2 FALLING) LTC4420 V2 R7 1M V2DIS V2UV GNDSW GND 4420 F01 Figure 1. The LTC4420 Protecting 2-Cell Lithium Battery Packs on V1 and V2 from Discharge Below Their Safe Minimum Voltage Setting Switchover and V2 Undervoltage Thresholds Several factors affect switchover voltage and should be taken into account when calculating resistor values. These include resistor tolerance, 1.5% ADJ comparator threshold error, divider impedance and worst-case ADJ pin leakage. These factors also apply to resistive dividers connected to monitor inputs CMP1 and V2UV. Referring to Figure 1 and the Electrical Characteristics table, the typical V1 switchover threshold: VSW1 = VTHA • (R1+R2+R3) R1+R2 (1) Table 1. OUT and LTC4420 ICC Power INPUT VOLTAGES V1 > 1.55V ADJ > 1.097V V2 > 1.55V V2DIS > 0.9V V2UV > 0.397* ICC SOURCE OUT CONNECTION Y† Y† X X X V1 V1 Y N Y Y X V2 V2 Y N Y N Y V2 V2 Y N Y N N V1 Hi-Z Y N N X X V1 Hi-Z N X Y N N V2 Hi-Z N X Y N Y V2 V2 N X Y Y X V2 V2 N X N X X VMAX** Hi-Z *Note: Refers to V2UV voltage at the end of the V2 monitoring period. **Note: VMAX = higher of V1 and V2. † For 64ms. 4420f For more information www.linear.com/LTC4420 9 LTC4420 Applications Information Typical V1 undervoltage threshold is: VV1UV = VTHC • (R1+R2+R3) R1 (2) Worst-case VOL due to current flow into the GNDSW pin must be taken into account while calculating values for the V2 undervoltage resistive divider: VTHC VV2UV = V R4+ OL 100µA V • R4+R5+ OL 100µA (3) Equations 1-3 assume ADJ and CMP1 pin leakages are negligible. To account for pin leakage, equations 1-3 must be modified by an ILEAK • REQ term where equivalent resistance REQ must be calculated on a case-by-case basis. Worst-case component values and reference voltage tolerances must be used to calculate the maximum and minimum threshold voltages. For example, to calculate minimum falling switchover threshold voltage VSW1(MIN), use VTHA(MIN), (R2+R1)(MAX), R3(MIN) in equation 1. 125 t PDA (µs) 100 75 50 tNOV •IOUT ∆VOUT 10 100 1k 10k dV ADJ /dt (V/s) 100k limits output droop to less than ∆VOUT. In order to estimate tNOV and IOUT, first consider a scenario where power supplies are present on V1 and V2, and their voltages are changing slowly compared to the ADJ comparator propagation delay tPDA. For such cases, IOUT is ILOAD and tNOV is tSWITCH. COUT can be sized according to equation 5 with IOUT = ILOAD(MAX) and tNOV = tSWITCH(MAX) to limit maximum output droop when switching to a higher supply. When switching to a lower supply, switchover is initiated only after OUT falls VREV below the supply that is being switched in. In such cases, total output droop is ∆VOUT + VREV. Next consider a scenario where the input power source powering OUT is unplugged. OUT backfeeds circuitry connected to the input supply pin. Both input and output droop at the same rate. Referring to Figure 1, assume the battery on V1 is unplugged when OUT is connected to V1. IOUT is the sum of ILOAD and the back fed current IBACK, which in this example is IR3. As OUT and V1, since the two are connected, droop below the ADJ threshold, switchover occurs to V2 with a dead time IOUT = (IBACK + ILOAD) 4420 F02 (6) (7) in equation 5 to size COUT: Selecting Output Capacitor COUT COUT ≥ COUT can be selected to control either output voltage droop during switchover or output rising slew rate during initial power-up or when switching to a higher supply. In general, output droop, ΔVOUT, can be calculated by: tNOV •IOUT COUT (5) where tPDA is an overdrive dependent ADJ comparator delay. As an approximation, use tPDA from the Electrical Characteristics table to estimate tNOV. Use this tNOV and: Figure 2. ADJ Comparator Propagation Delay as a Function of Slew Rate; tPDA vs dVADJ/dt VOUT = COUT ≥ tNOV = tPDA + tSWITCH 25 0 where IOUT is the current supplied by COUT during nonoverlap or dead time, tNOV. Choosing: ( tPDA + tSWITCH ) •IOUT ∆VOUT (8) Refer to Figure 2 for a more accurate estimate of tPDA vs dVOUT/dt. If ADJ is filtered with capacitor CADJ, its discharge time via divider R1 – R3 increases tPDA. This results in a higher output droop than estimated by equation (8). (4) 4420f 10 For more information www.linear.com/LTC4420 LTC4420 Applications Information In order to limit output rising slew rate dVOUT/dt, size: COUT ≥ ILIM dVOUT dt (9) as the LTC4420 limits OUT charging current to ILIM until OUT approaches the input supply to within ILIM • RON, where RON is the channel switch resistance. Refer to the Thermal Protection and Maximum COUT section to determine maximum allowed COUT. Inductive Effects Parasitic inductance and resistance can impact circuit performance by causing overshoot and undershoot of input and output voltages when the LTC4420 turns off. Parasitic inductance in the power path causes positive-going overshoot on the input and a negative-going undershoot on the output. Another cause of positive input overshoot is R-L-C tank ringing during hot plug of an input supply. Input overshoot is most pronounced when the total resistance of the input tank is low. Care must be taken to ensure over voltage transients do not exceed the Absolute Maximum ratings of the LTC4420. Additionally, parasitic resistance and inductance can cause input undershoot (droop) during power path turn on. If severe enough, undershoot can temporarily invalidate a supply and cause repeated power up cycles (motorboating) or unwanted switchover between sources. The first step to avoid these issues is to minimize parasitic inductance and resistance in the power path. Guidelines are given in the layout section for minimizing parasitic inductance on the printed circuit board (PCB). External to the PCB, twist the power and ground wires together to minimize inductance. V1 Second, use a bypass capacitor at the input to limit input voltage overshoot during LTC4420 power path turn off. A few micro farads is sufficient for most applications. When hot plugging supplies with large parasitic inductances, it is possible for the R-L-C tank to ring to more than twice the nominal supply voltage. Wall adapters and batteries typically have enough loss (i.e. series resistance) to prevent ringing of this magnitude. However, if this is a problem, snub input capacitor CSN1 with resistor RSN1, typically 0.5Ω. Place this network close to the supply pin. Third, if an input capacitor is not permissible, use a TVS (such as SMAJ16CA) in applications when supply pin transients can exceed 24V. Use a bidirectional TVS in applications requiring reverse input protection. Note that a TVS does not address droop and motorboating, which are solved only by input bypassing. During normal operation, the LTC4420 limits power path current to < 1.6A and internal circuitry prevents OUT from ringing below ground during power path turn off. This is also true for output shorts when the short is close to the LTC4420’s OUT pin. However, if the output is shorted through a long wire, current in the wire inductance (LPAR2 in Figure 3) builds up due to the discharge of COUT1 and can be much higher than 1.6A. This current causes the OUT pin to ring below its −0.3V absolute maximum rating once COUT1 has been fully discharged. For this special case, split the output capacitor between COUT1 and COUT2 and make COUT1 small. Snub COUT1 with resister RSN2 to damp R-L-C ringing if required. Size COUT2 to obtain the required total output capacitance. Also add a diode between OUT and ground close to the LTC4420 to clamp negative ringing if the OUT pin rings below –0.3V. LPAR2 LTC4420 V1 OUT LPAR1 RSN1 0.5Ω CSN1 5µF OPTIONAL OUT RSN2 1Ω COUT2 10µF OPTIONAL COUT1 1µF D1 1N5818 4420 F03 Figure 3. Recommended Inductive Transient Suppression Circuitry 4420f For more information www.linear.com/LTC4420 11 LTC4420 Applications Information V2 Monitoring and Control V2 monitoring duration and time between monitoring events are set by input V2TEST, V1 validity and V2 validity as determined previously. Complete behavior is described by the state diagram shown in Figure 4. This implementation was chosen for the following reasons, The LTC4420 monitors V2 voltage through an external resistive divider connected between V2, V2UV and GNDSW. When V2 is being monitored, open-drain output GNDSW is pulled low to activate the resistive divider, otherwise it is released high. V2UV is monitored by comparator CV2UV, whose output is latched at the end of the monitoring period. This latched output establishes V2 validity and is used in Table 1. 1. To provide flexibility in monitoring and disconnecting the backup battery as required by the application, while minimizing current draw through the V2 resistive divider. V2TEST and V2DIS need to be actively driven to achieve this. POWER OR UP SWITCHOVER EXIT THERMAL OR SHUTDOWN TO V2 V2 < 1.55V OR ST TE H V2 HIG DISABLE V2 MONITORING OT V2 N ID L A D V N T ES A V2T H HIG V2 ID AL D V AN T V2 THERMAL SHUTDOWN NO UV V2 NOT V2TEST AND AND V1 VALID VALID HIGH 2ms V2 MONITORING WHEN V1 IS VALID V2 V2TEST AND VALID HIGH ) V1 V2TEST AND VALID LOW V2 V2TEST AND VALID HIGH ND S ID L VA V1 ND A D W O TL AN ID V1 L VA S TE V2 TE (V NO A GH I TH V2 ( V1 V2TEST V2 NOT VALID AND LOW OR NOT VALID EST V2T ND LOW V1 A ID VAL WAIT FOR RISING V2TEST OR OVERRIDE CONDITION V1 V2TEST V2 NOT AND AND VALID HIGH VALID ID AL TV V2 NOT VALID AND V1 NOT VALID 128ms V2 MONITORING ) V1 VALID AND V2TEST LOW NO 2ms V2 MONITORING WHEN V1 IS INVALID T V2 VA LI D AN D NO T V1 VA LI D V1 NOT VALID AND (V2TEST LOW AND V2 NOT VALID) V2 VALID OR V2TEST HIGH 4420 F04 Figure 4. State Diagram Describing V2 Monitoring 4420f 12 For more information www.linear.com/LTC4420 LTC4420 Applications Information 2. To provide default battery backup monitoring and disconnect in systems where V2TEST and V2DIS are not actively driven. V2TEST and V2DIS are either tied high or low in these applications. 3. To allow a system powered by OUT to shut itself down if there is no valid input supply. 4. To support backup battery charging without having to disconnect the battery from the system. 5. Handling exceptions such as initial power up, recovery from thermal shutdown and switchover after long intervals when V2 was not being monitored. Configuring V2TEST and V2DIS V2TEST controls the duration of and the time between V2 monitoring events. It can either be tied high, low or actively driven based on the application. The following section explores common scenarios. In applications where primary supply V1 is going to be valid for long periods of time and where V2TEST can be actively driven, V2TEST should generally be driven low and only pulsed high when V2 status is needed. This minimizes V2-V2UV-GNDSW divider current. This scenario also applies when V2 is a battery that slowly discharges over time, making a V2 status update every 132s superfluous. When operating off V2, V2TEST may be pulsed at intervals shorter than 131s to check V2’s validity especially after large load current spikes. If V2TEST cannot be actively driven, it should be tied to either V2 or OUT through a pull-up resistor. If V2 can be reversed, tie V2TEST to OUT. Tying V2TEST high ensures that V2 is monitored every 132s as long as V2 > 1.55V. V2 monitoring duration is 128ms when V2 is valid and reduces to 2ms if V2 becomes invalid. Use smaller resistors in the V2-V2UV-GNDSW divider if V2 is a battery that can develop a passivation layer when it is not being used. Larger V2 current helps break the passivation whenever the V2 divider is active. In special cases where V2 needs to be monitored only when V1 goes invalid and when battery passivation is not an issue, tie V2TEST low. If automatic V2 disconnect is desired when a V2 UV event occurs, tie V2DIS low. Otherwise leave open or tie to either OUT or V2 through a pull up resistor. If V2 can be reversed, tie V2DIS to OUT. If V2DIS can be actively driven, driving it low some time after a V2 UV event (output V2OK goes low) allows systems powered by OUT to finish active tasks, backup data and initiate shutdown proceedings. Actively Driving V2TEST In Figure 5, V2TEST is actively driven. When V1 powers up above switchover threshold VSW1, it is qualified for 64ms after which the V1 to OUT power path is activated. When V2 rises above 1.55V, GNDSW is pulsed low for 128ms and V2UV is monitored, even though V2TEST is low. V2 is found to be valid resulting in V2OK being driven high. As long as V1 remains valid, V2 is monitored only when V2TEST is driven high with V2 monitoring time being the lower of either the V2TEST high time or 128ms. Figure 5 shows two such monitoring events of durations t1 and t2 where t1 and t2 are less than 128ms. When V1 drops below VSW1, OUT is switched to V2 and V2 validity is refreshed by monitoring it once for 128ms independent of the state of V2TEST. Following this, since V2 is the only valid supply, V2 is monitored for 2ms every 132s if V2TEST is low or for 128ms every 132s if V2TEST is high. If V2 becomes invalid and V2DIS is low, the V2 to OUT power path gets disabled. V2TEST Tied Low Figure 6 shows voltage waveforms for the case where V2TEST is tied low. When V2 powers up above 1.55V, GNDSW is pulsed low and V2 is monitored once for 128ms. Simultaneously, the V2 to OUT power path is activated in order to allow a system powered by OUT to power itself up and drive V2DIS to a desired state. V2 is determined to be valid causing V2OK to be driven high and the V2 power path to remain activated. If V2 was determined to be invalid and V2DIS was low, V2’s power path would have been disabled and V2OK pulled low after 128ms. Since both V1 and V2TEST are low, V2 is monitored for 2ms every 132s. When V1 becomes valid, OUT is switched to V1 and V2 monitoring is halted until V1 becomes invalid. 4420f For more information www.linear.com/LTC4420 13 LTC4420 Applications Information VSW1 VSW1 V1 1.55V V2 VUV2 t1 t2 t1 t2 V2TEST 128ms 128ms 131s 2ms GNDSW V2OK ~64ms OUT V2 POWER PATH ACTIVE V1 POWER PATH ACTIVE TIME 4420 F05 Figure 5. V2 Monitoring by Actively Driving VTEST. Note That t1 and t2 are < 128ms VSW1 V1 V2 1.55V VUV2 128ms 131s 2ms 131s 2ms GNDSW V2OK OUT ~64ms V1 POWER PATH ACTIVE V2 POWER PATH ACTIVE TIME 4420 F06 Figure 6. V2 Monitoring When V2TEST Is Low 4420f 14 For more information www.linear.com/LTC4420 LTC4420 Applications Information INCREASING CMP1 HYSTERESIS In some applications, built in CMP1 hysteresis may be insufficient. In such cases, CMP1 hysteresis can be increased as shown in Figure 7. Hysteresis at the monitored input VMON with R8 present and assuming R9 << R8, is given by: R3 R3 VHYST = VHYSTC + VPU (10) R1||R3||R8 R8 where VHYSTC is found in the electrical table and is typically 10mV. Account for supply VPU and resistor R8 when calculating rising and falling thresholds of monitored input VMON. VMON R3 VPU CMP1 R9 LTC4420 R1 4420 F07 Figure 7. Increasing COMP1 Hysteresis Supply Impedance and ADJ Comparator Hysteresis In some applications, V1 could be supplied by a battery pack with high ESR or through a long cable with appreciable series resistance. Load current, IOUT, flowing through this resistance reduces the monitored V1 voltage by: (11) The drop can be as high as: ΔV1 = ILIM • RESR ∆V VSW1 •COUT • 1– 2 •ILIM •RESR C1> ∆V (13) to ensure no switchover occurs when COUT is initially being charged. If the resulting C1 value causes large inrush current, is physically too big or requires a large snubber resistor when V1 is plugged (refer to the Typical Applications section), select C1 to be as high a value as the application can tolerate. A filter capacitor CADJ can also be added to ADJ, to ride through the initial output charge up time. CADJ should be minimized as it slows ADJ response, resulting in a larger output droop when the input supply powering V1 is either unplugged or drops quickly. Input Shorts and Supply Brownout CMPOUT1 R8 ∆V1 = IOUT • RESR Referring to Figure 1, in order to prevent switchover when COUT is being initially charged add input capacitor C1. Ideally, if V1 is greater than switchover threshold VSW1 by ∆V, size: (12) when COUT is initially being charged. Voltage droop at the V1 pin can result in repeated switchover between V1 and V2 if built-in V1 (ADJ) hysteresis is insufficient. The LTC4420 temporarily turns off its active power path during input shorts or brownout conditions if the input supply falls below OUT by 0.7V. If the primary input supply becomes invalid, switchover to the backup supply occurs. The power path is reactivated when the input recovers to within 0.7V of the output. Figure 8 shows the response of the LTC4420 to a brownout and recovery on V1 where switchover to V2 does not occur as V1 stays above 1.8V. When V1 falls, OUT gets disconnected from V1 and is slowly discharged by load resistance ROUT. When V1 recovers, the power path is reactivated and OUT tracks V1. In Figure 9, when V1 falls, OUT gets disconnected from V1 as V1 drops below the switchover threshold. When V1 recovers, it needs to be qualified for 64ms before it is reconnected to OUT. OUT gets discharged by ROUT and is connected to V2 once its voltage is 50mV less than V2. 4420f For more information www.linear.com/LTC4420 15 LTC4420 Applications Information 2. Once V2OK is asserted high, drive it below 50mV. V1 5V/DIV 3. Power up V1 and ADJ for at least 94ms. Complete steps 2 and 3 within 80s of V2OK asserting high. Freshness seal is enabled. V2 5V/DIV 1 OUT 5V/DIV COUT = 10µF ROUT = 100Ω 100µs/DIV 2 3 1.8V V2 4420 F08 Figure 8. Voltage Waveforms During a Brownout on V1 That Does Not Result in Switchover to V2. Switchover Threshold = 1.8V 0.48V V2UV DRIVEN LOW EXTERNALLY V2OK 1.8V V1 5V/DIV V1 1.116V 94ms V2 5V/DIV ADJ OUT 5V/DIV COUT = 10µF ROUT = 100Ω 100µs/DIV 4420 F10 < 80s Figure 10. Freshness Seal Engage Procedure 4420 F09 Figure 9. Voltage Waveforms When a Brownout on V1 Results in Switchover to V2. Switchover Threshold = 3V Reverse Voltage Blocking The LTC4420 blocks reverse voltages on supply pins V1 and V2 up to –15V relative to GND and up to –39V relative to OUT. Transient voltage suppressors (TVS) connected to V1 and V2 must be bidirectional and capacitors connected to these pins must be rated to handle reverse voltages. A reverse voltage on V2 does not disrupt V1 operation and vice-versa. Freshness Seal Mode Freshness seal mode prevents V2 battery discharge by keeping V2 disconnected from OUT even if V1 is absent or invalid. Very little current is drawn from V2—typically just 120nA. The following sequence (refer to Figure 10) puts the LTC4420 in freshness seal mode: 1. Power up V2 and V2UV. FSEAL ENABLED Engage this mode if V2 is a backup battery either during storage or during shipment. Once freshness seal has been engaged, if V1 is disconnected, V2 stays disconnected from OUT. Freshness seal is automatically disabled the next time V1 is revalidated. Limit V2OK pin capacitance to less than 10nF in order to prevent freshness seal mode from accidentally being engaged. Design Example In Figure 11, the LTC4420 prioritizes between a 5V supply connected to V1 and a 7.4V 2-cell Li-Ion battery connected to V2. The system is designed to switch OUT to V2 when V1 drops below 4V, provide early power failure warning when V1 drops below 4.5V and disconnect the backup battery voltage when it drops below 6V. Maximum anticipated load current is 100mA and maximum allowed output droop is 100mV. Output rising slew rate is limited to <0.1V/µs and V1 and V2 input capacitances are limited to 10µF to avoid large inrush current. 1% tolerance resistors are used ADJ, CMP1 and V2UV pin leakages and GNDSW VOL are ignored as their design impact is small. 4420f 16 For more information www.linear.com/LTC4420 LTC4420 Applications Information 5V INPUT V1 RSN1 0.5Ω R3 365k C1 2.2µF OUT COUT 15µF LTC4420 ADJ R6 1M V2TEST OUT R7 1M R2 88.7k R1 44.2k + CMP1 V2DIS CMPOUT1 PFV1 V2OK V2UV V2 2-CELL Li-Ion 7.4V R5 1.37M R4 95.3k C2 2.2µF First choose total resistive divider current to be ~10µA for V1 and 5µA for V2. Since the V2 divider is pulsed with a maximum duty cycle of 0.1%, average V2 divider current is negligible. For the 5V supply, this results in: 5V = 500kΩ 10µA (14) Since desired switchover threshold, VSW1, and total divider impedance are known, use equation 1 to first calculate R3. Using R3 and equation 2, calculate R1 and R2. Rewriting equation 1 results in: (R1+R2) = VTHA • (R1+R2+R3) VSW1 (15) Using (R1+R2+R3) = 500kΩ from equation 14, results in: (R1+R2) = 1.047V • 500kΩ = 130.9kΩ 4V (16) R3 ~ (500kΩ – 130.9kΩ) = 369.1kΩ (17) Using the nearest 1% resistor value yields R3 = 365kΩ. Rearranging equation 2, results in: (18) R1= 0.387V • ( 500kΩ ) 4.5V (19) A similar procedure is used to calculate R4 and R5 using equation 3 and total divider current. Resistance of the GNDSW pull-down, typically 120Ω, is neglected as it is small compared to R4 and R5. The design equations are shown below. 4420 F11 Figure 11. Design Example R1+R2+R3 = VTHC • (R1+R2+R3) VPFV1 Solving equations 16 and 19 results in R1= 43.3kΩ and R2 = 87.6kΩ. Using the nearest 1% resistors results in R2 = 88.7kΩ. Recalculating equation 1 using calculated R2 and R3 values and using standard 1% resistor values close to 43.3kΩ for R1 results in R1= 44.2kΩ. V2UV GNDSW GND R1= R4+R5 = 7.4V = 1.48MΩ 5µA (20) as desired current in the divider is 5µA. Rewriting equation 3 neglecting pin leakage and assuming R5>>R4 results in: R4 = VTHC • (R4+R5) VV2UV (21) R4 = 0.387V •1.48MΩ 6V (22) Solving equations 20 and 22 results in R4 = 96.2kΩ and R5 = 1.38MΩ. Choosing the nearest 1% resistor results in R4 = 95.3kΩ and R5 = 1.37MΩ. COUT affects both OUT droop during switchover as determined by equation 4 and OUT rising slew rate as determined by equation 9. Calculate minimum COUT required to meet desired output droop and slew rate specifications using equations 8 and 9 and size COUT to be the larger of the two values. 4420f For more information www.linear.com/LTC4420 17 LTC4420 Applications Information COUT required to limit OUT droop to < 100mV is given by equation 8, COUT ≥ COUT ( tPDA + tSWITCH ) •ILOAD 100mV (23) (7.3µs + 2.5µs) • 0.1A = 9.8µF ≥ 100mV (24) COUT required to limit OUT slew rate to < 0.1V/µs is given by equation 9, COUT ≥ ILIM = 11µF 0.1V/µs (25) Choose a COUT capacitor whose minimum value is 11µF accounting for voltage and temperature coefficients. Do this for other capacitors as well. Assuming correct PCB layout, choose C1 to be 2.2µF, which is ~1/5th of COUT to suppress inductive transients. Also snub C1 with a 0.5Ω resistor to prevent ringing. Layout Consideration Make power and ground traces as wide as possible. Place bypass capacitors, snubbers and TVS devices as close to the pin as possible to reduce power path resistance and parasitic inductance. These result in smaller overvoltage transients and improved overvoltage protection. Place resistive dividers close to the pins to improve noise immunity. Use a 4-layer board if possible with layer 2 as dedicated GND and solder the exposed pad to a large PCB GND trace for better heat dissipation. A partial layout for a 2-layer PCB is shown in Figure 12. GND GND C1 V1 C2 V2 LTC4420 OUT GND COUT 4419 F12 Figure 12. Recommended 12-Lead MSE Layout for a 2-Layer PCB 4420f 18 For more information www.linear.com/LTC4420 LTC4420 Applications Information Depending on the difference between input and output voltages, the LTC4420’s internal power dissipation can be high when operating in current limit mode. This usually occurs when a large COUT is being charged either during initial power up or when OUT switches over to a higher supply. The situation is worsened if there is a DC load on OUT, as this reduces the current available to charge COUT. In such cases, self heating can cause power path turn-off due to activation of the thermal protection circuitry. The power path is reactivated when die temperature drops to a safe value. This process can repeat indefinitely if COUT is discharged fully by load current IOUT in the interval when the power path is off. COUT < 500µF if possible. If a larger COUT is necessary, use Figure 13 to choose COUT. Also follow PCB layout guidelines to improve heat dissipation. 60k ILOAD = 0 10k COUT (µF) THERMAL PROTECTION AND MAXIMUM COUT 1k 100 –40°C 25°C 85°C 5 10 15 VIN (V) Maximum allowed COUT to prevent activation of the thermal protection circuit depends on several factors such as input supply and output voltages, starting ambient temperature, heat dissipation in the PCB and DC output current. Choose 20 4420 F13 Figure 13. Maximum Allowed COUT vs Input Voltage for Different TA Typical Applications Battery Backup with Interface to Low Voltage Logic 5V TO 18V WALL ADAPTER RSN1 0.5Ω C1 10µF R3 365k R2 88.7k R1 44.2k 3.6V TO 18V BACKUP RSN2 0.5Ω C2 10µF R5 1M R4 150k V1 OUT ADJ COUT 10µF IN OUT LTC1763-3.3V SHDN GND LTC4420 CMP1 C3 10µF R6 1M R7 1M R8 1M V2TEST CMPOUT1 V2 V2OK V2UV 3.3V V1UV SYSTEM V2OK V2DIS GNDSW GND SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.5V (V1 FALLING) V2OK THRESHOLD: V2 < 3V (V2 FALLING) 4420 TA02 4420f For more information www.linear.com/LTC4420 19 LTC4420 Typical Applications SuperCap Backup with SuperCap Charging L1 3.3µH C1 10µF 1.7V TO 5.5V INPUT C3 120pF R13 12.1k R14 127k SW1 RSENP RSENS 4.2V SW2 VOUT C2 940mF MID LTC3128 IN PROG MAXV GND 940mF FB RUN V1 V2 R5 1M R3 1M R11 1.87M R2 237k R12 301k R1 121k OUT LTC4420 R4 127k V2UV COUT 10µF R6 1M R7 1M R8 1M OUT V2TEST V2DIS GNDSW ADJ V2OK V2OK CMP1 CMPOUT1 V1UV GND 4420 TA03 SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) V2OK THRESHOLD: V2 < 3.5V (V2 FALLING) C2: MURATA DMF325R5H474M3DTA0 Triple Voltage Monitor + + 14.8V Li-Ion 9V ALKALINE C1 10µF C2 10µF R3 2M R1 191k R5 1M R4 59k V1 OUT ADJ CMP1 LTC4420 V2 R10 2M R7 1M R8 1M OUT R9 113k CMPOUT1 V2TEST COUT 10µF OUTUV V2DIS V2UV V2OK V2OK GNDSW GND SWITCHOVER THRESHOLD: V1 < 12V (V1 FALLING) V2OK THRESHOLD: V2 < 7V (V2 FALLING) OUTUV THRESHOLD: OUT < 7.5V (OUT FALLING) 4420 TA04 4420f 20 For more information www.linear.com/LTC4420 LTC4420 Typical Applications Early Power Failure Warning with Low Battery Indication L1, 10µH C4 0.1µF SW1 BST1 5V TO 15V INPUT C5 0.1µF SW2 VIN TO OTHER CIRCUITS BST2 LTC3111 VOUT COMP C8 10µF R13 1M R14 137k FB SNSGND V1 R8 20k C9 18pF C6 39pF RUN 12V C7, 1nF R12, 44.2k VCC R6 1M ADJ R2 75k R11 158k C3 1µF PWM R10 2.21M CMP1 4-CELL 14.8V Li-ION R7 1M COUT 10µF R8 1M LTC4420 R1 41.2k + OUT OUT C1 22µF R3 1M C2 10µF R5 2M R4 66.5k PFV1, V1 POWER FAILURE THRESHOLD: V1 < 10.6V (V1 FALLING) SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING) V2OK THRESHOLD: V2 < 12V (V2 FALLING) V2 V2UV V2TEST V2DIS CMPOUT1 PFV1 V2OK V2OK GNDSW GND 4420 TA05 Prioritization with Failsafe Backup Supply DS BAT54 COIN CELL 3V 12V WALL ADAPTER RSN1 0.5Ω C1 10µF R3 1M R2 75k R1 41.2k + 2-CELL Li-Ion 7.4V C2 10µF R5 1.37M R4 95.3k V1 OUT ADJ OUT R7 1M V2TEST R8 1M CMPOUT1 PFV1 V2OK V2UV CMP1 COUT 10µF LTC4420 V2 V2DIS V2UV GNDSW GND PFV1 THRESHOLD: V1 < 10.6V (V1 FALLING) SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING) V2UV THRESHOLD: V2 < 6V (V2 FALLING) 4420 TA06 4420f For more information www.linear.com/LTC4420 21 LTC4420 Package Description Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings. DD Package 12-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1725 Rev A) R = 0.115 TYP 7 0.40 ±0.10 12 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 2.38 ±0.05 1.65 ±0.05 3.00 ±0.10 (4 SIDES) 2.38 ±0.10 1.65 ±0.10 6 0.25 ±0.05 PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) PACKAGE OUTLINE 0.200 REF 0.45 BSC 1 0.23 ±0.05 0.45 BSC 0.75 ±0.05 2.25 REF 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 – 0.05 (DD12) DFN 0106 REV A BOTTOM VIEW—EXPOSED PAD NOTE: 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE 2. DRAWING NOT TO SCALE TOP AND BOTTOM OF PACKAGE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4420f 22 For more information www.linear.com/LTC4420 LTC4420 Package Description Please refer to http://www.linear.com/product/LTC4420#packaging for the most recent package drawings. MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 5.10 (.201) MIN 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 6 1 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 3.20 – 3.45 (.065 ±.004) (.126 – .136) 12 0.65 0.42 ±0.038 (.0256) (.0165 ±.0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 ±0.076 (.016 ±.003) REF 12 11 10 9 8 7 DETAIL “A” 0° – 6° TYP 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MSE12) 0213 REV G 4420f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4420 23 LTC4420 Typical Application High Efficiency Backup C4 22nF RSN1 0.5Ω C1 10µF R3 1M R2 237k R1 121k V1 OUT ADJ COUT 10µF V2TEST R12 1.1M BST1 SW1 VIN RUN R11 1.05M LTC4420 CMP1 RUN MPPC VS1 VS2 VCC SW2 BST2 OUT 5V C6 10µF R7 1M R8 1M LTC3129-1 SYSTEM 5V WALL ADAPTER C5 22nF L1 3.3µH PWM GND PGND VS3 C3 2.2µF + 2-CELL 7.4V Li-Ion C2 10µF R5 1.37M R4 95.3k V2 V1UV CMPOUT1 V2UV V2OK V2UV V2DIS GNDSW GND R13 1M SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) V2UV THRESHOLD: V2 < 6V (V2 FALLING) 4420 TA07 Related Parts PART NUMBER DESCRIPTION COMMENTS LT 1763 500mA, Low Noise Micropower LDO Regulators VIN: 1.8V to 20V, 12-DFN, 8-SO Packages LTC2952 Pushbutton PowerPath Controller with Supervisor VIN: 2.7V to 28V, On/Off Timers, ±8kV HBM ESD, TSSOP-20 and QFN-20 Packages LTC3103 15V, 300mA Synchronous Step-Down DC/DC Converter VIN: 2.5V to 15V, DFN-10 and MSE-10 Packages LTC3129/LTC3129-1 15V, 200mA Synchronous Buck-Boost DC/DC Converter with 1.3µA Quiescent Current VIN: 1.92V to 15V, QFN-16 and MSE-16 Packages ® LTC3388-1/LTC3388-3 20V, 50mA High Efficiency Nanopower Step-Down Regulator VIN: 2.7V to 20V, DFN-10 and MSE-10 Packages LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal 2.6A P-Channel, 2.6V to 5.5V, 40μA IQ, SOT-23 Package LTC4412 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-Channel, 11μA IQ, SOT-23 Package LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-Channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35μA IQ per Supply, MSOP-10 Package LTC4417 3-Channel Prioritized PowerPath Controller Triple P-Channel Controller, 2.5V to 36V, SSOP-24 and QFN-24 Packages LTC4355 Positive High Voltage Ideal Diode-OR with Supply and Fuse Monitors Dual N-channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages LTC4359 Ideal Diode Controller with Reverse Input Protection N-channel, 4V to 80V, MSOP-8 and DFN-6 Packages 4420f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4420 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4420 LT 0816 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2016