Cypress CY7B9910-5SC Low skew clock buffer Datasheet

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1CY 7B9 92 0
CY7B9910
CY7B9920
Low Skew
Clock Buffer
Features
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•
•
•
•
•
•
•
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Block Diagram Description
All outputs skew <100 ps typical (250 max.)
15- to 80-MHz output operation
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50Ω terminated lines
Low operating current
24-pin SOIC package
Jitter: <200 ps peak to peak, <25 ps RMS
Compatible with Pentium™-based processors
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency. The operational range of the
VCO is determined by the FS control pin.
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low-skew system clock distribution. These multiple-output
clock drivers optimize the timing of high-performance computer systems. Eight individual drivers can each drive terminated
transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic
levels (CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL allows “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low-frequency clock that can be multiplied by virtually any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock speed
and flexibility.
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
CY7B9910/CY7B9920 to operate as explained above. (For
testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω
resistor. This will allow an external tester to change the state of
these pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase-locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
Logic Block Diagram
Pin Configuration
TEST
PHASE
FREQ
DET
FB
REF
Voltage
FILTER
Controlled
SOIC
Top View
Oscillator
FS
REF
VCCQ
FS
NC
VCCQ
VCCN
Q0
Q1
GND
Q2
Q3
VCCN
Q0
Q1
Q2
Q3
Q4
Q5
1
24
2
23
3
22
4
21
5
20
6
7
7B9910
7B9920
19
18
8
17
9
16
10
15
11
14
12
13
GND
TEST
NC
GND
VCCN
Q7
Q6
GND
Q5
Q4
VCCN
FB
Q6
Q7
7B9910–1
7B9910–2
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
November 1994 – Revised July 7, 1997
CY7B9910
CY7B9920
Pin Definitions
Signal
Name
I/O
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
FS[9,10,11]
I
Three-level frequency range select.
TEST
I
Three-level select. See Test Mode section.
Q[0..7]
O
Clock outputs.
VCCN
PWR
Power supply for output drivers.
VCCQ
PWR
Power supply for internal circuitry.
GND
PWR
Ground.
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Commercial
DC Input Voltage............................................ –0.5V to +7.0V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Output Current into Outputs (LOW) ............................. 64 mA
Electrical Characteristics Over the Operating Range
CY7B9910
Parameter
Description
Test Conditions
VCC = Min., IOH = –16 mA
Min.
Max.
CY7B9920
Min.
Max.
2.4
Unit
VOH
Output HIGH Voltage
V
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
VCC
VCC –
1.35
VCC
V
VIL
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
V
VIHH
Three-Level Input HIGH
Voltage (Test, FS)[1]
Min. ≤ VCC ≤ Max.
VCC – 1V
VCC
VCC – 1V
VCC
V
VIMM
Three-Level Input MID
Voltage (Test, FS)[1]
Min. ≤ VCC ≤ Max.
VCC/2 –
500 mV
VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
VILL
Three-Level Input LOW
Voltage (Test, FS)[1]
Min. ≤ VCC ≤ Max.
0.0
1.0
0.0
1.0
V
IIH
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = Max.
10
µA
IIL
Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max., VIN = 0.4V
IIHH
Input HIGH Current
(Test, FS)
VIN = VCC
IIMM
Input MID Current
(Test, FS)
VIN = VCC/2
IILL
Input LOW Current
(Test, FS)
VIN = GND
VCC = Min., IOH =–40 mA
VCC –0.75
VCC = Min., IOL = 46 mA
0.45
V
VCC = Min., IOL = 46 mA
0.45
10
–500
200
–50
50
–200
2
µA
–500
–50
200
µA
50
µA
–200
µA
CY7B9910
CY7B9920
Electrical Characteristics Over the Operating Range (continued)
CY7B9910
Parameter
Description
Test Conditions
Min.
CY7B9920
Max.
Min.
Max.
Unit
–250
N/A
mA
mA
IOS
Output Short Circuit
Current[2]
VCC = Max., VOUT
= GND (25°C only)
ICCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max., Com’l
All Input
Mil/Ind
Selects Open
85
85
90
90
ICCN
Output Buffer Current per
Output Pair[3]
VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
14
19
mA
PD
Power Dissipation per
Output Pair[4]
VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
78
104[5]
mW
Capacitance[6]
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 5.0V
Max.
Unit
10
pF
Notes:
1. These inputs are normally wired to V CC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected
inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are
achieved.
2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short
circuit protected.
3. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+ .17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 3 for variable definition.
5. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
R1
CL
R2
3.0V
R1=130
R2=91
CL = 50 pF (CL = 30pF for –5 and – 2 devices)
(Includes fixture and probe capacitance)
2.0V
Vth =1.5V
0.8V
0.0V
2.0V
Vth =1.5V
0.8V
≤1ns
≤1ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
VCC
VCC
R1
CL
R1=100
R2=100
CL = 50 pF (CL =30 pF for –5 and – 2devices)
(Includes fixture and probe capacitance)
R2
80%
Vth = VCC/2
20%
0.0V
≤ 3ns
7B9910–5
80%
Vth = VCC/2
20%
≤ 3ns
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
3
CY7B9910
CY7B9920
Switching Characteristics Over the Operating Range[7]
CY7B9910–2[8]
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Min.
Typ.
CY7B9920–2[8]
Max.
Min.
FS = LOW[9, 10]
15
30
15
Typ.
Max.
Unit
30
MHz
FS = MID[9, 10]
25
50
25
50
FS = HIGH[9, 10, 11]
40
80
40
80[12]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
[13, 14]
tSKEW
Zero Output Skew (All Outputs)
tDEV
Device-to-Device Skew[14, 15]
tPD
Propagation Delay, REF Rise to FB Rise
tODCV
Output Duty Cycle Variation
tORISE
Output Rise Time[17, 18]
0.1
0.25
0.1
0.75
[16]
Time[17, 18]
tOFALL
Output Fall
tLOCK
PLL Lock Time[19]
tJR
Cycle-to-Cycle Output Jitter Peak to Peak
Description
Operating Clock
Frequency in MHz
ns
0.0
+0.25
–0.25
0.0
+0.25
ns
–0.65
0.0
+0.65
–0.65
0.0
+0.65
ns
0.15
1.0
1.2
0.5
2.0
2.5
ns
0.15
1.0
1.2
0.5
2.0
2.5
ns
0.5
0.5
ms
200
200
ps
25
25
ps
CY7B9910–5
Parameter
ns
0.75
–0.25
RMS
fNOM
0.25
Min.
Typ.
CY7B9920–5
Max.
Min.
FS = LOW[9, 10]
15
30
15
Typ.
Max.
Unit
30
MHz
FS = MID[9, 10]
25
50
25
50
FS = HIGH[9, 10, 11]
40
80
40
80[12]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
Outputs)[13, 14]
tSKEW
Zero Output Skew (All
tDEV
Device-to-Device Skew[8, 15]
tPD
Propagation Delay, REF Rise to FB Rise
–0.5
0.0
+0.5
–0.5
tODCV
Output Duty Cycle Variation[16]
–1.0
0.0
+1.0
–1.0
0.15
1.0
1.5
0.15
1.0
1.5
Output Rise
tOFALL
Output Fall Time[17, 18]
tJR
PLL Lock
0.5
0.25
0.5
ns
1.0
ns
0.0
+0.5
ns
0.0
+1.0
ns
0.5
2.0
3.0
ns
0.5
2.0
3.0
ns
0.5
0.5
ms
200
200
ps
25
25
ps
1.0
Time[17, 18]
tORISE
tLOCK
0.25
Time[19]
Cycle-to-Cycle Output Jitter Peak to
Peak[8]
RMS[8]
Notes:
7. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
10. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and
FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/X when the device is configured for a frequency
multiplication by using external division in the feedback path of value X.
11. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V CC has reached 4.3V.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, etc.).
16. tODCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω
to 2.06V (CY7B9910) or VCC/2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
4
CY7B9910
CY7B9920
Switching Characteristics Over the Operating Range[7] (continued)
CY7B9910–7
Parameter
fNOM
Description
Min.
[9, 10]
Operating Clock
Frequency in MHz
FS = LOW
FS = MID[9, 10]
[9, 10, 11]
FS = HIGH
Typ.
CY7B9920–7
Max.
Min.
15
30
25
40
Typ.
Max.
Unit
15
30
MHz
50
25
50
80
40
80[12]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
tSKEW
Zero Output Skew (All Outputs)
[13, 14]
0.3
[8, 15]
0.75
0.3
ns
1.5
ns
tDEV
Device-to-Device Skew
tPD
Propagation Delay, REF Rise to FB Rise
–0.7
0.0
+0.7
–0.7
0.0
+0.7
ns
tODCV
Output Duty Cycle Variation[16]
–1.2
0.0
+1.2
–1.2
0.0
+1.2
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
tORISE
tOFALL
Output Rise
Output Fall
Time[17, 18]
Time[17, 18]
Time[19]
tLOCK
PLL Lock
tJR
Cycle-to-Cycle Output
Jitter
tJR
1.5
0.75
0.5
0.5
ms
Peak to Peak[8]
200
200
ps
RMS[8]
25
25
ps
AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tPD
tODCV
tODCV
FB
Q
tSKEW
tSKEW
tJR
OTHER Q
7B9910–8
5
CY7B9910
CY7B9920
REF
LOAD
Z0
FB
REF
FS
SYSTEM
CLOCK
LOAD
Q0
Q1
Z0
Q2
Q3
LOAD
Q4
Q5
Z0
Q6
Q7
LOAD
TEST
Z0
7B9910–9
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
Operational Mode Descriptions
nated transmission lines (with impedances as low as 50
ohms), allows efficient printed circuit board design.
Figure 1 shows the device configured as a zero-skew clock
buffer. In this mode the 7B9910/9920 can be used as the basis
for a low-skew clock distribution tree. The outputs are aligned
and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output and the
operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive termi-
Figure 2 shows the CY7B9910/9920 connected in series to
construct a zero-skew clock distribution tree between boards.
Cascaded clock buffers will accumulate low-frequency jitter
because of the non-ideal filtering characteristics of the PLL
filter. It is not recommended that more than two clock buffers
be connected in series.
LOAD
REF
Z0
FB
SYSTEM
CLOCK
REF
FS
LOAD
Z0
Q0
Q1
Q2
Q3
LOAD
Q4
Q5
Z0
Q6
Q7
FB
REF
FS
TEST
Z0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LOAD
LOAD
TEST
7B9910–10
Figure 2. Board-to-Board Clock Distribution
6
CY7B9910
CY7B9920
Ordering Information
Accuracy
(ps)
250
500
750
Ordering Code
CY7B9910–2SC
CY7B9920–2SC
CY7B9910–5SC
CY7B9910–5SI
CY7B9920–5SC
CY7B9920–5SI
CY7B9910–7SC
CY7B9910–7SI
CY7B9920–7SC
CY7B9920–7SI
Package
Name
S13
S13
S13
S13
S13
S13
S13
S13
S13
S13
Package Type
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38–00437–B
Package Diagram
24-Lead (300-Mil) Molded SOIC S13
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.