ON MC14555BDR2 Dual binary to 1-of-4 decoder/demultiplexer Datasheet

MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
•
•
•
•
•
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC1455XBCP
AWLYYWW
1
Diode Protection on All Inputs
Active High or Active Low Outputs
Expandable
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
16
SOIC–16
D SUFFIX
CASE 751B
1455XB
AWLYWW
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MC1455XB
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
VDD
Parameter
Unit
– 0.5 to +18.0
V
– 0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
Tstg
Storage Temperature Range
TL
Lead Temperature
(8–Second Soldering)
Vin, Vout
Iin, Iout
DC Supply Voltage Range
Value
Input or Output Voltage Range
(DC or Transient)
X
= Specific Device Code
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Package
Shipping
MC14555BCP
PDIP–16
2000/Box
°C
MC14555BD
SOIC–16
48/Rail
– 65 to +150
°C
MC14555BDR2
SOIC–16
2500/Tape & Reel
260
°C
MC14555BF
SOEIAJ–16
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
MC14555BFEL
SOEIAJ–16
See Note 1.
MC14556BCP
PDIP–16
2000/Box
MC14556BD
SOIC–16
48/Rail
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
MC14556BDR2
SOIC–16
2500/Tape & Reel
MC14556BF
SOEIAJ–16
See Note 1.
MC14556BFEL
SOEIAJ–16
See Note 1.
v
v
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
Device
1
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Publication Order Number:
MC14555B/D
MC14555B, MC14556B
PIN ASSIGNMENTS
MC14555B
MC14556B
EA
1
16
VDD
EA
1
16
VDD
AA
2
15
EB
AA
2
15
EB
BA
3
14
AB
BA
3
14
AB
Q0A
4
13
BB
Q0A
4
13
BB
Q1A
5
12
Q0B
Q1A
5
12
Q0B
Q2A
6
11
Q1B
Q2A
6
11
Q1B
Q3A
7
10
Q2B
Q3A
7
10
Q2B
VSS
8
9
Q3B
VSS
8
9
Q3B
TRUTH TABLE
Inputs
Enable
Outputs
Select
MC14555B
MC14556B
E
B
A
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X = Don’t Care
BLOCK DIAGRAM
MC14555B
2
A
3
B
1
E
14
A
13
B
15
E
MC14556B
Q0
Q1
Q2
Q3
4
5
6
7
2
A
3
B
1
E
Q0
Q1
Q2
Q3
12
11
10
9
14
A
13
B
15
E
VDD = PIN 16
VSS = PIN 8
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2
Q0
Q1
Q2
Q3
4
5
6
7
Q0
Q1
Q2
Q3
12
11
10
9
MC14555B, MC14556B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
“1” Level
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.85 µA/kHz) f + IDD
IT = (1.70 µA/kHz) f + IDD
IT = (2.60 µA/kHz) f + IDD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3
µAdc
MC14555B, MC14556B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time — A, B to Output
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
tPLH,
tPHL
Propagation Delay Time — E to Output
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
220
95
70
440
190
140
5.0
10
15
—
—
—
200
85
65
400
170
130
Unit
ns
ns
ns
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
20 ns
INPUT A HIGH, INPUT E LOW
20 ns
20 ns
A INPUTS
(50% DUTY CYCLE)
1
2f
90%
50%
10%
VDD
20 ns
VSS
INPUT B
VDD
tPHL
B INPUTS
(50% DUTY CYCLE)
VSS
OUTPUT Q1
VOL
VOH
90%
50%
10%
OUTPUT Q3
MC14556B
tTHL
tPLH
OUTPUT Q3
MC14555B
VOH
VOL
Figure 2. Dynamic Signal Waveforms
*
Q0
A
*
Q1
B
*
Q2
*
Q3
E
4
V
tTLH OL
tTHL
LOGIC DIAGRAM
(1/2 of Dual)
http://onsemi.com
VOH
tPHL
90%
50%
10%
tTLH
* Eliminated for MC14555B
VSS
tPLH
All 8 outputs connect to respective CL loads.
f in respect to a system clock.
Figure 1. Dynamic Power Dissipation Signal Waveforms
VDD
90%
50%
10%
MC14555B, MC14556B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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5
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14555B, MC14556B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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6
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14555B, MC14556B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
MC14555B, MC14556B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC14555B/D