PD - 96055
IRLR7807ZCPbF
IRLU7807ZCPbF
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l Lead-Free
HEXFET® Power MOSFET
VDSS
30V
RDS(on) max Qg (typ)
13.8m:
7.0nC
Benefits
l
l
l
Very Low RDS(on) at 4.5V VGS
Ultra-Low Gate Impedance
Fully Characterized Avalanche Voltage
and Current
D-Pak
IRLR7807ZCPbF
I-Pak
IRLU7807ZCPbF
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
f
30f
IDM
Pulsed Drain Current
170
PD @TC = 25°C
Maximum Power Dissipation
PD @TC = 100°C
Maximum Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
c
43
g
g
A
W
40
20
0.27
-55 to + 175
Soldering Temperature, for 10 seconds
W/°C
°C
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
Notes through
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g
Typ.
Max.
–––
3.75
–––
50
–––
110
Units
°C/W
are on page 11
1
02/23/06
IRLR/U7807ZCPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
23
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
11
13.8
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
–––
14.5
18.2
VGS = 4.5V, ID = 12A
–––
V
VGS = 0V, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.35
1.8
2.25
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-4.5
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
µA
VDS = 24V, VGS = 0V
nA
VGS = 20V
IGSS
gfs
Qg
–––
–––
1.0
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Forward Transconductance
51
–––
–––
e
e
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -20V
S
VDS = 15V, ID = 12A
Total Gate Charge
–––
7.0
11
Qgs1
Pre-Vth Gate-to-Source Charge
–––
1.8
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.7
–––
Qgd
Gate-to-Drain Charge
–––
2.7
–––
ID = 12A
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
1.8
–––
See Fig. 16
Qsw
–––
3.4
–––
Qoss
Output Charge
–––
4.0
–––
td(on)
Turn-On Delay Time
–––
7.1
–––
VDD = 15V, VGS = 4.5V
tr
Rise Time
–––
28
–––
ID = 12A
td(off)
Turn-Off Delay Time
–––
9.8
–––
tf
Fall Time
–––
3.5
–––
Ciss
Input Capacitance
–––
780
–––
Coss
Output Capacitance
–––
180
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
VDS = 15V
nC
nC
ns
VGS = 4.5V
VDS = 15V, VGS = 0V
e
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
Max.
Units
–––
28
mJ
–––
12
A
–––
4.0
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
f
IS
Continuous Source Current
–––
–––
43
ISM
(Body Diode)
Pulsed Source Current
–––
–––
170
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
23
35
ns
Qrr
Reverse Recovery Charge
–––
14
21
nC
ton
Forward Turn-On Time
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
e
TJ = 25°C, IF = 12A, VDD = 15V
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRLR/U7807ZCPbF
1000
1000
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM 2.25V
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM 2.25V
100
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
0.1
2.5V
0.01
100
10
2.5V
1
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 175°C
0.001
0.1
0.1
1
10
0.1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
Fig 2. Typical Output Characteristics
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000.0
ID, Drain-to-Source Current (Α)
1
VDS, Drain-to-Source Voltage (V)
T J = 25°C
100.0
T J = 175°C
10.0
1.0
VDS = 10V
20µs PULSE WIDTH
0.1
ID = 30A
VGS = 10V
1.5
1.0
0.5
2.0
3.0
4.0
5.0
6.0
7.0
8.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRLR/U7807ZCPbF
10000
12
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds
C rss = C gd
ID= 12A
SHORTED
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
C oss = C ds + C gd
1000
Ciss
Coss
Crss
100
8
6
4
2
10
0
1
10
100
0
4
VDS, Drain-to-Source Voltage (V)
12
16
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
1000.0
ISD, Reverse Drain Current (A)
8
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
100.0
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T J = 175°C
10.0
1.0
T J = 25°C
10
0.1
100µsec
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
0.1
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 24V
VDS= 15V
10
2.0
0.1
1.0
10.0
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U7807ZCPbF
2.5
50
VGS(th) Gate threshold Voltage (V)
LIMITED BY PACKAGE
ID , Drain Current (A)
40
30
20
10
0
2.0
ID = 250µA
1.5
1.0
25
50
75
100
125
150
175
-75 -50 -25
T C , Case Temperature (°C)
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
τJ
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
Ci= τi/Ri
Ci= i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
1.796
0.000267
1.112
0.000607
0.842
0.004249
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U7807ZCPbF
15V
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
DRIVER
L
VDS
120
TOP
100
BOTTOM
ID
3.0A
1.4A
12A
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
VGS
Current Sampling Resistors
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRLR/U7807ZCPbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D=
Period
V DD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRLR/U7807ZCPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞
⎞ ⎛
Qgs 2
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRLR/U7807ZCPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
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IRLR/U7807ZCPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
(;$03/( 7+,6,6$1,5)8
:,7+$66(0%/<
/27&2'(
$66(0%/('21::
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IRLR/U7807ZCPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.39mH, RG = 25Ω,
IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/06
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