High-Performance Regulators for PCs Switching Regulator with MOS FET for DDR-SDRAM Cores BD95513MUV No.10030EAT37 ●Description BD95513MUV is a switching regulator capable of supplying high current output (up to 3A) at low output voltages (0.7V~5.0V) over a broad range of input voltages (4.5V~28V). The regulator features an internal N-MOSFET power transistor for high 3 TM efficiency and low space consumption, while incorporating ROHM’s proprietary H Reg control mode technology, yielding the industry’s fastest transient response time against load changes. SLLMTM (Simple Light Load Mode) technology is also integrated to improve efficiency when powering lighter loads, as well as soft start, variable frequency, short-circuit protection with timer latch, over-voltage protection, and REF functions. This regulator is suited for PC applications. ●Features 1) Internal low ON-resistance power N-MOSFET 2) Internal 5V linear voltage regulator 3 TM 3) Integrated H Reg DC/DC converter controller 4) Selectable Simple Light Load Mode (SLLMTM), Quiet Light Load Mode (QLLM) and forced continuous mode 5) Built-in thermal shutdown, low input, current overload, output over- and under-voltage protection circuitry 6) Soft start function to minimize rush current during startup 7) Adjustable switching frequency (f = 200 kHz ~ 1000 kHz) 8) Built-in output discharge function 9) VQFN032V5050 package size 10) Tracking function 11) Internal bootstrap diode ●Applications Mobile PCs, desktop PCs, LCD-TV, digital household electronics www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/17 2010.10- Rev.A Technical Note BD95513MUV ●Absolute Maximum Ratings (Ta = 25℃) Parameter Symbol Ratings Unit Input Voltage 1 VCC 7 *1 V Input Voltage 2 VDD 7 *1 V Input Voltage 3 External VCC Voltage BOOT Voltage BOOT-SW Voltage Output Feedback Voltage SS/FS/MODE Voltage VREG Voltage EN/CTL Input Voltage PGOOD Voltage Output Current (Average) Power Dissipation 1 VIN *1 30 V *1 V 35 V *1 V FB VCC V SS/FS/MODE VCC V VREG VCC V 7 *1 V 7 *1 V EXTVCC 7 BOOT BOOT-SW 7 EN/CTL PGOOD 3 *1 ISW Pd1 A *2 W *3 *6 W 0.38 Power Dissipation 2 Pd2 0.88 Power Dissipation 3 Pd3 2.06 *4 *6 W Power Dissipation 4 Pd4 *5 *6 W Operating Temperature Range Topr -10 ~ +100 ℃ Storage Temperature Range Tstg -55 ~ +150 ℃ Junction Temperature Tjmax +150 ℃ 4.56 *1 Do not exceed Pd. *2 Ta ≧ 25 ℃ (IC only), power dissipated at 3.0 mW/℃. *3 Ta ≧ 25 ℃ (single-layer board, 20.2 mm2 copper heat dissipation pad), power dissipated at 7.0 mW/℃. *4 Ta ≧ 25 ℃ (4-layer board, 10.29 mm2 copper heat dissipation pad on top layer, 5505 mm2 pad on 2nd and 3rd layer), power dissipated at 16.5 mW/℃. *5 Ta ≧ 25 ℃ (4-layer board, all layers with 5505 mm2 copper heat dissipation pads), power dissipated at 36.5 mW/℃. *6 Values observed with chip backside soldered. When unsoldered, power dissipation is lower. ●Operating Conditions (Ta = 25℃) Parameter Symbol Ratings Min Max Unit Input Voltage 1 VCC 4.5 5.5 V Input Voltage 2 VDD 4.5 5.5 V Input Voltage 3 VIN 4.5 28 V EXTVCC 4.5 5.5 V BOOT 4.5 33 V SW -0.7 28 V BOOT-SW 4.5 5.5 V MODE Input Voltage MODE 0 5.5 V EN/CTL Input Voltage EN/CTL 0 5.5 V PGOOD Voltage PGOOD 0 5.5 V tonmin - 100 ns External VCC Voltage BOOT Voltage SW Voltage BOOT-SW Voltage Minimum On Time ★This product is not designed for use in a radioactive environment. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/17 2010.10- Rev.A Technical Note BD95513MUV ●Electrical Characteristics (Unless otherwise noted, Ta =25℃, AVIN =12V, VCC =VDD =VREG, EN/CTL=5V, MODE=0V, RFS =180kΩ) Limits Parameter Symbol Unit Condition Min. Typ. Max. [Whole Device] AVIN Bias Current 1 IIN1 - 1200 1800 µA AVIN Bias Current 2 IIN2 - 150 250 µA EXTVCC=5V IINstb - 0 10 µA CTL=EN=0V EN Low Voltage ENlow GND - 0.8 V EN High Voltage ENhigh 2.3 - 5.5 V EN Bias Voltage IEN - 12 20 µA CTL Low Voltage CTLlow GND - 0.8 V CTL High Voltage CTLhigh 2.3 - 5.5 V CTL Bias Current ICTL - 1 6 µA VREG Input Voltage VREG 4.90 5.00 5.10 V Maximum Current IREG 100 - - mA EVCC_UVLO 4.2 4.4 4.6 V REVCC - 1.0 2.0 Ω AVIN Threshold Voltage AVIN _ UVLO 4.1 4.3 4.5 V AVIN Hysteresis Voltage dAVIN _ UVLO 100 160 220 mV VREG Threshold Voltage VREG_ UVLO 4.1 4.3 4.5 V VREG Hysteresis Voltage dVREG_ UVLO 100 160 220 mV ton 400 500 600 nsec MAX ON Time tonmax 10.0 22.0 40.0 µsec MIN OFF Time toffmin - 450 550 nsec High-side ON Resistance Ron_high - 120 200 mΩ Low-side ON Resistance Ron_low - 120 200 mΩ SCP Startup Voltage VSCP 0.420 0.490 0.560 V Delay tSCP - 1 - ms AVIN Standby Current [5V Regulator] VIN=6.0 to 25V IREG=0 to 100mA [5V Switch] EXTVCC Input Threshold Voltage Switch Resistance EXTVCC:Sweep up [Under-Voltage Lockout Protection] 3 [H REG TM VCC:Sweep up VCC:Sweep down VREG:Sweep up VREG:Sweep down Control Block] ON Time [FET Block] [SCP Block] www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/17 When VFB: 30% down 2010.10- Rev.A Technical Note BD95513MUV Parameter Symbol Limits Unit Condition Min. Typ. Max. VOVP 0.812 0.840 0.868 V Charge Current Iss 1.4 2.2 3.0 µA Standby Voltage Vss_stb - - 100 mV IOCP 3 - - A Feedback Terminal Voltage 1 VFB1 0.693 0.700 0.707 V Feedback Terminal Voltage 2 VFB2 0.690 0.700 0.710 V IFB -100 0 100 nA SLLMTM Condition VthSLLM VCC-0.5 - VCC V SLLMTM Longest low-gate off time: ∞ Forced Continuous Mode VthCONT GND - 0.5 V Continuous mode VFB Power Good Low Voltage VFB PL 0.605 0.63 0.655 V When VFB: 10% down VFB Power Good High Voltage VFB PH 0.745 0.77 0.795 V When VFB: 10% up [Over-Voltage Protection Block] OVP Detect Voltage When VFB: 20% up [Soft Start Block] [Current Regulation Block] Maximum Output Current [Voltage Detection Block] Feedback Terminal Bias Current Ta =-10℃ to 100℃ Iout = 0A to 3A [MODE Block] [Power Good Block] www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/17 2010.10- Rev.A Technical Note BD95513MUV ●Reference Data 100 100 SLLMTM 100 SLLMTM 80 80 80 60 η [%] η [%] Continuous Mode QLLM 40 60 Continuous Mode η [%] 60 Continuous Mode 40 40 QLLM QLLM 20 20 20 0 0.01 0 0 0.1 1 10 0.01 Io [A] 2µsec/div VOUT (50mV/div) 0.1 1 0.01 10 Io [A] Fig.1 Io-Efficiency (VIN=7V,VOUT=2.5V) Fig.2 Io-Efficiency (VIN=12V,VOUT=2.5V) VOUT (50mV/div) Fig.4 Transient Response (VIN=7V, VOUT=2.5V) Fig.5 Transient Response (VIN=12V, VOUT=2.5V) Fig.6 Transient Response (VIN=19V, VOUT=2.5V) 2µsec/div 2µsec/div VOUT (50mV/div) VOUT (50mV/div) VOUT (50mV/div) SW (10V/div) SW (10V/div) SW (10V/div) IOUT (2A/div) IOUT (2A/div) Fig.8 Transient Response (VIN=12V, VOUT=2.5V) Fig.7 Transient Response (VIN=7V, VOUT=2.5V) 2µsec/div VOUT HG LG Fig.10 SLLMTM Mode (IOUT=0A) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Fig.9 Transient Response (VIN=19V, VOUT=2.5V) 2µsec/div 2µsec/div VOUT VOUT IL 2µsec/div IOUT (2A/div) 2µsec/div IOUT (2A/div) 10 SW (10V/div) IOUT (2A/div) IOUT (2A/div) 1 Fig.3 Io-Efficiency (VIN=19V,VOUT=2.5V) 2µsec/div VOUT (50mV/div) 0.1 Io [A] SW (10V/div) SW (10V/div) SLLMTM IL IL HG LG HG LG Fig.11 SLLMTM Mode (IOUT=0.4A) 5/17 Fig.12 1 SLLMTM Mode (IOUT=1A) 2010.10- Rev.A Technical Note BD95513MUV ●Reference Data 10µsec/div 200µsec/div 10µsec/div VOUT EN VOUT 2[V/div] SW PGOOD Fig.13 QLLM Mode (IOUT=0A) 2msec/div EN VOUT 2[V/div] Fig.15 PGOOD Rising Waveform Fig.14 QLLM Mode (IOUT=1A) 200µsec/div VOUT 2[V/div] VIN HG/LG SW IL 5[A/div] PGOOD VOUT Fig.17 SCP Timer Latch Waveform Fig.16 PGOOD Falling Waveform Fig.18 VIN change (5→19V) 400µsec/div VIN EN VREG 2[V/div] HG/LG VOUT 2[V/div] VOUT SW Fig.19 VIN change (19→5V) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Fig.20 EN wake up 6/17 2010.10- Rev.A Technical Note BD95513MUV ●Block Diagram VIN VREG 13 VCC 7 AVIN 16 SS VDD EN 10 8 VREG AVIN Reference Block UVLO Soft Start BOOT 5 SS VIN(4.5～28V) VIN 1 2 3 CTL VREG REF(0.7V) VREF×0.85 VSS×0.85 VOUT Delay PGOOD HG MODE EN Power Good H3RegTM Controller Block R 26 SW Q MODE S FB 18 AVIN MODE 28 Driver Circuit 30 FB 21 VDD 22 OVP VREG 31 LG REF×1.2 UVLO ILIM SCP TSD VOUT 29 SS EXTVCC 14 OCP 27 17 6 ILIM SCP 4 23 PGND 24 25 32 Thermal Protection 5V Reg 20 TSD EN/UVLO MODE 15 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. VREG 11 FS 9 7/17 MODE 12 CE 19 VOUT GND 2010.10- Rev.A Technical Note BD95513MUV ●Pin Configuration PGND PGND PGND 24 23 22 VDD CE VOUT FB REF 21 20 19 18 17 16 SS PGND 25 SW 26 15 VREG SW 27 14 EXTVcc SW 28 13 VCC SW 29 12 GND SW 30 11 FS SW 31 10 EN PGND 32 9 MODE 1 2 3 4 VIN VIN VIN VIN 5 6 7 8 BOOT PGOOD AVIN CTL *Connect the underside (FIN) to the ground terminal ●Pin Function Table PIN No. PIN Name 1-4 VIN 5 BOOT 6 PGOOD 7 AVIN Battery voltage sense 8 CTL 9 MODE 10 EN Linear regulator on/off (high = 5.0V, low = off) Control mode selection GND : Continuous Mode 3.0V : QLLM VCC : SLLMTM Enable output (high when VOUT ON) 11 FS Switching frequency adjustment(RFS = 30 k ~ 100 kΩ) 12 GND Sense ground 13 VCC Power supply input 14 EXTVCC 15 VREG 16 SS 17 REF 18 FB 19 VOUT 20 N.C. 21 VDD 22-25 PGND 26-31 SW 32 PGND Underside FIN www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. PIN Function Battery voltage input (4.5 ~ 28 V) HG driver power supply Power good output (high when output ±10% of regulation) External power supply input IC reference voltage (5.0V / 200mA) Soft start condenser input Output reference voltage (0.7 V) Feedback input (0.7 V) Voltage discharge output Power supply input (5 V) Power ground Output to inductor Power ground Substrate connection 8/17 2010.10- Rev.A Technical Note BD95513MUV ●Pin Descriptions ・VCC This pin supplies power to the IC’s internal circuitry, excluding the FET driver. The input supply voltage range is 4.5 to 5.5V, with a maximum current draw of 900µA. This pin should be bypassed with a capacitance of approximately 0.1µF. ・EN Enables or disables the switching regulator. When the voltage on this pin reaches 2.3 V or higher, the internal switching regulator is turned on. At voltages less than 0.8 V, the regulator is turned off. ・VDD This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak current when switching on or off, this pin should be bypassed with a capacitance of approximately 1 µF. ・VREG Output pin from the 5 V linear regulator. This pin also supplies power to the internal driver and control circuitry. VREG standby function is controlled by the CTL pin. The output supplies 5V at 100 mA and should be bypassed to ground using a 10 µF capacitor with a rating of X5R or X7R. ・EXTVCC External power supply input for the linear regulator. When the voltage on the EXTVCC pin exceeds 4.4 V, the regulator uses it in conjunction with other power sources to supply VREG. Leave the EXTVCC pin floating when not in use. ・REF Reference voltage output pin. The reference voltage is set internally by the IC to 0.7 V, and the IC works to keep VREF approximately equal to VFB. Variations in voltage levels on this pin affect the output voltage, so the pin should be bypassed with a 100 pF ~ 0.1 µF ceramic capacitor. ・SS Soft start/stop pin. When EN is set high, the capacitor between the internal current source and SS-GND controls the startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7 V), the output voltage is held at the same voltage as the SS pin. ・AVIN The BD95513MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this line should be bypassed with either a power capacitor or RC filter. ・FS Frequency-adjusting resistance input pin. Attaching a resistance of 30 k ~ 100 kΩ adjusts the switching frequency from 200 kHz ~ 1 MHz. ・BOOT This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC. The maximum voltage on this pin should not exceed +30 V vs. GND or +7 V vs. SW. When operating the switching regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (VIN + VDD) ~ VDD. ・PGOOD Power good indicator. This open-drain output should be connected via a 100 kΩ pull-up resistor. ・MODE Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode; when TM high, SLLM mode. ・CTL Linear regulator control pin. When voltage is 2.3 V or higher, a logic HIGH is recognized and the internal regulator (VREG = 5 V) is switched on. At voltages of 0.8 V or lower, a logic LOW is recognized and the regulator is switched off. However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW. ・FB Output voltage feedback input. VFB is held at 0.7 V by the IC. ・SW Output from the switching regulator to the inductor. This output swings from VIN ~ GND. The trace from the output to the inductor should be as short and wide as possible. ・VOUT Voltage output discharge pin. When EN is off, this output is pulled low. ・VIN Power supply input. The IC can accept any input from 4.5 V to 28 V. This pin should be bypassed directly to ground by a power capacitor. ・PGND Power ground terminal. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/17 2010.10- Rev.A Technical Note BD95513MUV ●Operation 3 TM CONTROLLA control system. The BD95513MUV is a switching regulator incorporating ROHM’s proprietary H Reg When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time interval. This improves the regulator’s transient response. When light-load mode is activated, the IC employs the Simple TM Light Load Mode (SLLM ) controller, further improving system efficiency. H3RegTM Control (Normal Operation) VFB When VFB falls below the reference voltage (0.7V), 3 TM the H Reg CONTROLLA is activated; VREF tON = HG VREF VIN × 1 [sec]・・・(1) f High gate output is determined by the above formula. LG (Rapid Changes in Load) VFB When VOUT drops due to a sudden change in load and the voltage remains below VREF after the preprogrammed tON time interval has elapsed, the system quickly restores VOUT by extending the tON time, thereby improving transient response. VREF Io tON+α HG LG Light Load Control TM (SLLM Mode) VFB VREF HG TM SLLM mode is enabled by setting the MODE pin to logic high. When the low gate is off and the current through the inductor is 0 TM function is (current flowing from VOUT to SW), the SLLM activated, disabling high gate output. If VFB falls below VREF again, the high gate is switched back on, lowering the switching frequency of the regulator and yielding higher efficiency when powering light loads. LG 0A (QLLM Mode) VFB VREF HG LG QLLM mode is enabled by setting the MODE pin to HiZ or middle voltage. When the lower gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), QLLM mode is activated, disabling high gate output. If VFB falls below VREF within a programmed time interval (typ. 40 µs), the high gate is switched on, but if VFB does not fall below VREF, the lower gate is forced on, dropping VFB and switching the high gate back on. The minimum switching frequency is set to 25 kHz (T = 40 µs), which keeps the regulator’s frequency from entering the audible spectrum but yields less efficient results than SLLMTM mode. 0A www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/17 2010.10- Rev.A Technical Note BD95513MUV ●Timing Chart ・Soft Start Function The soft start function is enabled when the EN pin is set high. Current control circuitry takes effect at startup, yielding a moderate “ramping start” in output voltage. Soft start timing and incoming current are given by equation (2) and (3) below: EN tSS Soft start period: SS tSS = VOUT VREF×Css [sec] ・・・(2) 2µA(typ) Rush current: IIN(ON)= Co×VOUT tss [A] ・・・(3) IIN (Css: soft start capacitor; Co: output capacitor) ・Timer Latch-type Short Circuit Protection VREF×0.70 VOUT 1ms SCP When output voltage falls to VREF x 0.70 or less, the output short circuit protection engages, turning the IC off after a set period of time to prevent internal damage. When EN is switched back on or when UVLO is cleared, output continues. The time period before shutting off is set internally at 1ms. EN/UVLO ・Output Over-Voltage Protection VOUT VREF×1.2 HG When output reaches or exceeds VREF x 1.2, the output over-voltage protection is engaged, turning the low-side FET completely on to reduce the output (low gate on, high gate off). When the output falls, it returns to standard mode. LG Switching www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/17 2010.10- Rev.A Technical Note BD95513MUV ●External Component Selection 1. Inductor (L) Selection The inductor’s value directly influences the output ripple current. As formula (4) indicates below, the greater the inductance or switching frequency, the lower the ripple current: ΔIL ΔIL= (VIN-VOUT)×VOUT [A]・・・(4) L×VIN×f The proper output ripple current setting is about 30% of maximum output current. VIN IL ΔIL=0.3×IOUTmax. [A]・・・(5) VOUT L L= Co (VIN-VOUT)×VOUT ΔIL×VIN×f [H]・・・(6) (ΔIL: output ripple current, f: switching frequency) Output ripple current * Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor’s rated current value. * To minimize possible inductor damage and maximize efficiency, choose an inductor with a low DCR and ACR resistance. 2. Output Capacitor Selection (CO) VIN When determining the proper output capacitor, be sure to factor in the equivalent series resistance (ESR) and equivalent series inductance (ESL) required to set the output ripple voltage at 20 mV or more. When selecting the limit of the inductor, be sure to allow enough margin for the output voltage. Output ripple voltage is determined by formula (7) below: ΔVOUT=ΔIL×ESR+ESL×ΔIL / TON・・・(7) VOUT L ESL ESR Co (ΔIL: Ouput ripple current, ESR: equivalent series resistance, ESL: equivalent series inductance) Output Capacitor Give special consideration to the conditions of formula (7) for output capacitance. Also, keep in mind that the output rise time must be established within the soft start timeframe. tss×(Ilimit-IOUT) Co≦ ・・・(8) VOUT tss: Soft start timeframe (see p. 10, equation (2)) Ilimit: Maximum output current Choosing a capacitance that is too large can cause startup malfunctions, or in some cases, may engage the short circuit protection. 3. Input Capacitor Selection (CIN) In order to prevent extreme over-current conditions, the input capacitor must have a low enough ESR to fully support a large ripple in the output. The formula for RMS ripple current (IRMS) is given by equation (9) below: VIN CIN VOUT L IRMS=IOUT× Co VIN(VIN-VOUT) VIN When VIN=2×VOUT, IRMS= [A]・・・(9) IOUT 2 Input Capacitor A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/17 2010.10- Rev.A Technical Note BD95513MUV 4. Frequency Adjustment The resistance connected to the FS terminal adjusts the on-time (tON) during normal operation as illustrated to the left. When tON, input voltage and VREF voltage are known, the switching frequency can be determined by the following formula: VREF F= ・・・(10) VIN×tON 500 450 5V 7V 12V 19V 25V From top: VIN= 400 Frequency [kHz] 350 300 However, real-life considerations (such as external MOSFET gate capacitance and switching time) must be factored in as they affect the overall switching rise and fall time. This leads to an increase in tON, lowering the total frequency slightly. 250 200 150 Additionally, when output current lingers around 0A in continuous mode, this “dead time” also has an effect upon tON, further lowering the switching frequency. Confirm the switching frequency by measuring the current through the coil (at the point where current does not flow backwards) during normal operation. 100 50 0 50 100 150 200 250 300 RFS[kΩ] The BD95513MUV operates by feeding the output voltage back through a resistive voltage divider. The output voltage is set by the following equation (see schematic below): 1 R1+R2 Output Voltage = × VREF (0.7V) + 2 ×ΔIL×ESR・・・(11) R2 The switching frequency is also amplified by the same resistive voltage divider network: R1+R2 ×(frequency set by RFS) [Hz]・・・(12) fsw = R2 VIN REF(0.7V) H3RegTM CONTROLLA VIN R Q SLLMTM S Driver Circuit Output Voltage ESR SLLM FB R1 R2 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/17 2010.10- Rev.A Technical Note BD95513MUV ●Evaluation Board Circuit (Frequency=300kHz Continuous Mode/QLLM/SLLMTM Example Circuit) VIN 12V VREG BD95513MUV U1 R1 R4 VREG 7 EN 13 VDD EN 8 VREG(5V) 14 EXTVCC R9 REF 6 C4 17 VIN PGND VOUT 1.8V/3A 22~25,32 PGOOD PGND REF(0.7V) VOUT GND FB 18 CE R8 GND PGND 19 C13 C1 C7 C6 PGND SW 26~31 SS/ 11 TRACK FS 12 PGND L1 VREG 16 R6 1~4 R7 VDD CTL D1 15 C10 CTL 5V C11 5 BOOT MODE C12 9 C14 MODE C5 21 C3 10 AVIN VCC 20 ●Evaluation Board Parts List Part No Value Company Part name Part No Value Company Part name U1 ROHM BD95513MUV R1 10Ω ROHM MCR03 D1 ROHM RB051L-40 R4 10Ω ROHM MCR03 C1 1µF KYOCERA CM105B105K06A R6 180KΩ ROHM MCR03 C3 1µF KYOCERA CM105B105K16A R7 31kΩ ROHM MCR03 C4 10µF KYOCERA CM316B106K06A R8 20kΩ ROHM MCR03 C5 1000pF MURATA GRM39X7R102K50 R9 100kΩ ROHM MCR03 C6 0.1µF KYOCERA CM105B104K06A L1 1.8µH SUMIDA CDEP104-1R8ML C7 1µF KYOCERA CM105B105K16A C14 470µF SANYO 2R5TPE470ML C11 10µF KYOCERA CM316B106M16A C15 1µF KYOCERA CM105B105K06A C12 0.1µF KYOCERA CM05B104K25A C16 1µF KYOCERA CM105B105K06A C13 220pF MURATA GRM39C0G221J50 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/17 2010.10- Rev.A Technical Note BD95513MUV ●Notes for use (1) Absolute maximum ratings Exceeding the absolute maximum ratings (such as supply voltage, temperature range, etc.) may result in damage to the device. In such cases, it may be impossible to identify problems such as open circuits or short circuits. If any operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power supply polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power supply lines The PCB layout pattern should be designed to provide the IC with low-impedance GND and supply lines. To minimize noise on the supply and GND lines, ground and power supply lines of analog and digital blocks should be separated. For all power lines supplying ICs, connect a bypass capacitor between the power supply and the GND terminal. If using electrolytic capacitors, keep in mind that their capacitance is reduced at lower temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use thermal design techniques that allow for a sufficient margin for power dissipation in actual operating conditions. (6) Inter-pin shorts and mounting errors Use caution when positioning he IC for mounting on PCBs. The IC may be damaged if there are any connection errors or if pins are shorted together. (7) Operation in strong electromagnetic fields Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to malfunction. (8) ASO When using the IC, set the output transistor so that it does not exceed either absolute maximum ratings or ASO. (9) Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit), which is designed to shut down the IC only to prevent thermal overloading. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC if this circuit is activated, or in environments in which activation of this circuitry can be assumed. TSD ON Temp. [℃] (typ.) Hysteresis Temp. [℃] (typ.) 175 15 BD95513MUV (10) Testing on application boards When testing the IC with application boards, connecting capacitors directly to low-impedance terminals can subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should be turned off completely before connecting it to or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/17 2010.10- Rev.A Technical Note BD95513MUV (11) Regarding IC input pins This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistance Transistor (NPN) P + N P+ P B C Pin A N Pin B Pin B Pin A E N N P+ N N B P P Substrate Parasitic Element C + N E P Substrate Parasitic Element GND P Parasitic Elements GND Parasitic Elements GND GND Example of IC Structure Other Adjacent Elements (12) Ground wiring traces When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. ●Power Dissipation 5.5 5.0 ① IC Only Θj-a = 328.9 ℃/W ② IC mounted on 1-layer board 2 (with 20.2 mm copper thermal pad) Θj-a = 142.0 ℃/W ③ IC mounted on 4-layer board 2 2 (with 20.2 mm pad on top layer, 5502 mm pad on layers 2,3) Θj-a = 60.7 ℃/W ④ IC mounted on 4-layer board (with 5505mm pad on all layers) Θj-a = 27.4 ℃/W ④4.56W Power Dissipation : Pd (W) 4.5 4.0 3.5 3.0 2.5 ③2.06W 2 2.0 1.5 ②0.88W 1.0 ①0.38W 0.5 0.0 0 25 50 75 100 125 150 Ambient Temperature: Ta(℃) VQFN032V5050 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/17 2010.10- Rev.A Technical Note BD95513MUV ●Ordering part number B D 9 Part No. 5 5 1 3 M Part No. U V - Package MUV : VQFN032V5050 E 2 Packaging and forming specification E2: Embossed tape and reel VQFN032V5050 <Tape and Reel information> 5.0 ± 0.1 5.0±0.1 1.0MAX 3.4±0.1 0.4 ± 0.1 1 8 9 32 16 25 24 0.75 0.5 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold ) (0.22) ( reel on the left hand and you pull out the tape on the right hand 3.4 ± 0.1 +0.03 0.02 -0.02 S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape 17 +0.05 0.25 -0.04 1pin Reel (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/17 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.10- Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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