Catalyst CAT25C256LAT2 128k/256k-bit spi serial cmos eeprom Datasheet

CAT25C128/256
CAT25C128/256
128K/256K-Bit SPI Serial CMOS EEPROM
FEATURES
■ Self-Timed Write Cycle
■ 5 MHz SPI Compatible
■ 64-Byte Page Write Buffer
■ 1.8 to 5.5 Volt Operation
■ Block Write Protection
■ Hardware and Software Protection
– Protect 1/4, 1/2 or all of EEPROM Array
■ Low Power CMOS Technology
■ 100,000 Program/Erase Cycles
■ SPI Modes (0,0 &1,1)
■ 100 Year Data Retention
■ Industrial and Automotive
■ RoHS-compliant packages
Temperature Ranges
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS EEPROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface
and is enabled through a Chip Select (CS). In addition
to the Chip Select, the clock input (SCK), data in (SI)
and data out (SO) are required to access the device.
The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
The CAT25C128/256 is designed with software and
hardware write protection features including Block Lock
protection. The device is available in 8-pin DIP, 8-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
CS
1
8
SO
2
3
4
7
6
5
WP
VSS
VCC
HOLD
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
SS
2
3
4
7
6
5
14
2
3
13
12
4
11
5
10
6
9
7
8
V CC
HOLD
NC
NC
NC
SCK
SI
SENSE AMPS
SHIFT REGISTERS
VCC
HOLD
SCK
SI
**CAT25C128 only.
NC
CS
SO
SO
NC
NC
WP
VSS
NC
NC
1
2
20
19
3
18
4
17
5
16
6
15
14
13
12
11
7
8
9
10
SO
SI
NC
V CC
HOLD
HOLD
NC
NC
SCK
SI
NC
NC
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
Function
Serial data Output
Serial Clock
Write Protect
Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
XDEC
EE PROM
ARRAY
DATA IN
STORAGE
PIN FUNCTIONS
Pin Name
SO
SCK
WP
VCC
VSS
CS
SI
HOLD
NC
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
CONTROL LOGIC
CS
SO
WP
8
1
TSSOP Package (Y20)**
DIP Package (L)
1
BLOCK DIAGRAM
TSSOP Package (Y14)**
SOIC Package
(V**, X)
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
For Ordering Information details, see page 11.
1
Document No. 1018, Rev. I
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating
for extended periods may affect device performance
and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS1) ................... –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
(3)
Parameter
Min.
Endurance
Max.
Units
100,000
Cycles/Byte
TDR(3)
Data Retention
100
Years
VZAP(3)
ESD Susceptibility
2000
Volts
ILTH(3)(4)
Latch-Up
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
2
mA
VCC = 5.0V
FCLK = 5MHz
ISB(5)
Power Supply Current
(Standby)
1
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
2
µA
ILO
Output Leakage Current
3
µA
VIL(3)
Input Low Voltage
-1
VCC x 0.3
V
VIH(3)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
0.4
V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
VCC - 0.8
V
0.2
VCC-0.2
VOUT = 0V to VCC,
CS = 0V
4.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
V
1.8V≤VCC<2.7V
V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and
JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Document No. 1018, Rev. I
2
CAT25C128/256
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
A.C. CHARACTERISTICS (CAT25C128)
Limits
VCC =
2.5V-5.5V
Vcc=
1.8V-5.5V
Max.
Min.
Min.
tSU
Data Setup Time
100
70
35
ns
tH
Data Hold Time
100
70
35
ns
tWH
SCK High Time
250
150
80
ns
tWL
SCK Low Time
250
150
80
ns
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
50
tRI(1)
Input Rise Time
tFI(1)
Input Fall Time
tHD
HOLD Setup Time
250
250
40
ns
tCD
HOLD Hold Time
250
250
40
ns
tWC
Write Cycle Time
10
10
5
ms
tV
Output Valid from Clock Low
250
250
80
ns
tHO
Output Hold Time
tDIS
Output Disable Time
250
250
100
ns
tHZ
HOLD to Output High Z
150
150
50
ns
tCS
CS High Time
1000
250
200
ns
tCSS
CS Setup Time
1000
250
100
ns
tCSH
tWPS
tWPH
CS Hold Time
WP Setup Time
WP Hold Time
500
50
50
250
50
50
100
50
50
ns
ns
ns
DC
UNITS Conditions
MHz
50
50
ns
2
2
2
µs
2
2
2
µs
0
DC
Max.
5
0
3
Min.
Test
SYMBOL PARAMETER
1
Max.
VCC =
4.5V-5.5V
0
CL = 50pF
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Document No. 1018, Rev. I
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)
Limits
Vcc=
1.8V-5.5V
VCC =
2.5V-5.5V
VCC =
2.7V-5.5V
Test
SYMBOL PARAMETER
Min. Max. Min.
tSU
Data Setup Time
500
100
70
35
ns
tH
Data Hold Time
500
100
70
35
ns
tWH
SCK High Time
2500
250
150
80
ns
tWL
SCK Low Time
2500
250
150
80
ns
fSCK
Clock Frequency
tLZ
HOLD to Output Low Z
tRI(3)
DC
0.2
DC
Max. Min.
VCC=
4.5V-5.5V
2.0
DC
Max. Min. Max. UNITS Conditions
2.5
DC
5
MHz
100
50
50
50
ns
Input Rise Time
2
2
2
2
µs
tFI(3)
Input Fall Time
2
2
2
2
µs
tHD
HOLD Setup Time
250
100
100
40
ns
tCD
HOLD Hold Time
250
100
100
40
ns
tWC
Write Cycle Time
10
10
10
5
ms
tV
Output Valid from Clock Low
250
200
200
80
ns
tHO
Output Hold Time
tDIS
Output Disable Time
250
200
200
100
ns
tHZ
HOLD to Output High Z
150
100
100
50
ns
tCS
CS High Time
100
100
100
100
ns
tCSS
CS Setup Time
100
100
100
100
ns
tCSH
tWPS
tWPH
CS Hold Time
WP Setup Time
WP Hold Time
100
50
50
100
50
50
100
50
50
100
50
50
ns
ns
ns
0
0
0
0
NOTE:
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 1018, Rev. I
4
ns
CL = 50pF
CAT25C128/256
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT25C128/256. During a read cycle, data
is shifted out on the falling edge of the serial clock.
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C128/
256 and CS high disables the CAT25C128/256. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway). The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low transition
on CS is required prior to any sequence being initiated. A
low to high transition on CS after a valid write sequence is
what initiates an internal write cycle.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
SCK
VIL
tH
tSU
VIH
tWL
VALID IN
SI
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
5
Document No. 1018, Rev. I
CAT25C128/256
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0.
9 illustrates hold timing sequence.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
HOLD
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C128/256 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK is
low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication, HOLD is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor. Figure
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address
Protected
Protection
0
0
None
No Protection
0
1
25C128: 3000-3FFF
25C256: 6000-7FFF
Quarter Array Protection
1
0
25C128: 2000-3FFF
25C256: 4000-7FFF
Half Array Protection
1
1
25C128: 0000-3FFF
25C256: 0000-7FFF
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
WP
WEL
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
Document No. 1018, Rev. I
6
CAT25C128/256
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect feature. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write protected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C128/256, followed
by the 16-bit address(the three Most Significant Bit is
don’t care for 25C256 and four most significant bits are
don't care for 25C128).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allowing
the read cycle to be continued indefinitely. The
readoperation is terminated by pulling the CS high.
DEVICE OPERATION
Write Enable and Disable
The CAT25C128/256 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
1
0
1
0
HIGH IMPEDANCE
SO
Figure 3. WRDI Instruction Timing
CS
SK
SI
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
7
Document No. 1018, Rev. I
CAT25C128/256
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in
Figure 5.
WRITE Sequence
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruction must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C128/256.
The CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don’t
care for 25C256 and four most significant bits are don't
care for 25C128), and then the data to be written.
Programming will start after the CS is brought high. Figure
6 illustrates byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
2
1
SK
OPCODE
SI
0
0
0
0
0
0
1
BYTE ADDRESS*
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
11
7
6
5
4
12
13
14
2
1
SCK
OPCODE
SI
0
0
0
0
0
DATA OUT
SO
HIGH IMPEDANCE
MSB
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
8
3
0
CAT25C128/256
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
Page Write
The CAT25C128/256 features page write capability.
After the first initial byte the host may continue to write
up to 64 bytes of data to the CAT25C128/256. After
each byte of data is received, six lower order address
bits are internally incremented by one; the high order
bits of address will remain constant. The only restriction
is that the 64 bytes must reside on the same page. If the
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
3
SK
OPCODE
SI
0
0
0
0
0
DATA IN
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
DATA IN
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 8. Page Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SK
DATA IN
OPCODE
SI
0
0
0
0
0
0
SO
1
0
ADDRESS
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
9
Document No. 1018, Rev. I
CAT25C128/256
DESIGN CONSIDERATIONS
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
to start an internal write cycle. Access to the array during
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
into the CAT25C128/256, and the serial output pin (SO)
will remain in a high impedence state until the falling
edge of CS is detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C128/256 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C128/256
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) — — — —
Figure 10. WP Timing
tWPS
tWPH
tCSH
SCK
WP
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
10
CAT25C128/256
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
Suffix
25C128
V
Product
Number
25C128: 128K
25C256: 256K
–G
- 1.8
I
Tape & Reel
T: Tape & Reel
2: 2000/Reel
3: 3000/Reel
Temperature Range
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚C to +105˚C)
E = Extended (-40˚C to +125˚C)
Package
L: PDIP
V: SOIC, JEDEC**
X: SOIC, EIAJ(4)
Y14: 14-Pin TSSOP**
Y20: 20-Pin TSSOP**
**CAT25C128 only
T3
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Operating Voltage
Blank (VCC = 2.5V to 5.5V
1.8 (VCC = 1.8V to 5.5V)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu pre-plated (PPF).
(3) The device used in the above example is a CAT25C128VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,
NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT25C256XI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
11
Document No. 1018, Rev. I
CAT25C128/256
REVISION HISTORY
Date
Rev.
Reason
8/5/2004
F
Updated Features
Updated DC Operating Characteristics table & notes
2/172005
G
Updated D.C. Operating Characteristics table
05/23/2005
H
Updated Reliability Characteristics table
10/13/06
I
Update Features
Update Description
Update Pin Configuration
Update Pin Funtions
Update D.C. Operating Characteristics (VCC Range)
Update A.C. Characteristics tables (VCC Range)
Update Ordering Information
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Document No. 1018, Rev. I
Publication #:
Revison:
Issue date:
Type:
12
1018
I
10/13/06
Final