LINER LTC1659 12-bit rail-to-rail micropower dac in msop package Datasheet

LTC1659
12-Bit Rail-to-Rail
Micropower DAC in
MSOP Package
FEATURES
DESCRIPTION
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The LTC®1659 is a single supply, rail-to-rail voltage output,
12-bit digital-to-analog converter (DAC) in an MSOP package. It includes a rail-to-rail output buffer amplifier and an
easy-to-use 3-wire cascadable serial interface.
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■
■
■
■
■
■
■
Buffered True Rail-to-Rail Voltage Output
Maximum DNL Error: 0.5LSB
12-Bit Resolution
Supply Operation: 3V to 5V
Output Swings from 0V to VREF
VREF Can Tie to VCC
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
Power-On Reset Clears DAC to 0V
3-Wire Cascadable Serial Interface
Low Cost
8-Lead SO and MSOP Packages
The LTC1659 output swings from 0V to REF. The REF input
can be tied to VCC which can range from 2.7V to 5.5V.
This allows a rail-to-rail output swing from 0V to VCC. The
LTC1659 draws only 250μA from a 5V supply.
Its guaranteed ±0.5LSB maximum DNL makes the LTC1659
excel in calibration, control and trim/adjust applications.
The low power supply current and the small MSOP
package make the LTC1659 ideal for battery-powered
applications.
APPLICATIONS
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, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail DAC
8
6
VCC
2 DIN
1 CLK
μP
3 CS/LD
0.5
REF
+
12-BIT
SHIFT
REG
AND
DAC
LATCH
12-BIT
DAC
VOUT
–
7
RAIL-TO-RAIL
VOLTAGE
OUTPUT
DNL ERROR (LSB)
2.7V TO 5.5V
Differential Nonlinearity
vs Input Code
0
4 DOUT
TO
OTHER
DACS
POWER-ON
RESET
–0.5
GND
5
0
1659 TA01
512 1024 1536 2048 2560 3072 3584 4095
CODE
1659 TA02
1659fa
1
LTC1659
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND ............................................... –0.5V to 7.5V
Logic Inputs to GND ................................. –0.5V to 7.5V
VOUT .................................................–0.5V to VCC + 0.5V
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC1659CS8 ............................................ 0°C to 70°C
LTC1659IS8 ......................................... –40°C to 85°C
LTC1659CMS8 ......................................... 0°C to 70°C
LTC1659IMS8 ...................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PIN CONFIGURATION
TOP VIEW
CLK 1
8
TOP VIEW
VCC
DIN 2
7
VOUT
CS/LD 3
6
REF
DOUT 4
5
GND
CLK
DIN
CS/LD
DOUT
1
2
3
4
8
7
6
5
VCC
VOUT
REF
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 140°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 160°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1659CS8#PBF
LTC1659CS8#TRPBF
1659
8-Lead Plastic SO
0°C to 70°C
LTC1659IS8#PBF
LTC1659IS8#TRPBF
1659I
8-Lead Plastic SO
–40°C to 85°C
LTC1659CMS8#PBF
LTC1659CMS8#TRPBF
LTCK
8-Lead Plastic MSOP
0°C to 70°C
LTC1659IMS8#PBF
LTC1659IMS8#TRPBF
LTCK
8-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
●
12
Bits
Monotonicity
●
12
Bits
DNL
Differential Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
INL
Integral Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
●
±0.5
LSB
●
±5.0
±5.5
LSB
LSB
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2
LTC1659
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Offset Error
Measured at Code 20
VOS TC
Offset Error Temperature Coefficient
VFS
Full-Scale Voltage
VFS TC
Full-Scale Voltage Temperature Coefficient
MIN
TYP
●
MAX
UNITS
±12
±18
mV
mV
±15
REF = 4.096V
●
4.070
4.060
4.095
4.095
μV/°C
4.120
4.130
10
V
V
ppm/°C
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
5.5
V
ICC
Supply Current
(Note 5)
●
240
450
μA
Short-Circuit Current Low
VOUT Shorted to GND
●
70
120
mA
Short-Circuit Current High
VOUT Shorted to VCC
●
65
120
mA
Output Impedance to GND
Input Code = 0
●
40
150
Ω
Output Line Regulation
Input Code = 4095, VCC = 4.5V to 5.5V
0.1
1.5
LSB/V
2.7
Op Amp DC Performance
AC Performance
Voltage Output Slew Rate
(Note 3)
Voltage Output Settling Time
(Notes 3, 4) to ±0.5LSB
●
0.5
Digital Feedthrough
1.0
V/μs
14
μs
0.3
nV • s
Reference Input
●
17
(Notes 6, 7)
●
0
Digital Input High Voltage
VCC = 5V
●
2.4
Digital Input Low Voltage
VCC = 5V
●
VOH
Digital Output High Voltage
VCC = 5V, IOUT = –1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 5V, IOUT = 1mA, DOUT Only
●
VIH
Digital Input High Voltage
VCC = 3V
●
RIN
REF Input Resistance
REF
REF Input Range
VIH
VIL
28
40
kΩ
VCC
V
0.8
V
Digital I/O
V
VCC – 1.0
V
0.4
2.0
V
V
VIL
Digital Input Low Voltage
VCC = 3V
●
VOH
Digital Output High Voltage
VCC = 3V, IOUT = –1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 3V, IOUT = 1mA, DOUT Only
●
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
μA
CIN
Digital Input Capacitance
(Note 7)
●
10
pF
0.6
VCC – 0.7
V
V
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3
LTC1659
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching (VCC = 4.5V to 5.5V
t1
DIN Valid to CLK Setup
●
40
ns
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High Time
(Note 7)
●
40
ns
t4
CLK Low Time
(Note 7)
●
40
ns
t5
⎯C⎯S/LD Pulse Width
(Note 7)
●
50
ns
t6
LSB CLK to ⎯C⎯S/LD
(Note 7)
●
40
ns
t7
⎯C⎯S/LD Low to CLK
(Note 7)
●
20
t8
DOUT Output Delay
CLOAD = 15pF
●
5
t9
CLK Low to ⎯C⎯S/LD Low
(Note 7)
●
20
ns
●
60
ns
ns
150
ns
Switching (VCC = 2.7V to 5.5V)
t1
DIN Valid to CLK Setup
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High Time
(Note 7)
●
60
ns
t4
CLK Low Time
(Note 7)
●
60
ns
t5
⎯C⎯S/LD Pulse Width
(Note 7)
●
80
ns
t6
LSB CLK to ⎯C⎯S/LD
(Note 7)
●
60
ns
t7
⎯C⎯S/LD Low to CLK
(Note 7)
●
30
t8
DOUT Output Delay
CLOAD = 15pF
●
10
t9
CLK Low to ⎯C⎯S/LD Low
(Note 7)
●
30
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity is defined from code 20 to code 4095 (full scale). See
Applications Information.
Note 3: Load is 5kΩ in parallel with 100pF.
ns
220
ns
ns
Note 4: DAC switched between all 1s and the code corresponding to VOS
for the part.
Note 5: Digital inputs at 0V or VCC.
Note 6: VOUT can only swing from (GND + |VOS|) to (VCC – |VOS|) when
output is unloaded.
Note 7: Guaranteed by design, not subject to test.
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4
LTC1659
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
Minimum Output Voltage vs
Output Sink Current
Differential Nonlinearity (DNL)
0.5
5
1
OUTPUT PULL-DOWN VOLTAGE (V)
4
2
DNL ERROR (LSB)
INL ERROR (LSB)
3
1
0
–1
–2
0
–3
–4
–5
0
512 1824 1536 2048 2560 3072 3584 4095
CODE
125°C
–55°C
0.2
25°C
0.3
0.2
–55°C
0.1
5
10
OUTPUT SINK CURRENT (mA)
15
1659 • G03
Supply Current vs Temperature
300
290
SUPPLY CURRENT (μA)
VCC – VOUT (V)
25°C
125°C
0.4
0
VCC = 5V
2
0.4
0.3
0.5
Supply Current vs
Logic Input Voltage
SUPPLY CURRENT (mA)
0.5
0.6
1659 • G02
Supply Headroom for Full Output
Swing vs Load Current
ΔVOUT < 1 LSB
CODE = ALL 1s
VOUT = 4.095V
0.7
512 1024 1536 2048 2560 3072 3584 4095
CODE
1659 • G01
0.6
0.8
0
–0.5
0
CODE = ALL ZEROS
VCC = 5V
0.9
1.6
1.2
0.8
280
270
260
VCC = 5.5V
VCC = 5.0V
250
VCC = 4.5V
240
0.4
0.1
230
0
0
0
5
10
LOAD CURRENT (mA)
15
1659 • G04
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
1659 • G05
220
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (C)
1659 • G06
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LTC1659
PIN FUNCTIONS
CLK (Pin 1): Serial Interface Clock. Internal Schmitt trigger
on this input allows direct optocoupler interface.
DOUT (Pin 4): Output of the Shift Register which Becomes
Valid on the Rising Edge of the Serial Clock.
DIN (Pin 2): Serial Interface Data. Data on the DIN pin is
latched into the shift register on the rising edge of the
serial clock.
GND (Pin 5): Ground.
⎯ ⎯S/LD (Pin 3): Serial Interface Enable and Load Control.
C
When ⎯C⎯S/LD is low the CLK signal is enabled, so the data
⎯ S
⎯ /LD is pulled high, data is loaded
can be clocked in. When C
from the shift register into the DAC register, updating the
DAC output and the CLK is disabled internally.
REF (Pin 6): Reference Input. This pin can be tied to VCC.
The output will swing from 0V to REF. The typical input
resistance is 28k.
VOUT (Pin 7): Buffered DAC Output.
VCC (Pin 8): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
Requires a bypass capacitor to ground.
BLOCK DIAGRAM
8 VCC
CLK 1
LD
DIN 2
12-BIT
SHIFT
REGISTER
DAC
REGISTER
12-BIT
DAC
+
7 VOUT
–
CS/LD 3
POWER-ON
RESET
DOUT 4
6 REF
5 GND
1659 BD
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LTC1659
TIMING DIAGRAM
t1
t2
t6
CLK
t4
t7
t3
t9
DIN
B11
MSB
B0
PREVIOUS WORD
CS/LD
DOUT
B0
LSB
B1
B10
t8
B11
PREVIOUS WORD
B10
t5
B1
B0
B11
CURRENT WORD
1659 TD
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔVOUT – LSB)/LSB
where ΔVOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specified
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go
below zero, the linearity is measured between full scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/4095)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/4096
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
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7
LTC1659
OPERATION
Serial Interface
Voltage Output
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first.
The DAC register loads the data from the shift register
when ⎯C⎯S/LD is pulled high. The CLK is disabled internally
when ⎯C⎯S/LD is high. Note: CLK must be low before ⎯C⎯S/LD
is pulled low to avoid an extra internal clock pulse.
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40Ω when driving a load
to the rails. The output can drive 1000pF without going
into oscillation.
The buffered output of the 12-bit shift register is available
on the DOUT pin which swings from GND to VCC. Multiple
LTC1659s may be daisy-chained together by connecting
the DOUT pin to the DIN pin of the next chip, while the CLK
and ⎯C⎯S/LD signals remain common to all chips in the
daisy chain. The serial data is clocked to all of the chips,
then the ⎯C⎯S/LD signal is pulled high to update all of them
simultaneously.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from the REF to VOUT. Please
note if REF is tied to VCC the output can only swing to
(VCC – VOS). See Applications Information.
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8
LTC1659
APPLICATIONS INFORMATION
error (FSE) is positive, the output for the highest codes
limits at VCC as shown is Figure 1c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to voltages within the supply range.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(1c)
VREF = VCC
OUTPUT
VOLTAGE
0
2048
INPUT CODE
4095
(1a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(1b)
1659 F01
Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve
(1a) Overall Transfer Function
(1b) Effect of Negative Offset for Codes Near Zero Scale
(1c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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9
LTC1659
TYPICAL APPLICATION
12-Bit, 3V to 5V Single Supply, Rail-to-Rail Voltage Output DAC
2.7V TO 5.5V
0.1μF
DIN VCC
REF
CLK
μP
LTC1659
OUTPUT
0V TO REF
VOUT
CS/LD
DOUT
GND
TO NEXT DAC FOR
DAISY-CHAINING
1659 TA03
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
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10
LTC1659
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.42 ± 0.038
(.0165 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
1
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8) 0307 REV F
1659fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1659
TYPICAL APPLICATION
Digitally Programmable Current Source
5V
0.1μF
CLK
μP
DIN
VCC
VS + 6V TO 100V
FOR RL ≤ 50Ω
RL
REF
LTC1659
VOUT
GND
DIN • 5
≈ 0mA TO 10mA
4096 • RA
+
LT®1077
CS/LD
IOUT =
Q1
2N3440
–
RA
510Ω
5%
1659 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,
Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V
5V to 15V Single Supply, Complete VOUT DAC in
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V
Output Swings from GND to REF. REF Input Can Be Tied
to VCC
LTC1450/LTC1450L
Single 12-Bit VOUT DACs with Parallel Interface
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V,
Internal 2.048V Reference Brought Out to Pin
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Low Power, Multiplying VOUT DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V
3V, Low Power, Complete VOUT DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V,
VCC: 4.5V to 5.5V
Low Power, Complete VOUT DAC in SO-8 Package with
Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
1659fa
12 Linear Technology Corporation
LT 0507 REV A• PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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