ON MC14022BDR2 Octal counter Datasheet

MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in
code converter. High–speed operation and spike–free outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positive–going edge of
the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
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MARKING
DIAGRAMS
Fully Static Operation
DC Clock Input Circuit Allows Slow Rise Times
Carry Out Output for Cascading
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4022B
Triple Diode Protection on All Inputs
16
PDIP–16
P SUFFIX
CASE 648
MC14022BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
14022B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Parameter
Value
Unit
– 0.5 to +18.0
V
– 0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
Symbol
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14022BCP
PDIP–16
2000/Box
MC14022BD
SOIC–16
2400/Box
MC14022BDR2
SOIC–16
2500/Tape & Reel
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
v
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14022B/D
MC14022B
PIN ASSIGNMENT
Q1
1
16
VDD
Q0
2
15
R
Q2
3
14
C
Q5
4
13
CE
Q6
5
12
Cout
NC
6
11
Q4
Q3
7
10
Q7
VSS
8
9
NC
NC = NO CONNECTION
BLOCK DIAGRAM
CLOCK
14
CLOCK
ENABLE
13
RESET
15
VDD = PIN 16
VSS = PIN 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
FUNCTIONAL TRUTH TABLE
(Positive Logic)
2
1
3
7
11
4
5
10
12
Clock
Clock
Enable
0
X
X
1
0
X
1
X
X
X
Reset
Output=n
0
0
0
0
0
0
1
n
n
n+1
n
n+1
n
Q0
X = Don’t Care. If n < 4 Carry = 1,
Otherwise = 0.
NC = PIN 6, 9
LOGIC DIAGRAM
11
1
Q4
5
Q1
7
Q6
Q3
CLOCK
14
13
CLOCK
ENABLE
15
RESET
VDD
VSS
C Q
C
D RQ
C Q
C
D RQ
Q0
2
Q5
4
http://onsemi.com
2
C Q
C
D RQ
C Q
C
D RQ
Q2
3
Q7
10
CARRY
12
MC14022B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
“1” Level
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (4.) (5.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.28 µA/kHz)f + IDD
IT = (0.56 µA/kHz)f + IDD
IT = (0.85 µA/kHz)f + IDD
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.00125.
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3
µAdc
MC14022B
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SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Reset to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
Propagation Delay Time
Clock to Cout
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
tPLH,
tPHL
Propagation Delay Time
Clock to Decode Output
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
tPLH,
tPHL
Turn–Off Delay Time
Reset to Cout
tPLH = (1.7 ns/pF) CL + 315 ns
tPLH = (0.66 ns/pF) CL + 142 ns
tPLH = (0.5 ns/pF) CL + 100 ns
tPLH
Clock Pulse Width
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
—
—
—
500
230
175
1000
460
350
ns
5.0
10
15
—
—
—
400
175
125
800
350
250
ns
5.0
10
15
—
—
—
275
125
95
1000
460
350
ns
5.0
10
15
—
—
—
400
175
125
800
350
250
tWH
5.0
10
15
250
100
75
125
50
35
—
—
—
ns
fcl
5.0
10
15
—
—
—
5.0
12
16
2.0
5.0
6.7
MHz
Reset Pulse Width
tWH
5.0
10
15
500
250
190
250
125
95
—
—
—
ns
Reset Removal Time
trem
5.0
10
15
750
275
210
375
135
105
—
—
—
ns
tTLH, tTHL
5.0
10
15
Clock Frequency
Clock Input Rise and Fall Time
—
No Limit
Clock Enable Setup Time
tsu
5.0
10
15
350
150
115
175
75
52
—
—
—
ns
Clock Enable Removal Time
trem
5.0
10
15
420
200
140
260
100
70
—
—
—
ns
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
http://onsemi.com
4
MC14022B
VDD
VSS
VDD
VSS
A
S1
B
Output
Sink Drive
Output
Source Drive
Outputs
(S1 to A)
Clock to desired
Output
(S1 to B)
Carry
Clock to Q5
thru Q7
(S1 to B)
S1 to A
VGS =
VDD
– VDD
VDS =
Vout
Vout – VDD
Vout
CLOCK Q0
ENABLE Q1
Q2
Q3
RESET Q4
Q5
Q6
Q7
CLOCK C
out
ID
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD
500 µF
0.01 µF
CERAMIC
ID
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
CLOCK
ENABLE
RESET
PULSE
GENERATOR
fc
CLOCK
CL
VSS
CL
CL
CL
CL
CL
CL
CL
CL
Figure 2. Typical Power Dissipation Test Circuit
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
C
R
MC14022B
CE
Q0 Q1 • • • Q6 Q7
7 DECODED
OUTPUTS
C
R
MC14022B
CE
Q0 Q1 • • • Q6 Q7
6 DECODED
OUTPUTS
C
R
MC14022B
CE
Q1 • • • Q6 Q7
6 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
Figure 3. Counter Expansion
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5
LAST STAGE
MC14022B
tWH
tWL
90%
CLOCK
trel
CLOCK
ENABLE
tsu
20 ns
trem
10%
20 ns
20 ns
20 ns
VDD
20 ns
VSS
tPLH
tPHL
tPLH
50%
tPLH
tPHL
tTHL
90%
Q1
VSS
VDD
RESET
Q0
VDD
50%
VSS
tPLH
tPHL
VOH
VOL
VOH
50%
10%
VOL
tTLH
VOH
Q2
tPLH
tPHL
VOL
tTLH
VOH
Q3
tPLH
tPHL
VOL
tTLH
VOH
Q4
tPLH
Q5
tTLH
tPHL
tPLH
VOL
tTLH
tTHL
tPHL
tTLH
tPHL
tTHL
VOH
Q6
VOL
tPLH
tPHL
VOH
Q7
Cout
tPHL
VOH
VOL
tTLH
tPLH
tTHL
VOL
VOH
tPHL
VOL
tTLH
Figure 4. AC Measurement Definition and Functional Waveforms
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6
tTHL
MC14022B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
–T–
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
M
T B
S
A
S
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14022B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
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MC14022B/D
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