GENERAL DESCRIPTION The AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking resolver-to-digital converter contained in a 40-lead DIP or 44terminal LCC ceramic package. It is manufactured on a BiMOS II process that combines the advantages of CMOS logic and bipolar high accuracy linear circuits on the same chip. The converter allows users to select their own resolution and dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The converter allows users to select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S80A converts resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver. A1 COS I/P ANALOG GND RIPPLE CLK DATA LOAD A2 SEGMENT SWITCHING R-2R DAC 16-BIT UP/DOWN COUNTER +12V –12V INTEGRATOR I/P DEMOD I/P REF I/P DEMOD O/P AC ERROR O/P AD2S80A SIN I/P SIG GND A3 INTEGRATOR O/P PHASE SENSITIVE DETECTOR VCO DATA TRANSFER LOGIC VCO I/P OUTPUT DATA LATCH 16 DATA BITS BYTE SELECT 5V DIG GND BUSY DIR INHIBIT APPLICATIONS DC Brushless and AC Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control Military Servo Control FUNCTIONAL BLOCK DIAGRAM ENABLE FEATURES Monolithic (BiMOS ll) Tracking R/D Converter 40-Lead DIP Package 44-Terminal LCC Package 10-,12-,14-, and 16-Bit Resolution Set by User Ratiometric Conversion Low Power Consumption: 300 mW Typ Dynamic Performance Set by User High Max Tracking Rate 1040 RPS (10 Bits) Velocity Output Industrial Temperature Range Versions Military Temperature Range Versions ESD Class 2 Protection (2,000 V Min) /883 B Parts Available SC1 SC2 a Variable Resolution, Monolithic Resolver-to-Digital Converter AD2S80A PRODUCT HIGHLIGHTS Monolithic. A one chip solution reduces the package size required and increases the reliability. Resolution Set by User. Two control pins are used to select the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing the user to use the AD2S80A with the optimum resolution for each application. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. The 10-, 12-, 14- or 16-bit output word is in a three-state digital logic available in 2 bytes on the 16 output data lines. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. An analog signal proportional to velocity is also available and can be used to replace a tachogenerator. Military Product. The AD2S80A is available processed in accordance with MIL-STD-883B, Class B. The AD2S80A operates over 50 Hz to 20,000 Hz reference frequency. MODELS AVAILABLE Information on the models available is given in the section “Ordering Information.” Low Power Consumption. Typically only 300 mW. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD2S80A–SPECIFICATIONS (typical at 25ⴗC unless otherwise noted) Parameter Conditions Min SIGNAL INPUTS Frequency Voltage Level Input Bias Current Input Impedance Maximum Voltage 50 1.8 Bandwidth1 ACCURACY Angular Accuracy Monotonicity Missing Codes (16-Bit Resolution) VELOCITY SIGNAL Linearity Reversion Error DC Zero Offset2 DC Zero Offset Tempco Gain Scaling Accuracy Output Voltage Dynamic Ripple Output Load INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs Hz V rms nA MΩ V pk 20,000 8.0 150 Hz V pk nA MΩ 1 +10 1040 260 65 16.25 LSB Degrees rps rps rps rps ⴞ8 +1 LSB ⴞ4 +1 LSB ⴞ2 +1 LSB arc min arc min arc min 4 1 Codes Code ⴞ3 ±2 6 ± 10 ± 10.5 1.5 1.0 % FSD % FSD mV µV/°C % FSD V % rms O/P kΩ ± 10.4 V mA 3 LSTTL 600 ns 35 110 ns 60 140 ns 60 (Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable –10 A, J, S B, K, T L, U Guaranteed Monotonic A, B, J, K, S, T L, U ±1 ±1 Over Full Range –22 1 mA Load Mean Value Overvoltage Protection Short Circuit O/P Protection Logic LO to Inhibit Logic LO Enables Position Output. Logic HI Outputs in High Impedance State ±8 ±9 ± 5.6 ±8 ±8 3 LOGIC LO MS Byte DB1–DB8, LS Byte DB9–DB16 LS Byte DB1–DB8, LS Byte DB9–DB16 Time to Data Available SHORT CYCLE INPUTS SC1 SC2 0 0 0 1 1 0 1 1 20,000 2.2 150 1.0 INHIBIT3 Sense Time to Stable Data BYTE SELECT Sense 2.0 60 50 1.0 10, 12, 14, and 16 Bidirectional Natural Binary ENABLE Time Unit 8 DIGITAL POSITION Resolution Output Format Load ENABLE3 Max 1.0 REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance CONTROL DYNAMICS Repeatability Allowable Phase Shift Tracking Rate Typ Internally Pulled High (100 kΩ) to +VS 10 Bit 12 Bit 14 Bit 16 Bit –2– REV. B AD2S80A Parameter DATA LOAD Sense BUSY3 Sense Width Load DIRECTION3 Sense Conditions Min Internally Pulled High (100 kΩ) to VS. Logic LO Allows Data to be Loaded into the Counters from the Data Lines Typ Max Unit 150 300 ns 600 1 ns LSTTL 3 LSTTL 3 LSTTL Logic HI When Position O/P Changing 200 Use Additional Pull-Up Logic HI Counting Up Logic LO Counting Down Max Load RIPPLE CLOCK3 Sense Width Reset Load DIGITAL INPUTS High Voltage, VIH Low Voltage, VIL DIGITAL INPUTS High Current, IIH Low Current, IIL DIGITAL INPUTS Low Voltage, VIL Low Current, IIL DIGITAL OUTPUTS High Voltage, VOH Low Voltage, VOL THREE-STATE LEAKAGE Current IL Logic HI All 1s to All 0s All 0s to All 1s Dependent on Input Velocity Before Next Busy INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 10.8 V, VL = 5.0 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.0 V 300 2.0 0.8 V INHIBIT, ENABLE DB1–DB16 ± VS = ± 13.2 V , VL = 5.5 V INHIBIT, ENABLE DB1–DB16, Byte Select ± VS = ± 13.2 V, VL = 5.5 V ⴞ100 µA ⴞ100 µA ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V 1.0 V –400 µA DB1–DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1–DB16 RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA 2.4 DB1–DB16 Only ± VS = ± 12.0 V, VL = 5.5 V VOL = 0 V ± VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V NOTES 1 Refer to small signal bandwidth. 2 Output offset dependent on value for R6. 3 Refer to timing diagram. Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. REV. B V –3– V 0.4 V ± 100 µA ± 100 µA AD2S80A–SPECIFICATIONS (typical at 25ⴗC unless otherwise noted) Parameter RATIO MULTIPLIER AC Error Output Scaling PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Increase Decrease Conditions Min 10 Bit 12 Bit 14 Bit 16 Bit Max Unit 177.6 44.4 11.1 2.775 w.r.t. REF w.r.t. REF –0.882 –0.9 60 1 At 10 kHz ± VS = ± 10.8 V dc ±7 ± VS = ± 12 V dc Positive Direction Negative Direction 7.1 7.1 mV –0.918 ± 0.02 150 V rms/V dc V rms/V dc nA MΩ V 63 5 150 7.9 7.9 1.1 8.7 8.7 ±8 +10.8 –10.8 +5 ± VS @ ± 12 V ± VS @ 13.2 V +VL @ ± 5.0 V 12 100 1 60 +0.5 –8.0 –8.0 +2.0 1 70 –1.22 +VS –VS +VS –VS mV/Bit mV/Bit mV/Bit mV/Bit ±8 57 Input Offset Voltage Input Bias Current Input Bias Current Tempco Input Voltage Range Linearity of Absolute Rate Full Range Over 0% to 50% of Full Range Reversion Error Sensitivity of Reversion Error to Symmetry of Power Supplies POWER SUPPLIES Voltage Levels +VS –VS +VL Current ± IS ± IS ± IL Typ ⴞ12 ⴞ19 ⴞ0.5 dB nA/LSB mV nA V MHz kHz/µA kHz/µA %/V %/V %/V %/V mV nA nA/°C V 5 380 ±8 <2 <1 1.5 % FSD % FSD % FSD %/V of Asymmetry +13.2 –13.2 +13.2 V V V ⴞ23 ⴞ30 ⴞ1.5 mA mA mA Specification subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S80A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B AD2S80A PIN CONFIGURATIONS RECOMMENDED OPERATING CONDITIONS Power Supply Voltage (+VS, –VS) . . . . . . . . . ± 12 V dc ± 10% Power Supply Voltage VL . . . . . . . . . . . . . . . . . . . 5 V dc ± 10% Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10% Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak Signal and Reference Harmonic Distortion . . . . . . . 10% (max) Phase Shift Between Signal and Reference . . . ± 10 Degrees (max) Ambient Operating Temperature Range Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C 40 DEMOD O/P REFERENCE I/P 1 DEMOD I/P 2 39 INTEGRATOR O/P AC ERROR O/P 3 38 INTEGRATOR I/P DIP (D) Package COS 4 37 VCO I/P ANALOG GND 5 36 –VS SIGNAL GND 6 35 RIPPLE CLK SIN 7 34 DIRECTION +VS 8 33 BUSY MSB DB1 9 32 DATA LOAD AD2S80A 31 SC2 TOP VIEW DB3 11 (Not to Scale) 30 SC1 DB2 10 ABSOLUTE MAXIMUM RATINGS l (with respect to GND) DB4 12 29 DIGITAL GND +VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc +VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V to –VS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW Operating Temperature Commercial (JD, KD, LD) . . . . . . . . . . . . . . . . 0°C to 70°C Industrial (AD, BD) . . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (SD, SE, TD, TE, UD, UE) . . . –55°C to +125°C θJC3 (40-Lead DIP 883 Parts Only) . . . . . . . . . . . . . . . 11°C/W θJC3 (44-Terminal LCC 883 Parts Only) . . . . . . . . . . . 10°C/W Storage Temperature (All Grades) . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C DB5 13 28 INHIBIT DB6 14 27 BYTE SELECT DB7 15 26 ENABLE DB8 16 25 VL INTEGRATOR I/P INTEGRATOR O/P 22 DB14 DB12 20 21 DB13 2 1 44 43 42 41 40 NC 3 VCO I/P 4 DEMOD O/P DEMOD I/P DB11 19 REFERENCE I/P 23 DB15 COS 6 5 SIN 7 39 –VS 38 RIPPLE CLOCK 37 DIRECTION MSB DB1 10 36 BUSY DB2 11 35 DATA LOAD AD2S80A DB3 12 34 NC TOP VIEW (Not to Scale) DB4 13 33 SC2 DB5 14 32 SC1 DB6 15 31 DIGITAL GND DB7 16 30 INHIBIT DB8 17 29 NC Resolution (2N) Degrees /Bit Minutes /Bit Seconds /Bit 360.0 180.0 90.0 45.0 22.5 21600.0 10800.0 5400.0 2700.0 1350.0 1296000.0 648000.0 324000.0 162000.0 81000.0 0 1 2 3 4 1 2 4 8 16 5 6 7 8 9 32 64 128 256 512 10 11 12 13 14 1024 2048 4096 8192 116384 0.3515625 0.1757813 0.0878906 0.0439453 0.0219727 21.09375 10.546875 5.273438 2.636719 1.318359 1265.625 632.8125 316.40625 158.20313 79.10156 15 16 17 18 32768 65536 131072 262144 0.0109836 0.0054932 0.0027466 0.0013733 0.659180 0.329590 0.164795 0.082397 39.55078 19.77539 9.88770 4.94385 REV. B 11.25 5.625 2.8125 1.40625 0.703125 675.0 337.5 168.75 84.375 42.1875 BYTE SELECT VL ENABLE DB15 DB14 LSB DB16 NC = NO CONNECT DB13 DB11 DB12 DB9 DB10 18 19 20 21 22 23 24 25 26 27 28 Bit Weight Table Binary Bits (N) LCC (E) Package +VS 8 NC 9 CAUTION NOTES: 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur. 2 Correct polarity voltages must be maintained on the +V S and –V S pins. 3 With reference to Appendix C of MIL-M-38510. 24 DB16 LSB DB10 18 AC ERROR O/P SIGNAL GND ANALOG GND DB9 17 PIN DESIGNATIONS 40500.0 20250.0 10125.0 5062.5 2531.25 MNEMONIC DESCRIPTION REFERENCE I/P DEMOD I/P AC ERROR O/P COS ANALOG GROUND SIGNAL GROUND SIN +VS DB1–DB16 VL ENABLE REFERENCE SIGNAL INPUT DEMODULATOR INPUT RATIO MULTIPLIER OUTPUT COSINE INPUT POWER GROUND RESOLVER SIGNAL GROUND SINE INPUT POSITIVE POWER SUPPLY PARALLEL OUTPUT DATA LOGIC POWER SUPPLY LOGIC Hl-OUTPUT DATA IN HIGH IMPEDANCE STATE, LOGIC LO PRESENTS DATA TO THE OUTPUT LATCHES LOGIC Hl-MOST SIGNIFICANT BYTE TO DB1–DB8 LOGIC LO-LEAST SlGNlFlCANT BYTE TO DB1–DB8 LOGIC LO INHIBITS DATA TRANSFER TO OUTPUT LATCHES DlGITAL GROUND SELECT CONVERTER RESOLUTION LOGIC LO DB1–DB16 INPUTS LOGIC Hl DB1–D16 OUTPUTS CONVERTER BUSY, DATA NOT VALID WHILE BUSY Hl LOGIC STATE DEFINES DIRECTION OF INPUT SIGNAL ROTATION POSITIVE PULSE WHEN CONVERTER OUTPUT CHANGES FROM 1S TO ALL 0S OR VICE VERSA NEGATIVE POWER SUPPLY VCO INPUT INTEGRATOR INPUT INTEGRATOR OUTPUT DEMODULATOR OUTPUT BYTE SELECT INHIBIT DIGITAL GROUND SC1–SC2 DATA LOAD BUSY DIRECTION RIPPLE CLOCK –VS VCO I/P INTEGRATOR I/P INTEGRATOR O/P DEMOD O/P –5– AD2S80A CONNECTING THE CONVERTER SIGNAL GROUND and ANALOG GROUND are connected internally. ANALOG GROUND and DIGITAL GROUND must be connected externally. The power supply voltages connected to +VS and –VS pins should be +12 V dc and –12 V dc and must not be reversed. The voltage applied to VL can be 5 V dc to +VS. The external components required should be connected as shown in Figure 1. It is recommended that the decoupling capacitors are connected in parallel between the power lines +VS, –VS and ANALOG GROUND adjacent to the converter. Recommended values are 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and 10 µF should be connected between +VL and DIGITAL GROUND adjacent to the converter. CONVERTER RESOLUTION Two major areas of the AD2S80A specification can be selected by the user to optimize the total system performance. The resolution of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12, 14, or 16 bits; and the dynamic characteristics of bandwidth and tracking rate are selected by the choice of external components. When more than one converter is used on a card, then separate decoupling capacitors should be used for each converter. The resolver connections should be made to the SIN and COS inputs, REFERENCE INPUT and SIGNAL GROUND as shown in Figure 7 and described in section “CONNECTING THE RESOLVER.” The choice of the resolution will affect the values of R4 and R6 which scale the inputs to the integrator and the VCO respectively (see section COMPONENT SELECTION). If the resolution is changed, then new values of R4 and R6 must be switched into the circuit. The two signal ground wires from the resolver should be joined at the SIGNAL GROUND pin of the converter to minimize the coupling between the sine and cosine signals. For this reason it is also recommended that the resolver is connected using individually screened twisted pair cables with the sine, cosine and reference signals twisted separately. Note: When changing resolution under dynamic conditions, do it when the BUSY is low, i.e., when Data is not changing. REFERENCE I/P HF FILTER OFFSET ADJUST R9 +12V –12V C3 R8 C1 R2 R3 BANDWIDTH SELECTION C2 R4 R1 INTEGRATOR I/P AC ERROR O/P DEMOD I/P SIN SIG GND A1 COS A2 SEGMENT SWITCHING R-2R DAC RIPPLE CLK DEMOD O/P R5 PHASE SENSITIVE DETECTOR A3 INTEGRATOR O/P AD2S80A GND VELOCITY SIGNAL R6 16-BIT UP/DOWN COUNTER VCO + DATA TRANSFER LOGIC +12V –12V C5 C4 OUTPUT DATA LATCH VCO I/P TRACKING RATE SELECTION R7 C6 DATA SC1 SC2 LOAD ENABLE 16 DATA BITS BYTE SELECT 5V DIG GND BUSY DIRN INHIBIT Figure 1. AD2S80A Connection Diagram –6– REV. B AD2S80A CONVERTER OPERATION POSITION OUTPUT When connected in a circuit such as shown in Figure 1 the AD2S80A operates as a tracking resolver-to-digital converter and forms a Type 2 closed-loop system. The output will automatically follow the input for speeds up to the selected maximum tracking rate. No convert command is necessary as the conversion is automatically initiated by each LSB increment, or decrement, of the input. Each LSB change of the converter initiates a BUSY pulse. The resolver shaft position is represented at the converter output by a natural binary parallel digital word. As the digital position output of the converter passes through the major carries, i.e., all “1s” to all “0s” or the converse, a RIPPLE CLOCK (RC) logic output is initiated indicating that a revolution or a pitch of the input has been completed. The direction of input rotation is indicated by the DIRECTION (DIR) logic output. This direction data is always valid in advance of a RIPPLE CLOCK pulse and, as it is internally latched, only changing state (1 LSB min change) with a corresponding change in direction. The AD2S80A is remarkably tolerant of input amplitude and frequency variation because the conversion depends only on the ratio of the input signals. Consequently there is no need for accurate, stable oscillator to produce the reference signal. The inclusion of the phase sensitive detector in the conversion loop ensures a high immunity to signals that are not coherent or are in quadrature with the reference signal. Both the RIPPLE CLOCK pulse and the DIRECTION data are unaffected by the application of the INHIBIT. The static positional accuracy quoted is the worst case error that can occur over the full operating temperature excluding the effects of offset signals at the INTEGRATOR INPUT (which can be trimmed out—see Figure 1), and with the following conditions: input signal amplitudes are within 10% of the nominal; phase shift between signal and reference is less than 10 degrees. SIGNAL CONDITIONING The amplitude of the SINE and COSINE signal inputs should be maintained within 10% of the nominal values if full performance is required from the velocity signal. These operating conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national standards. In practice, the AD2S80A can be used well outside these operating conditions providing the above points are observed. The digital position output is relatively insensitive to amplitude variation. Increasing the input signal levels by more than 10% will result in a loss in accuracy due to internal overload. Reducing levels will result in a steady decline in accuracy. With the signal levels at 50% of the correct value, the angular error will increase to an amount equivalent to 1.3 LSB. At this level the repeatability will also degrade to 2 LSB and the dynamic response will also change, since the dynamic characteristics are proportional to the signal level. VELOCITY SIGNAL The tracking converter technique generates an internal signal at the output of the integrator (the INTEGRATOR OUTPUT pin) that is proportional to the rate of change of the input angle. This is a dc analog output referred to as the VELOCITY signal. The AD2S80A will not be damaged if the signal inputs are applied to the converter without the power supplies and/or the reference. In many applications it is possible to use the velocity signal of the AD2S80A to replace a conventional tachogenerator. REFERENCE INPUT The amplitude of the reference signal applied to the converter’s input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. DC ERROR SIGNAL The signal at the output of the phase sensitive detector (DEMODULATOR OUTPUT) is the signal to be nulled by the tracking loop and is, therefore, proportional to the error between the input angle and the output digital angle. This is the dc error of the converter; and as the converter is a Type 2 servo loop, it will increase if the output fails to track the input for any reason. It is an indication that the input has exceeded the maximum tracking rate of the converter or, due to some internal malfunction, the converter is unable to reach a null. By connecting two external comparators, this voltage can be used as a “built-in-test.” The AD2S80A will not be damaged if the reference is supplied to the converter without the power supplies and/or the signal inputs. HARMONIC DISTORTION The amount of harmonic distortion allowable on the signal and reference lines is 10%. Square waveforms can be used but the input levels should be adjusted so that the average value is 1.9 V rms. (For example, a square wave should be 1.9 V peak.) Triangular and sawtooth waveforms should have a amplitude of 2 V rms. Note: The figure specified of 10% harmonic distortion is for calibration convenience only. REV. B –7– AD2S80A 4. Maximum Tracking Rate (R6) The VCO input resistor R6 sets the maximum tracking rate of the converter and hence the velocity scaling as at the max tracking rate, the velocity output will be 8 V. COMPONENT SELECTION The following instructions describe how to select the external components for the converter in order to achieve the required bandwidth and tracking rate. In all cases the nearest “preferred value” component should be used, and a 5% tolerance will not degrade the overall performance of the converter. Care should be taken that the resistors and capacitors will function over the required operating temperature range. The components should be connected as shown in Figure 1. Decide on your maximum tracking rate, “T,” in revolutions per second. Note that “T” must not exceed the maximum tracking rate or 1/16 of the reference frequency. 10 R6 = PG compatible software is available to help users select the optimum component values for the AD2S80A, and display the transfer gain, phase and small step response. 1. HF Filter (R1, R2, C1, C2) The function of the HF filter is to remove any dc offset and to reduce the amount of noise present on the signal inputs to the AD2S80A, reaching the Phase Sensitive Detector and affecting the outputs. R1 and C2 may be omitted—in which case R2 = R3 and C1 = C3, calculated below—but their use is particularly recommended if noise from switch mode power supplies and brushless motor drive is present. Resolution 10 12 14 16 C1 = C 2 = 15 kΩ ≤ R1 = R2 ≤ 56 kΩ Ratio of Reference Frequency/Bandwidth 2.5 : 1 4 :1 6 :1 7.5 : 1 Typical values may be 100 Hz for a 400 Hz reference frequency and 500 Hz to 1000 Hz for a 5 kHz reference frequency. b. Select C4 so that C1 = C 2 = C4 = (Hz) 21 F R6 × fBW 2 with R6 in Ω and fBW, in Hz selected above. This filter gives an attenuation of three times at the input to the phase sensitive detector. c. C5 is given by 2. Gain Scaling Resistor (R4) If R1, C2 are used: C5 = 5 × C4 d. R5 is given by E DC 1 × Ω 100 ×10 –9 3 R5 = where 100 × 10–9 = current/LSB If R1, C2 are not used: R4 = Ω 5. Closed-Loop Bandwidth Selection (C4, C5, R5) a. Choose the closed-loop bandwidth (fBW) required ensuring that the ratio of reference frequency to bandwidth does not exceed the following guidelines: Values should be chosen so that R4 = T ×n where n = bits per revolution = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits For more detailed information and explanation, see section “CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE.” 1 2π R1 fREF and fREF = Reference frequency 6. 32 × 10 4 2 × π × f BW × C5 Ω 6. VCO Phase Compensation The following values of C6 and R7 should be fitted. EDC 100 × 10 –9 C6 = 470 pF, R7 = 68 Ω Ω = 10 × 10–3 for 14 bits 7. Offset Adjust Offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. If this can be tolerated, then R8 and R9 can be omitted from the circuit. = 2.5 × 10–3 for 16 bits If fitted, the following values of R8 and R9 should be used: where EDC = 160 × 10 for 10 bits resolution –3 = 40 × 10–3 for 12 bits R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer = Scaling of the DC ERROR in volts 3. AC Coupling of Reference Input (R3, C3) Select R3 and C3 so that there is no significant phase shift at the reference frequency. That is, To adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. Connect the COS pin to the REFERENCE INPUT and the SIN pin to the SIGNAL GROUND and with the power and reference applied, adjust the potentiometer to give all “0s” on the digital output bits. The potentiometer may be replaced with select on test resistors if preferred. R3 = 100 kΩ C3 > 1 R3 × fREF F with R3 in Ω. –8– REV. B AD2S80A DATA TRANSFER 5V To transfer data the INHIBIT input should be used. The data will be valid 600 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is applied and allows time for an active BUSY to clear. By using the ENABLE input the two bytes of data can be transferred after which the INHIBIT should be returned to a logic “HI” state to enable the output latches to be updated. 10k⍀ 1k⍀ TO COUNTER (CLOCK) IN4148 RIPPLE CLOCK 2N3904 5V 0V 5k⍀ IN4148 BUSY NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO." Figure 2. Diode Transistor Logic Nand Gate BUSY Output DIRECTION Output The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL level. A BUSY pulse is initiated each time the input moves by the analog equivalent of one LSB and the internal counter is incremented or decremented. The DIRECTION (DIR) logic output indicates the direction of the input rotation. Any change in the state of DIR precedes the corresponding BUSY, DATA and RIPPLE CLOCK updates. DIR can be considered as an asynchronous output and can make multiple changes in state between two consecutive LSB update cycles. This corresponds to a change in input rotation direction but less than 1 LSB. INHIBIT Input The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a BUSY pulse to refresh the output data. DIGITAL TIMING VH BUSY RIPPLE CLOCK ENABLE Input The ENABLE input determines the state of the output data. A logic “HI” maintains the output data pins in the high impedance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the ENABLE has no effect on the conversion process. t1 t2 VL VH t4 t3 VH DATA t5 INHIBIT VH t6 BYTE SELECT Input The BYTE SELECT input selects the byte of the position data to be presented at the data output DB1 to DB8. The least significant byte will be presented on data output DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S80A is used with a resolution less than 16 bits the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “LO” will present the least significant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate data outputs 9 to 16. VL VH t7 DIR VL t8 t9 VL INHIBIT VL ENABLE t 10 DATA t 11 BYTE SELECT The operation of the BYTE SELECT has no effect on the conversion process of the converter. VH VZ VL VL VH VH DATA t 12 RIPPLE CLOCK As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on the RIPPLE CLOCK (RC) output is initiated indicating that a revolution, or a pitch, of the input has been completed. t 13 VL PARAMETER TMIN TMAX CONDITION t1 200 600 BUSY WIDTH VH–VH t2 10 25 RIPPLE CLOCK VH TO BUSY VH t3 470 580 RIPPLE CLOCK V L TO NEXT BUSY VH t4 16 45 BUSY VH TO DATA VH t5 3 25 BUSY VH TO DATA VL t6 70 140 INHIBIT VH TO BUSY VH t7 485 625 MIN DIR VH TO BUSY VH t8 515 670 MIN DIR VH TO BUSY VH t9 – 600 INHIBIT VL TO DATA STABLE If the AD2S80A is being used in a pitch and revolution counting application, the ripple and busy will need to be gated to prevent false decrement or increment (see Figure 2). t10 40 110 ENABLE VL TO DATA VH t11 35 110 ENABLE VL TO DATA VL t12 60 140 BYTE SELECT VL TO DATA STABLE RIPPLE CLOCK is unaffected by INHIBIT. t13 60 125 BYTE SELECT VH TO DATA STABLE The minimum pulse width of the ripple clock is 300 ns. RIPPLE CLOCK is normally set high before a BUSY pulse and resets before the next positive going edge of the next consecutive pulse. The only exception to this is when DIR changes while the RIPPLE CLOCK is high. Resetting of the RIPPLE clock will only occur if the DIR remains stable for two consecutive positive BUSY pulse edges. REV. B –9– AD2S80A CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE Additional compensation in the form of a pole/zero pair is required to stabilize any Type 2 loop to avoid the loop gain characteristic crossing the 0 dB axis with 180° of additional phase lag, as shown in Figure 5. The AD2S80A allows the user greater flexibility in choosing the dynamic characteristics of the resolver-to-digital conversion to ensure the optimum system performance. The characteristics are set by the external components shown in Figure 1, and the section “COMPONENT SELECTION” explains how to select desired maximum tracking rate and bandwidth values. The following paragraphs explain in greater detail the circuit of the AD2S80A and the variations in the dynamic performance available to the user. This compensation is implemented by the integrator components (R4, C4, R5, C5). The overall response of such a system is that of a unity gain second order low pass filter, with the angle of the resolver as the input and the digital position data as the output. Loop Compensation The AD2S80A (connected as shown in Figure 1) operates as a Type 2 tracking servo loop where the VCO/counter combination and Integrator perform the two integration functions inherent in a Type 2 loop. The AD2S80A does not have to be connected as tracking converter, parts of the circuit can be used independently. This is particularly true of the Ratio Multiplier which can be used as a control transformer (see Application Note). A block diagram of the AD2S80A is given in Figure 3. C5 R5 AC ERROR C4 sin sin t RATIO MULTIPLIER cos sin t A1 sin ( – ) sin t PHASE SENSITIVE DEMODULATOR INTEGRATOR CLOCK DIGITAL R4 R6 VCO DIRECTION VELOCITY Figure 3. Functional Diagram Ratio Multiplier The ratio multiplier is the input section of the AD2S80A and compares the signal from the resolver input angle, θ, to the digital angle, φ, held in the counter. Any difference between these two angles results in an analog voltage at the AC ERROR OUTPUT. This circuit function has historically been called a “Control Transformer” as it was originally performed by an electromechanical device known by that name. The AC ERROR signal is given by A1 sin (θ–φ) sin ωt where ω = 2 π fREF fREF = reference frequency A1, the gain of the ratio multiplier stage is 14.5. So for 2 V rms inputs signals AC ERROR output in volts/(bit of error) 360 = 2 × sin n × A1 where n = bits per rev = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits giving an AC ERROR output = 178 mV/bit @ 10 bits resolution = 44.5 mV/bit @ 12 bits = 11.125 mV/bit @ 14 bits = 2.78 mV/bit @ 16 bits The ratio multiplier will work in exactly the same way whether the AD2S80A is connected as a tracking converter or as a control transformer, where data is preset into the counters using the DATA LOAD pin. HF Filter The AC ERROR OUTPUT may be fed to the PSD via a simple ac coupling network (R2, C1) to remove any dc offset at this point. Note, however, that the PSD of the AD2S80A is a wideband demodulator and is capable of aliasing HF noise down to within the loop bandwidth. This is most likely to happen where the resolver is situated in particularly noisy environments, and the user is advised to fit a simple HF filter R1, C2 prior to the phase sensitive demodulator. The attenuation and frequency response of a filter will affect the loop gain and must be taken into account in deriving the loop transfer function. The suggested filter (R1, C1, R2, C2) is shown in Figure 1 and gives an attenuation at the reference frequency (fREF) of 3 times at the input to the phase sensitive demodulator . Values of components used in the filter must be chosen to ensure that the phase shift at fREF is within the allowable signal to reference phase shift of the converter. Phase Sensitive Demodulator The phase sensitive demodulator is effectively ideal and develops a mean dc output at the DEMODULATOR OUTPUT pin of ±2 2 π × (DEMODULATOR INPUT rms voltage ) –10– REV. B AD2S80A The tracking rate in rps per µA of VCO input current can be found by dividing the VCO scaling factor by the number of LSB changes per rev (i.e., 4096 for 12-bit resolution). for sinusoidal signals in phase or antiphase with the reference (for a square wave the DEMODULATOR OUTPUT voltage will equal the DEMODULATOR INPUT). This provides a signal at the DEMODULATOR OUTPUT which is a dc level proportional to the positional error of the converter. The input resistor R6 determines the scaling between the converter velocity signal voltage at the INTEGRATOR OUTPUT pin and the VCO input current. Thus to achieve a 5 V output at 100 rps (6000 rpm) and 12-bit resolution the VCO input current must be: DC Error Scaling = 160 mV/bit (10 bits resolution) = 40 mV/bit (12 bits resolution) = 10 mV/bit (14 bits resolution) = 2.5 mV/bit (16 bits resolution) (100 × 4096)/(7900) = 51.8 µA When the tracking loop is closed, this error is nulled to zero unless the converter input angle is accelerating. Thus, R6 would be set to: 5/(51.8 × 10–6) = 96 kΩ Integrator The velocity offset voltage depends on the VCO input resistor, R6, and the VCO bias current and is given by The integrator components (R4, C4, R5, C5) are external to the AD2S80A to allow the user to determine the optimum dynamic characteristics for any given application. The section “COMPONENT SELECTION” explains how to select components for a chosen bandwidth. Since the output from the integrator is fed to the VCO INPUT, it is proportional to velocity (rate of change of output angle) and can be scaled by selection of R6, the VCO input resistor. This is explained in the section “VOLTAGE CONTROLLED OSCILLATOR (VCO)” below. To prevent the converter from “flickering” (i.e., continually toggling by ± 1 bit when the quantized digital angle, φ, is not an exact representation of the input angle, θ) feedback is internally applied from the VCO to the integrator input to ensure that the VCO will only update the counter when the error is greater than or equal to 1 LSB. In order to ensure that this feedback “hysteresis” is set to 1 LSB the input current to the integrator must be scaled to be 100 nA/bit. Therefore, R4 = DC Error Scaling (mV /bit ) 100 (nA /bit ) Any offset at the input of the integrator will affect the accuracy of the conversion as it will be treated as an error signal and offset the digital output. One LSB of extra error will be added for each 100 nA of input bias current. The method of adjusting out this offset is given in the section “COMPONENT SELECTION.” Velocity Offset Voltage = R6 × (VCO bias current) The temperature coefficient of this offset is given by Velocity Offset Tempco = R6 × (VCO bias current tempco) where the VCO bias current tempco is typically –1.22 nA/°C. The maximum recommended rate for the VCO is 1.1 MHz which sets the maximum possible tracking rate. Since the minimum voltage swing available at the integrator output is ± 8 V, this implies that the minimum value for R6 is 57 kΩ. As 1.1 × 106 = 139 µA 7.9 × 103 8 MinValue R6 = = 57 kΩ 139 × 10 –6 Max Current = Transfer Function By selecting components using the method outlined in the section “Component Selection,” the converter will have a critically damped time response and maximum phase margin. The Closed-Loop Transfer Function is given by: 14 (1+ sN ) θOUT = 2 θ IN (sN + 2.4)(sN + 3.4 sN + 5.8) where, sN, the normalized frequency variable is: Voltage Controlled Oscillator (VCO) 2 s sN = π f BW The VCO is essentially a simple integrator feeding a pair of dc level comparators. Whenever the integrator output reaches one of the comparator threshold voltages, a fixed charge is injected into the integrator input to balance the input current. At the same time the counter is clocking either up or down, dependent on the polarity of the input current. In this way the counter is clocked at a rate proportional to the magnitude of the input current of the VCO. and fBW is the closed-loop 3 dB bandwidth (selected by the choice of external components). The acceleration KA, is given approximately by 2 K A = 6 × ( f BW ) sec During the reset period the input continues to be integrated, the reset period is constant at 400 ns. The normalized gain and phase diagrams are given in Figures 4 and 5. The VCO rate is fixed for a given input current by the VCO scaling factor: = 7.9 kHz/µA REV. B –2 –11– AD2S80A 12 the step until the converter is settled to 1 LSB. The times t1 and t2 are given approximately by 9 GAIN PLOT 6 1 f BW t2 = 5 3 0 –3 f BW × R 12 where R = resolution, i.e., 10, 12, 14, or 16. –6 –9 –12 0.02fBW 0.04fBW 0.1fBW 0.4fBW 0.2fBW FREQUENCY fBW 2fBW The large signal step response (for steps greater than 5 degrees) applies when the error voltage exceeds the linear range of the converter. Typically the converter will take 3 times longer to reach the first peak for a 179 degrees step. Figure 4. AD2S80A Gain Plot 180 In response to a velocity step, the velocity output will exhibit the same time response characteristics as outlined above for the position output. 135 ACCELERATION ERROR A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant KA of the converter. 90 PHASE PLOT t1 = 45 0 KA = –45 –90 –135 –180 0.02fBW 0.04fBW 0.1fBW 0.2fBW 0.4fBW fBW 2fBW FREQUENCY Figure 5. AD2S80A Phase Plot OUTPUT POSITION t2 Input Acceleration Error in Output Angle The numerator and denominator must have consistent angular units. For example if KA is in sec–2, then the input acceleration may be specified in degrees/sec2 and the error output in degrees. Angular measurement may also be specified using radians, minutes of arc, LSBs, etc. KA does not define maximum input acceleration, only the error due to it’s acceleration. The maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. Angular Accuracy × KA = Degrees/sec2 KA can be used to predict the output position error for a given input acceleration. For example for an acceleration of 100 revs/sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution. Error in LSBs = Input acceleration [LSB/sec 2 ] K A[sec –2 ] 100 [rev/sec 2 ] × 212 = 0.15 LSBs or 47.5 seconds of arc 2.7×10 6 To determine the value of KA based on the passive components used to define the dynamics of the converter the following should be used. = TIME t1 KA = Figure 6. AD2S80A Small Step Response The small signal step response is shown in Figure 6. The time from the step to the first peak is t1 and the t2 is the time from 4.04 ×1011 2n • R6• R4 •(C4 + C5) Where n = resolution of the converter. R4, R6 in ohms C5, C4 in farads –12– REV. B AD2S80A VELOCITY ERRORS SOURCES OF ERRORS Integrator Offset The signal at the INTEGRATOR OUTPUT pin relative to the ANALOG GROUND pin is an analog voltage proportional to the rate of change of the input angle. This signal can be used to stabilize servo loops or in the place of a velocity transducer. Although the conversion loop of the AD2S80A includes a digital section there is an additional analog feedback loop around the velocity signal. This ensures against flicker in the digital positional output in both dynamic and static states. Additional inaccuracies in the conversion of the resolver signals will result from an offset at the input to the integrator as it will be treated as an error signal. This error will typically be 1 arc minute over the operating temperature range. A description of how to adjust from zero offset is given in the section “COMPONENT SELECTION” and the circuit required is shown in Figure 1. Differential Phase Shift Phase shift between the sine and cosine signals from the resolver is known as differential phase shift and can cause static error. Some differential phase shift will be present on all resolvers as a result of coupling. A small resolver residual voltage (quadrature voltage) indicates a small differential phase shift. Additional phase shift can be introduced if the sine channel wires and the cosine channel wires are treated differently. For instance, different cable lengths or different loads could cause differential phase shift. The additional error caused by differential phase shift on the input signals approximates to Error = 0.53 a × b arc minutes where a = differential phase shift (degrees). b = signal to reference phase shift (degrees). This error can be minimized by choosing a resolver with a small residual voltage, ensuring that the sine and cosine signals are handled identically and removing the reference phase shift (see section “CONNECTING THE RESOLVER”). By taking these precautions the extra error can be made insignificant. A better quality velocity signal will be achieved if the following points are considered: 1. Protection. The velocity signal should be buffered before use. 2. Reversion error.1 The reversion error can be nulled by varying one supply rail relative to the other. 3. Ripple and Noise. Noise on the input signals to the converter is the major cause of noise on the velocity signal. This can be reduced to a minimum if the following precautions are taken: The resolver is connected to the converter using separate twisted pair cable for the sine, cosine and reference signals. Care is taken to reduce the external noise wherever possible. An HF filter is fltted before the Phase Sensitive Demodulator (as described in the section HF FILTER). A resolver is chosen that has low residual voltage, i.e., a small signal in quadrature with the reference. Under static operating conditions phase shift between the reference and the signal lines alone will not theoretically affect the converter’s static accuracy. Components are selected to operate the AD2S80A with the lowest acceptable bandwidth. Feedthrough of the reference frequency should be removed by a filter on the velocity signal. However, most resolvers exhibit a phase shift between the signal and the reference. This phase shift will give rise under dynamic conditions to an additional error defined by: Maintenance of the input signal voltages at 2 V rms will prevent LSB flicker at the positional output. The analog feedback or hysteresis employed around the VCO and the intergrator is a function of the input signal levels (see section “INTEGRATOR”) . Shaft Speed (rps) × Phase Shift (Degrees ) Reference Frequency For example, for a phase shift of 20 degrees, a shaft rotation of 22 rps and a reference frequency of 5 kHz, the converter will exhibit an additional error of: 22 × 20 0.088 Degrees 5000 Following the preceding precautions will allow the user to use the velocity signal in very noisy environments, for example, PWM motor drive applications. Resolver/converter error curves may exhibit apparent acceleration/deceleration at a constant velocity. This results in ripple on the velocity signal of frequency twice the input rotation. This effect can be eliminated by placing a phase shift in the reference to the converter equivalent to the phase shift in the resolver (see section “CONNECTING THE RESOLVER”). Note: Capacitive and inductive crosstalk in the signal and reference leads and wiring can cause similar problems. 1 Reversion error, or side-to-side nonlinearity, is a result of differences in the up and down rates of the VCO. REV. B –13– AD2S80A CONNECTING THE RESOLVER TYPICAL CIRCUIT CONFIGURATION The recommended connection circuit is shown in Figure 7. Figure 8 shows a typical circuit configuration for the AD2S80A in a 12-bit resolution mode. Values of the external components have been chosen for a reference frequency of 5 kHz and a maximum tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the values for R4, R6, C4 and C5 in the equation for KA gives a value of 1.67 × 106. The resistors are 0.125 W, 5% tolerance preferred values. The capacitors are 100 V ceramic, 10% tolerance components. In cases where the reference phase relative to the input signals from the resolver requires adjustment, this can be easily achieved by varying the value of the resistor R2 of the HF filter (see Figure 1). Assuming that R1 = R2 = R and C1 = C2 = C 1 and Reference Frequency = 2 π RC by altering the value of R2, the phase of the reference relative to the input signals will change in an approximately linear manner for phase shifts of up to 10 degrees. Increasing R2 by 10% introduces a phase lag of 2 degrees. Decreasing R2 by 10% introduces a phase lead of 2 degrees. PHASE LEAD = ARC TAN C 1 2fRC PHASE LAG = ARC TAN 2fRC R R C Phase Shift Circuits For signal and reference voltages greater than 2 V rms a simple voltage divider circuit of resistors can be used to generate the correct signal level at the converter. Care should be taken to ensure that the ratios of the resistors between the sine signal line and ground and the cosine signal line and ground are the same. Any difference will result in an additional position error. For more information on resistive scaling of SIN, COS and REFERENCE converter inputs refer to the application note, “Circuit Applications of the 2S81 and 2S81 Resolver-to-Digital Converters.” RELIABILITY The AD2S80A Mean Time Between Failures (MTBF) has been calculated according to MIL-HDBK-217E, Figure 10 shows the MTBF in hours in naval sheltered conditions for AD2S80A/ 883B only. OSCILLATOR (e.g., OSC1758) C3 1 R3 REF I/P 2 AD2S80A 3 TWISTED PAIR SCREENED CABLE S2 R1 S4 S3 R2 4 COS I/P 5 ANALOG GND 6 SIGNAL GND 7 SIN I/P DIGITAL 31 GND S1 RESOLVER POWER RETURN Figure 7. Connecting the AD2S80A to a Resolver –14– REV. B AD2S80A 1M⍀ 4.7M⍀ C3 100nF R3 100k⍀ C2 2.2nF R2 15k⍀ REFERENCE INPUT 2 39 R4 130k⍀ 3 38 4 37 5 36 6 35 RIPPLE CLK PIN 1 1 100nF COS HIGH RESOLVER SIGNALS 40 R6 56k⍀ C1 R1 2.2nF 15k⍀ REF LOW COS LOW 7 SIN LOW 8 AD2S80A SIN HIGH 9 TOP VIEW 32 DATA LOAD (Not to Scale) 31 SC2 MSB DATA OUTPUT C5 6.8nF R5 180k⍀ 100nF R7 C6 68⍀ 470pF –12V 34 DIRECTION 10 +12V VELOCITY O/P C4 1.3nF 33 BUSY 11 30 12 29 0V 13 28 INHIBIT 14 27 BYTE SELECT 15 26 ENABLE 16 25 17 24 18 23 19 22 20 21 100nF +5V LSB Figure 8. Typical Circuit Configuration 360 10M 315 225 MTBF – Hours ANGLE – Degrees 270 180 135 1M 100k 90 45 0 0 4 8 12 TIME – ms 16 20 10k 24 –40 0 20 40 60 80 100 TEMPERATURE – ⴗC Figure 9. Large Step Response Curves for Typical Circuit Shown in Figure 8 REV. B –20 Figure 10. AD2S80A MTBF Curve –15– 120 AD2S80A The ratio multiplier of the AD2S80A can be used independently of the loop integrators as a control transformer. In this mode the resolver inputs θ are multiplied by a digital angle φ any difference between φ and θ will be represented by the AC ERROR output as SIN ωt sin (θ–φ) or the DEMOD output as sin (θ–φ). To use the AD2S80A in this mode refer to the “Control Transformer” application note. Dynamic Switching In applications where the user requires wide band response from the converter, for example 100 rpm to 6000 rpm, superior performance is achieved if the converters control characteristics are switched dynamically. This reduces velocity offset levels at low tracking rates. For more information on the technique refer to “Dynamic Resolution Switching Using the Variable Resolution Monolithic Resolver-to-Digital Converters.” OTHER PRODUCTS The AD2S82A is a monolithic, variable resolution 10-, 12-, 14and 16-bit resolver-to-digital converter in a 44-terminal J-leaded PLCC package. In addition to the AD2S80A functions it has a VCO OUTPUT which is a measure of position within a LSB, and a COMPLEMENT Data Output. The AD2S81A is a low cost, monolithic, 12-bit resolver-todigital converter in a 28-lead ceramic DIP package. ORDERING GUIDE Model Operating Temperature Range Accuracy Package Description Package Option AD2S80AJD AD2S80AKD AD2S80ALD AD2S80AAD AD2S80ABD AD2S80ASD AD2S80ATD AD2S80AUD AD2S80ASE AD2S80ATE AD2S80AUE AD2S80ASD/883B AD2S80ATD/883B AD2S80ASE/883B AD2S80ATE/883B 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 8 arc min 4 arc min 2 arc min 8 arc min 4 arc min 8 arc min 4 arc min 2 arc min 8 arc min 4 arc min 2 arc min 8 arc min 4 arc min 8 arc min 4 arc min Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Side Brazed Ceramic DIP Leadless Ceramic Chip Carrier Leadless Ceramic Chip Carrier Leadless Ceramic Chip Carrier Side Brazed Ceramic DIP Side Brazed Ceramic DIP Leadless Ceramic Chip Carrier Leadless Ceramic Chip Carrier D-40 D-40 D-40 D-40 D-40 D-40 D-40 D-40 E-44A E-44A E-44A D-40 D-40 E-44A E-44A C00008–2.5–9/00 (rev. B) APPLICATIONS Control Transformer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Terminal LCC (E) Package 0.100 (2.54)1 0.055 (1.40) 0.064 (1.63) 0.045 (1.14) 2.02 (51.31) 1.98 (50.29) 39 0.050 (1.27) BSC 0.060 (1.52) 0.02 (0.51) 0.09 (2.29) 0.07 (1.77) 0.150 (3.81) MIN 0.125 (3.22) 44 1 0.028 (0.71) 0.022 (0.56) 17 18 0.662 (16.82)2 SQ 0.640 (16.27) 0.020 (0.51) REF ⴛ 45° 7 BOTTOM VIEW 29 28 0.100 (2.54) TYP 0.59 (14.99) TYP 6 40 0.61 (15.49) 0.58 (14.73) 0.075 (1.91) REF PRINTED IN U.S.A. 40-Lead Ceramic DIP (D) Package 0.040 (1.02) REF ⴛ 45° 3 PLACES NOTES 1THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2APPLIES TO ALL FOUR SIDES. ALL TERMINALS ARE GOLD PLATED. 0.01 (0.25) TYP 0.012 (0.31) 0.009 (0.23) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. LEADS ARE GOLD PLATED (50 MICROINCHES MIN) KOVAR OR ALLOY 42. –16– REV. B