AD ADUM6200ARIZ Dual-channel, 5 kv isolators with integrated dc-to-dc converter Datasheet

Dual-Channel, 5 kV Isolators with
Integrated DC-to-DC Converter
ADuM6200/ADuM6201/ADuM6202
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
OSCILLATOR
RECTIFIER REGULATOR
GND1 2
16 VISO
15 GNDISO
VIA/VOA 3
14 VIA/VOA
2-CHANNEL iCOUPLER CORE
VIB/VOB 4
13 VIB/VOB
RCIN 5
12 NC
11 VSEL
ADuM6200/
ADuM6201/
ADuM6202
VE1/NC 7
10 VE2/NC
GND1 8
9 GNDISO
08775-001
RCSEL 6
NC = NO CONNECT
Figure 1.
VIA
VIB
3
14
ADuM6200
4
13
VOA
VOB
08775-002
isoPower integrated, isolated dc-to-dc converter
Regulated 5 V or 3.3 V output
Up to 400 mW output power
Dual dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC wide body package version
16-lead SOIC wide body enhanced creepage version
High temperature operation: 105°C maximum
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 60601-1: 250 V rms, 8 mm package (RI-16-1)
IEC 60950-1: 400 V rms, 8 mm package (RI-16-1)
VDE certificate of conformity (RW-16)
IEC 60747-5-2 (VDE 0884 Part 2):2003-01
VIORM = 846 V peak
VDE certificate of conformity, 8 mm package (RI-16-1)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
Figure 2. ADuM6200
APPLICATIONS
VIA
VOB
GENERAL DESCRIPTION
3
14
ADuM6201
4
13
VOA
VIB
08775-003
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Isolated sensor interfaces
Industrial PLCs
Figure 3. ADuM6201
1
The ADuM6200/ADuM6201/ADuM6202 isolators provide two
independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information).
VOA
VOB
3
14
ADuM6202
4
13
VIA
VIB
08775-004
The ADuM6200/ADuM6201/ADuM6202 are dual-channel
digital isolators with isoPower®, an integrated, isolated dc-to-dc
converter. Based on the Analog Devices, Inc., iCoupler® technology,
the dc-to-dc converter provides up to 400 mW of regulated, isolated power at either 5.0 V or 3.3 V from a 5.0 V input supply, or
at 3.3 V from a 3.3 V supply at the power levels shown in Table 1.
These devices eliminate the need for a separate, isolated dc-to-dc
converter in low power, isolated designs. The iCoupler chip scale
transformer technology is used to isolate the logic signals and for
the magnetic components of the dc-to-dc converter. The result
is a small form factor, total isolation solution.
Figure 4. ADuM6202
Table 1. Power Levels
Input Voltage (V)
5.0
5.0
3.3
Output Voltage (V)
5.0
3.3
3.3
Output Power (mW)
400
330
132
isoPower uses high frequency switching elements to transfer power
through its transformer. Special care must be taken during printed
circuit board (PCB) layout to meet emissions standards. See the
AN-0971 Application Note for board layout recommendations.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329; other patents are pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADuM6200/ADuM6201/ADuM6202
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions ......................... 11
Applications ....................................................................................... 1
Truth Table .................................................................................. 13
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 14
Functional Block Diagrams ............................................................. 1
Terminology .................................................................................... 17
Revision History ............................................................................... 2
Applications Information .............................................................. 18
Specifications..................................................................................... 3
PCB Layout ................................................................................. 18
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Start-Up Behavior....................................................................... 18
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 4
Propagation Delay Parameters ................................................. 19
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 6
Power Consumption .................................................................. 20
Package Characteristics ............................................................... 7
Regulatory Information ............................................................... 8
Insulation and Safety-Related Specifications ............................ 8
Insulation Characteristics ............................................................ 9
Recommended Operating Conditions ...................................... 9
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
EMI Considerations ................................................................... 19
DC Correctness and Magnetic Field Immunity ..................... 19
Current-Limit and Thermal Overload Protection ................. 21
Power Considerations ................................................................ 21
Thermal Analysis ....................................................................... 22
Increasing Available Power ....................................................... 22
Insulation Lifetime ..................................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/12—Rev. B to Rev. C
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Changes to Table 15 .......................................................................... 8
Changes to Insulation Characteristics Section ............................. 9
8/11—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Table 15 .......................................................................... 8
8/11—Rev. 0 to Rev. A
Added 16-Lead SOIC (RI-16-1) Package ........................ Universal
Changes to Features Section............................................................ 1
Changes to Table 15 and Table 16 .................................................. 8
Changes to Table 20 ........................................................................ 10
10/10—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range, which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO(MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO(LINE)
VISO(LOAD)
VISO(RIP)
VISO(NOISE)
fOSC
fPWM
IISO(MAX)
4.7
5.0
1
1
75
200
180
625
5.4
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 40 mA, VDD1 = 4.5 V to 5.5 V
IISO = 8 mA to 72 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 72 mA
CBO = 0.1 µF||10 µF, IISO = 72 mA
5
80
32
10
290
IDD1(Q)
IDD1(MAX)
26
VISO > 4.5 V
IISO = 80 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM6200
ADuM6201
ADuM6202
Available to Load
ADuM6200
ADuM6201
ADuM6202
Symbol
1 Mbps—A or C Grade
Min
Typ
Max
25 Mbps—C Grade
Min
Typ
Max
Unit
Test Conditions/
Comments
No VISO load
No VISO load
No VISO load
IDD1(D)
9
10
11
34
38
41
mA
mA
mA
80
80
80
74
72
70
mA
mA
mA
IISO(LOAD)
Table 4. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
55
Min
1
100
40
C Grade
Typ
Max
50
15
Mbps
ns
ns
ps/°C
ns
ns
50
50
6
15
ns
ns
45
25
60
6
5
PW
tPSK
tPSKCD
tPSKOD
Unit
1000
40
1
Test Conditions/
Comments
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
7
Rev. C | Page 3 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
Table 5. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Symbol
Min
Typ
VIH
VIL
VOH
0.7 × VISO or 0.7 × VDD1
Max
Unit
0.1
0.4
V
V
V
V
V
V
+20
V
V
V
µA
0.3 × VISO or 0.3 × VDD1
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
5.0
4.8
0.0
0.2
VOL
UVLO
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/µs
1.0
Mbps
fr
Test Conditions/
Comments
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
0 V ≤ VIx ≤ VDD1
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range, which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO(MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO(LINE)
VISO(LOAD)
VISO(RIP)
VISO(NOISE)
fOSC
fPWM
IISO(MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 20 mA, VDD1 = 3.0 V to 3.6 V
IISO = 4 mA to 36 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 36 mA
CBO = 0.1 µF||10 µF, IISO = 36 mA
IDD1(Q)
IDD1(MAX)
5
40
29
10
175
17
Rev. C | Page 4 of 28
VISO > 3 V
IISO = 40 mA
Data Sheet
ADuM6200/ADuM6201/ADuM6202
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM6200
ADuM6201
ADuM6202
Available to Load
ADuM6200
ADuM6201
ADuM6202
Symbol
1 Mbps—A or C Grade
Min
Typ
Max
25 Mbps—C Grade
Min
Typ
Max
Unit
Test Conditions/
Comments
No VISO load
No VISO load
No VISO load
IDD1(D)
6
7
8
23
25
27
mA
mA
mA
40
40
40
36
35
34
mA
mA
mA
C Grade
Typ
Max
Unit
IISO(LOAD)
Table 8. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
60
Min
1
100
40
50
45
Mbps
ns
ns
ps/°C
ns
ns
50
50
6
15
ns
ns
45
25
65
6
5
PW
tPSK
1000
tPSKCD
tPSKOD
40
Test Conditions/
Comments
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
Between any two units
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
7
Table 9. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Symbol
Min
Typ
VIH
VIL
VOH
0.7 × VISO or 0.7 × VDD1
Max
0.1
0.4
V
V
V
V
V
V
+20
V
V
V
µA
0.3 × VISO or 0.3 × VDD1
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
VOL
3.3
3.1
0.0
0.0
Unit
UVLO
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/µs
1.0
Mbps
fr
Test Conditions/
Comments
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
0 V ≤ VIx ≤ VDD1
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. C | Page 5 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range, which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO(MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO(LINE)
VISO(LOAD)
VISO(RIP)
VISO(NOISE)
fOSC
fPWM
IISO(MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
5
100
25
7
230
IDD1(Q)
IDD1(MAX)
13
VISO > 3 V
IISO = 100 mA
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM6200
ADuM6201
ADuM6202
Available to Load
ADuM6200
ADuM6201
ADuM6202
Symbol
1 Mbps—A or C Grade
Min
Typ
Max
25 Mbps—C Grade
Min
Typ
Max
Unit
Test Conditions/
Comments
No VISO load
No VISO load
No VISO load
IDD1(D)
6
6
6
22
23
24
mA
mA
mA
100
100
100
96
95
94
mA
mA
mA
IISO(LOAD)
Table 12. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
1
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
60
Min
1
100
40
25
65
6
50
15
50
50
6
15
ns
ns
5
PW
tPSK
tPSKCD
tPSKOD
Unit
Mbps
ns
ns
ps/°C
ns
ns
45
1000
40
Test Conditions/
Comments
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
7
2
C Grade
Typ
Max
Rev. C | Page 6 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
Table 13. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Min
VIH
0.7 × VISO or
0.7 × VDD1
Logic Low Input Threshold
VIL
Logic High Output Voltages
VOH
Logic Low Output Voltages
Undervoltage Lockout
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity1
Refresh Rate
1
Symbol
Typ
Max
Unit
V
0.3 × VISO or
0.3 × VDD1
VDD1 − 0.3 or
VISO − 0.3
VDD1 − 0.5 or
VISO − 0.5
VOL
V
VDD1 or VISO
V
IOx = −20 μA, VIx = VIxH
VDD1 − 0.2 or
VISO − 0.2
0.0
0.0
V
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VISO supplies
+20
V
V
V
μA
UVLO
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions/Comments
0 V ≤ VIx ≤ VDD1
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
PACKAGE CHARACTERISTICS
Table 14.
Parameter
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
IC Junction-to-Ambient Thermal
Resistance
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
3
Symbol
Min
Typ
Max
Unit
RI-O
CI-O
CI
θJA
1012
2.2
4.0
45
Ω
pF
pF
°C/W
TSSD
TSSD-HYS
150
20
°C
°C
Test Conditions/Comments
f = 1 MHz
Thermocouple is located at the center of
the package underside; test conducted
on a 4-layer board with thin traces3
TJ rising
This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
Refer to the Thermal Analysis section for thermal model definitions.
Rev. C | Page 7 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
REGULATORY INFORMATION
The ADuM6200/ADuM6201/ADuM6202 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime
section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels.
Table 15.
UL1
Recognized under UL 1577 component
recognition program
CSA
Approved under CSA Component Acceptance Notice #5A
Single protection, 5000 V rms isolation
voltage
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
600 V rms (848 V peak) maximum working voltage
File E214100
RW-16 package:
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
380 V rms (537 V peak) maximum working voltage
Reinforced insulation per IEC 60601-1, 125 V rms (176 V peak)
maximum working voltage
RI-16-1 package:
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
400 V rms (565 V peak) maximum working voltage
Reinforced insulation per IEC 60601-1, 250 V rms (353 V peak)
maximum working voltage
File 205078
VDE
RW-16 package:2
Certified according to IEC 60747-5-2
(VDE 0884 Part 2):2003-01
Basic insulation, 846 V peak
RI-16-1 package:3
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-12
Reinforced insulation, 846 V peak
File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM6200/ADuM6201/ADuM6202 is proof-tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec (current leakage
detection limit = 15 μA).
In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM6200/ADuM6201/ADuM6202 in the RW-16 package is proof-tested by applying an insulation
test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884
Part 2):2003-01 approval.
3
In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM6200/ADuM6201/ADuM6202 in the RI-16-1 package is proof-tested by applying an
insulation test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V
0884-10 (VDE V 0884-10):2006-12 approval.
2
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
Minimum External Tracking (Creepage)
L(I02)
RW-16 Package
RI-16-1 Package
Minimum Internal Distance (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
L(I01)
CTI
Value
5000
8.0
Unit
V rms
mm
7.6
8.3 min
0.017 min
>175
IIIa
mm
mm
mm
V
Rev. C | Page 8 of 28
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
DIN IEC 112/VDE 0303, Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet
ADuM6200/ADuM6201/ADuM6202
INSULATION CHARACTERISTICS
IEC 60747-5-2 (VDE 0884 Part 2):2003-01 and DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured
by protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 or
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
Table 17.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 450 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage
Method b1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Tests
Subgroup 2 and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
Symbol
Characteristic
Unit
VIORM
I to IV
I to II
I to II
40/105/21
2
846
V peak
VPR
1590
V peak
1375
1018
V peak
V peak
VIOTM
6000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 5)
Case Temperature
Side 1 Current (IDD1)
Insulation Resistance at TS
VIO = 500 V
Thermal Derating Curve
500
400
300
200
100
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
08775-107
SAFE OPERATING VDD1 CURRENT (mA)
600
Figure 5. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter
TEMPERATURE
Operating Temperature
SUPPLY VOLTAGES
VDD1 @ VSEL = 0 V
VDD1 @ VSEL = VISO
Symbol
Min
Max
Unit
Test Conditions/Comments
TA
−40
+105
°C
Operation at 105°C requires reduction of the
maximum load current as specified in Table 19
Each voltage is relative to its respective ground
VDD1
VDD1
3.0
4.5
5.5
5.5
V
V
Rev. C | Page 9 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 19.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
Supply Voltages (VDD1, VISO)1
Input Voltage (VIA, VIB, VE1, VE2, VSEL,
RCIN, RCSEL)1, 2
Output Voltage (VOA, VOB)1, 2
Average Output Current per Pin3
Common-Mode Transients4
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−100 kV/µs to +100 kV/µs
ESD CAUTION
1
Each voltage is relative to its respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides
of a given channel, respectively. See the PCB Layout section.
3
See Figure 5 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the isolation barrier. Commonmode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
2
Table 20. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
424
Unit
V peak
Applicable Certification
All certifications, 50-year operation
600
565
V peak
V peak
Working voltage per IEC 60950-1
600
565
V peak
V peak
Working voltage per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Rev. C | Page 10 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16
VISO
GND1 2
15
GNDISO
14
VOA
VIB 4
RCIN 5
ADuM6200
13 VOB
TOP VIEW
(Not to Scale) 12 NC
RCSEL 6
11
VSEL
NC 7
10
VE2
GND1 8
9
GNDISO
NC = NO CONNECT
08775-006
VIA 3
Figure 6. ADuM6200 Pin Configuration
Table 21. ADuM6200 Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
VIA
VIB
RCIN
6
RCSEL
7, 12
9, 15
NC
GNDISO
10
VE2
11
VSEL
13
14
16
VOB
VOA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Input B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low.
This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side
of the isolator, damaging the ADuM6200 and possibly the devices that it powers.
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external
regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
No Internal Connection.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
Data Enable Input. When this pin is high or not connected, the secondary outputs are active; when this pin is
low, the outputs are in a high-Z state.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
Logic Output B.
Logic Output A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
Rev. C | Page 11 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
VDD1 1
16
VISO
GND1 2
15
GNDISO
14
VOA
RCIN 5
ADuM6201
13 VIB
TOP VIEW
(Not to Scale) 12 NC
RCSEL 6
11
VSEL
VE1 7
10
VE2
GND1 8
9
GNDISO
NC = NO CONNECT
08775-007
VIA 3
VOB 4
Figure 7. ADuM6201 Pin Configuration
Table 22. ADuM6201 Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
VIA
VOB
RCIN
6
RCSEL
7
VE1
9, 15
GNDISO
10
VE2
11
VSEL
12
13
14
16
NC
VIB
VOA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Output B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low.
This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side
of the isolator, damaging the ADuM6201 and possibly the devices that it powers.
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external
regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low,
the output is in a high-Z state.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
Data Enable Input. When this pin is high or not connected, the secondary output is active; when this pin is low,
the output is in a high-Z state.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
No Internal Connection.
Logic Input B.
Logic Output A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
Rev. C | Page 12 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
VDD1 1
16
VISO
GND1 2
15
GNDISO
VOA 3
14
VIA
RCIN 5
ADuM6202
13 VIB
TOP VIEW
(Not to Scale) 12 NC
RCSEL 6
11
VSEL
VE1 7
10
NC
GND1 8
9
GNDISO
NC = NO CONNECT
08775-008
VOB 4
Figure 8. ADuM6202 Pin Configuration
Table 23. ADuM6202 Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
VOA
VOB
RCIN
6
RCSEL
7
VE1
9, 15
GNDISO
10, 12
11
NC
VSEL
13
14
16
VIB
VIA
VISO
Description
Primary Supply Voltage, 3.0 V to 5.5 V.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Logic Output A.
Logic Output B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low.
This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side
of the isolator, damaging the ADuM6202 and possibly the devices that it powers.
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external
regulation. This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
Data Enable Input. When this pin is high or not connected, the primary outputs are active; when this pin is low,
the outputs are in a high-Z state.
Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
No Internal Connection.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
Logic Input B.
Logic Input A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
TRUTH TABLE
Table 24. Power Control Truth Table (Positive Logic)
RCSEL
Input
High
High
High
High
Low
Low
Low
1
RCIN
Input
X
X
X
X
High
Low
RCOUT(EXT)
VSEL
Input
High
Low
Low
High
X
X
X
VDD1
Input1
5V
5V
3.3 V
3.3 V
X
X
X1
VISO
Output
5V
3.3 V
3.3 V
5V
X
0V
X
Operation
Self-regulation mode, normal operation
Self-regulation mode, normal operation
Self-regulation mode, normal operation
This supply configuration is not recommended due to extremely poor efficiency
Part runs at maximum open-loop voltage; damage can occur
Power supply disabled
Slave mode; RCOUT(EXT) supplied by a master isoPower device
VDD1 must be common between all isoPower devices being regulated by a master isoPower part.
Rev. C | Page 13 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
30
3.5
INPUT CURRENT (A)
20
15
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
10
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
IDD1
5
0.5
0
20
40
60
80
100
120
IISO CURRENT (mA)
0.5
0
3.0
08775-124
0
3.5
4.0
4.5
5.0
5.5
0
6.5
6.0
INPUT SUPPLY VOLTAGE (V)
Figure 9. Typical Power Supply Efficiency
in All Supported Power Configurations
Figure 12. Typical Short-Circuit Input Current and Power
vs. VDD1 Supply Voltage
120
5.4
5.2
VISO (V)
100
IISO CURRENT (mA)
3.5
POWER
08775-036
EFFICIENCY (%)
25
4.0
POWER (W)
35
80
5.0
4.8
60
4.6
40
50
100
150
200
250
300
IDD1 CURRENT (mA)
0
10% LOAD
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ms)
Figure 13. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
Figure 10. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
1200
3.7
3.5
VISO (V)
1000
800
3.3
3.1
600
60
400
40
0
0
20
40
60
80
IISO CURRENT (mA)
100
120
Figure 11. Typical Total Power Dissipation vs. Isolated Output Supply
Current in All Supported Power Configurations
Rev. C | Page 14 of 28
90% LOAD
20
10% LOAD
10% LOAD
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ms)
Figure 14. Typical VISO Transient Load Response, 3.3 V Output,
10% to 90% Load Step
08775-128
200
IISO (mA)
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
08775-126
TOTAL POWER DISSIPATION (mW)
10% LOAD
08775-127
0
90% LOAD
20
0
08775-125
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
20
0
IISO (mA)
40
Data Sheet
ADuM6200/ADuM6201/ADuM6202
5.02
5
5.00
4
VISO (V)
4.98
VISO (V)
4.96
4.94
4.92
3
2
5.0
90% LOAD
10% LOAD
1
0
0
0.5
1.0
1.5
2.0
2.5
TIME (µs)
3.0
3.5
4.0
0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ms)
Figure 15. Typical Output Voltage Ripple at 90% Load, VISO = 5 V
08775-132
2.5
08775-129
RC
SIGNAL (V)
4.90
Figure 18. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V
3.34
20
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
3.32
SUPPLY CURRENT (mA)
3.28
3.26
8
4
2
0
0
0.5
1.0
1.5
2.0
2.5
TIME (µs)
3.0
3.5
4.0
0
08775-130
RC
SIGNAL (V)
3.24
4
12
0
5
10
15
DATA RATE (Mbps)
20
25
08775-041
VISO (V)
16
3.30
Figure 19. Typical ICHn Supply Current per Forward Data Channel
(15 pF Output Load)
Figure 16. Typical Output Voltage Ripple at 90% Load, VISO = 3.3 V
7
20
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
6
SUPPLY CURRENT (mA)
16
4
3
2
90% LOAD
10% LOAD
12
8
4
0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
TIME (ms)
3.0
Figure 17. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 5 V
0
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 20. Typical ICHn Supply Current per Reverse Data Channel
(15 pF Output Load)
Rev. C | Page 15 of 28
08775-042
1
08775-131
VISO (V)
5
ADuM6200/ADuM6201/ADuM6202
Data Sheet
3.0
5
2.5
SUPPLY CURRENT (mA)
3
5V
2
3.3V
1
1.5
5V
1.0
3.3V
0
5
10
15
DATA RATE (Mbps)
20
25
0
Figure 21. Typical IISO(D) Dynamic Supply Current per Input
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 22. Typical IISO(D) Dynamic Supply Current per Output
(15 pF Output Load)
Rev. C | Page 16 of 28
08775-044
0
2.0
0.5
08775-043
SUPPLY CURRENT (mA)
4
Data Sheet
ADuM6200/ADuM6201/ADuM6202
TERMINOLOGY
IDD1(Q)
IDD1(Q) is the minimum operating current drawn at the VDD1
pin when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic
supply current. IDD1(Q) reflects the minimum current operating
condition.
IDD1(D)
IDD1(D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1(MAX)
IDD1(MAX) is the input current under full dynamic and VISO load
conditions.
IISO(LOAD)
IISO(LOAD) is the current available to the load.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
The tPLH propagation delay is measured from the 50% level of
the rising edge of the VIx signal to the 50% level of the rising
edge of the VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/
or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the
recommended operating conditions.
Channel-to-Channel Matching (tPSKCD/tPSKOD)
Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. C | Page 17 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
APPLICATIONS INFORMATION
The ADuM620x implements undervoltage lockout (UVLO)
with hysteresis on the VDD1 power input. This feature ensures
that the converter does not enter oscillation due to noisy input
power or slow power-on ramp rates.
The ADuM620x can accept an external regulation control
signal (RCIN) that can be connected to other isoPower devices.
This feature allows a single regulator to control multiple power
modules without contention. When accepting control from a
master power module, the VISO pins can be connected together,
adding their power. Because there is only one feedback control
path, the supplies work together seamlessly. The ADuM620x
can only regulate itself or accept regulation (slave device) from
another device in this product line; it cannot provide a
regulation signal to other devices.
PCB LAYOUT
The ADuM620x digital isolators with 0.4 W isoPower integrated
dc-to-dc converter require no external interface circuitry for the
logic interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 23). Note that low ESR bypass
capacitors are required between Pin 1 and Pin 2 and between
Pin 15 and Pin 16, as close to the chip pads as possible.
The power supply section of the ADuM620x uses a 180 MHz
oscillator frequency to pass power efficiently through its chip
scale transformers. In addition, the normal operation of the data
section of the iCoupler introduces switching transients on the
power supply pins. Bypass capacitors are required for several
operating frequencies. Noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and
proper regulation require a large value capacitor. These capacitors
are most conveniently connected between Pin 1 and Pin 2 for
VDD1, and between Pin 15 and Pin 16 for VISO.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 µF and 10 µF for VDD1 and VISO. The smaller
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.
The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1
and Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
BYPASS < 2mm
VDD1
VISO
GND1
GNDISO
VIA/VOA
VOA/VIA
VIB/VOB
VOB/VIB
NC
RCIN
VSEL
RCSEL
VE1/NC
VE2/NC
GND1
GNDISO
08775-020
The dc-to-dc converter section of the ADuM620x works on
principles that are common to most switching power supplies. It
has a secondary side controller architecture with isolated pulsewidth modulation (PWM) feedback. VDD1 power is supplied to
an oscillating circuit that switches current into a chip scale air
core transformer. Power transferred to the secondary side is
rectified and regulated to either 3.3 V or 5 V. The secondary
(VISO) side controller regulates the output by creating a PWM
control signal that is sent to the primary (VDD1) side by a dedicated
iCoupler data channel. The PWM modulates the oscillator
circuit to control the power being sent to the secondary side.
Feedback allows for significantly higher power and efficiency.
Figure 23. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Table 19, thereby leading to latch-up and/or
permanent damage.
The ADuM620x is a power device that dissipates approximately
1 W of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation device,
the device primarily depends on heat dissipation into the PCB
through the GND pins. If the device is used at high ambient
temperatures, provide a thermal path from the GND pins to the
PCB ground plane. The board layout in Figure 23 shows enlarged
pads for Pin 8 (GND1) and Pin 9 (GNDISO). Multiple vias should
be implemented from the pad to the ground plane to significantly
reduce the temperature inside the chip. The dimensions of the
expanded pads are at the discretion of the designer and depend
on the available board space.
START-UP BEHAVIOR
The ADuM620x devices do not contain a soft start circuit.
Therefore, the start-up current and voltage behavior must be
taken into account when designing with this device.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the VDD1 slew rate.
With a fast VDD1 slew rate (200 µs or less), the peak current draws
up to 100 mA/V of VDD1. The input voltage goes high faster than
the output can turn on, so the peak current is proportional to
the maximum input voltage.
Rev. C | Page 18 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM620x devices may not be able to drive the output to
the regulation point if a current-limiting device clamps the VDD1
voltage during startup. As a result, the ADuM620x devices can
draw large amounts of current at low voltage for extended
periods of time.
The output voltage of the ADuM620x devices exhibits VISO
overshoot during startup. If this overshoot could potentially
damage components attached to VISO, a voltage-limiting device
such as a Zener diode can be used to clamp the voltage. Typical
behavior is shown in Figure 17 and Figure 18.
EMI CONSIDERATIONS
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 1 µs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 µs, the
input side is assumed to be unpowered or nonfunctional, and
the isolator output is forced to a default state by the watchdog
timer circuit.
The limitation on the magnetic field immunity of the ADuM620x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3.3 V operating condition of the
ADuM620x is examined because it represents the most susceptible mode of operation.
The dc-to-dc converter section of the ADuM620x devices must
operate at 180 MHz to allow efficient power transfer through the
small transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge emissions and dipole radiation between the primary and
secondary ground planes. Grounded enclosures are recommended
for applications that use these devices. If grounded enclosures
are not possible, follow good RF design practices in the layout
of the PCB. See the AN-0971 Application Note for board layout
recommendations.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
PROPAGATION DELAY PARAMETERS
Given the geometry of the receiving coil in the ADuM620x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 25.
50%
OUTPUT (VOx)
tPHL
50%
08775-118
tPLH
Figure 24. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM620x component.
100
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM620x
components operating under the same conditions.
10
1
0.1
0.01
0.001
1k
1M
10k
100k
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 25. Maximum Allowable External Magnetic Flux Density
Rev. C | Page 19 of 28
08775-119
INPUT (VIx)
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high output.
V = (−dβ/dt) ∑ πrn2; n = 1, 2, … , N
ADuM6200/ADuM6201/ADuM6202
Data Sheet
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM620x transformers. Figure 26 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 26, the ADuM620x is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example noted, a 0.5 kA current placed 5 mm away from
the ADuM620x is required to affect the operation of the device.
MAXIMUM ALLOWABLE CURRENT (kA)
1000
DISTANCE = 1m
IISO
IDD1(Q)
IDD1(D)
CONVERTER
PRIMARY
IDDP(D)
PRIMARY
DATA I/O
2-CHANNEL
CONVERTER
SECONDARY
IISO(D)
SECONDARY
DATA I/O
2-CHANNEL
08775-021
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces
the received pulse from >1.0 V to 0.75 V—still well above the
0.5 V sensing threshold of the decoder.
Figure 27. Power Consumption Within the ADuM620x
Both dynamic input and output current is consumed only
when operating at channel speeds higher than the refresh
rate, fr. Each channel has a dynamic current determined by
its data rate. Figure 19 shows the current for a channel in the
forward direction, which means that the input is on the primary
side of the part. Figure 20 shows the current for a channel in the
reverse direction, which means that the input is on the secondary
side of the part. Both figures assume a typical 15 pF load. The
following relationship allows the total IDD1 current to be calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + ∑ ICHn; n = 1 to 4
100
where:
IDD1 is the total supply input current.
IISO is the current drawn by the secondary side external loads.
E is the power supply efficiency at the maximum load from
Figure 9 at the VISO and VDD1 condition of interest.
ICHn is the current drawn by a single channel, determined from
Figure 19 or Figure 20, depending on channel direction.
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
08775-120
0.01
1k
(1)
Figure 26. Maximum Allowable Current
for Various Current-to-ADuM620x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data
channels as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined
separately. All of these quiescent power demands are combined
into the IDD1(Q) current shown in Figure 27. The total IDD1 supply
current is the sum of the quiescent operating current, the dynamic
current IDD1(D) demanded by the I/O channels, and any external
IISO load.
Calculate the maximum external load by subtracting the
dynamic output load from the maximum allowable load.
IISO(LOAD) = IISO(MAX) − ∑ IISO(D)n; n = 1 to 4
(2)
where:
IISO(LOAD) is the current available to supply an external secondary
side load.
IISO(MAX) is the maximum external secondary side load current
available at VISO.
IISO(D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 19 and Figure 20 for a
typical 15 pF load.
This analysis assumes a 15 pF capacitive load on each data output.
If the capacitive load is larger than 15 pF, the additional current
must be included in the analysis of IDD1 and IISO(LOAD).
To determine IDD1 in Equation 1, additional primary side
dynamic output current (IAOD) is added directly to IDD1.
Additional secondary side dynamic output current (IAOD)
is added to IISO on a per-channel basis.
Rev. C | Page 20 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
To determine IISO(LOAD) in Equation 2, additional secondary
side output current (IAOD) is subtracted from IISO(MAX) on a
per-channel basis.
For each output channel with CL greater than 15 pF, the
additional capacitive supply current is given by
−3
IAOD = 0.5 × 10 × ((CL − 15) × VISO) × (2f − fr); f > 0.5 fr
(3)
where:
CL is the output load capacitance (pF).
VISO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate expressed in units of Mbps.
fr is the input channel refresh rate (Mbps).
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADuM620x is protected against damage due to excessive
power dissipation by thermal overload protection circuits.
Thermal overload protection limits the junction temperature to
a maximum of 150°C (typical). Under extreme conditions (that
is, high ambient temperature and power dissipation), when the
junction temperature starts to rise above 150°C, the PWM is
turned off, turning off the output current. When the junction
temperature drops below 130°C (typical), the PWM turns on
again, restoring the output current to its nominal value.
Consider the case where a hard short from VISO to ground occurs.
At first, the ADuM620x reaches its maximum current, which is
proportional to the voltage applied at VDD1. Power dissipates on
the primary side of the converter (see Figure 12). If self-heating
of the junction becomes great enough to cause its temperature
to rise above 150°C, thermal shutdown is activated, turning off
the PWM and turning off the output current. As the junction
temperature cools and drops below 130°C, the PWM turns on
and power dissipates again on the primary side of the converter,
causing the junction temperature to rise to 150°C again. This
thermal oscillation between 130°C and 150°C causes the part
to cycle on and off as long as the short remains at the output.
Thermal limit protections are intended to protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation to prevent junction
temperatures from exceeding 130°C.
POWER CONSIDERATIONS
The ADuM6200/ADuM6201/ADuM6202 power input, data
input channels on the primary side, and data input channels on
the secondary side are all protected from premature operation
by undervoltage lockout (UVLO) circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive,
and all input channel drivers and refresh circuits are idle. Outputs
remain in a high impedance state to prevent transmission of
undefined states during power-up and power-down operations.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary VISO voltage is below its UVLO limit at this point;
the regulation control signal from the secondary side is not being
generated. The primary side power oscillator is allowed to free
run under these conditions, supplying the maximum amount of
power to the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VDD1. When the
regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator
on the primary side. The VDD1 current is then reduced and is
proportional to the load current. The inrush current is less than
the short-circuit current shown in Figure 12. The duration of
the inrush current depends on the VISO loading conditions and
on the current and voltage available at the VDD1 pin.
As the secondary side converter begins to accept power from the
primary, the VISO voltage starts to rise. When the secondary side
UVLO is reached, the secondary side outputs are initialized to
their default low state until data is received from the corresponding primary side input. It can take up to 1 µs after the secondary
side is initialized for the state of the output to correlate to the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 µs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the converter sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs
and the outputs are set to their default low value before the
secondary power reaches UVLO.
Rev. C | Page 21 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
THERMAL ANALYSIS
The ADuM620x devices consist of four internal silicon die
attached to a split lead frame with two die attach paddles. For
the purposes of thermal analysis, the device is treated as a thermal
unit with the highest junction temperature reflected in the θJA
value from Table 14. The value of θJA is based on measurements
taken with the part mounted on a JEDEC standard 4-layer board
with fine width traces and still air. Under normal operating
conditions, the ADuM620x operates at full load across the full
temperature range without derating the output current. However, following the recommendations in the PCB Layout section
decreases the thermal resistance to the PCB, allowing increased
thermal margin at high ambient temperatures.
INCREASING AVAILABLE POWER
The ADuM620x devices are designed to work in combination
with the ADuM6000 in a master/slave configuration. The RCIN
and RCSEL pins allow the ADuM620x to receive a PWM signal
from an ADuM6000 through its RCIN pin and to act as a slave to
that control signal. The RCSEL pin chooses whether the part acts
as a standalone, self-regulated device or as a slave device.
When the ADuM620x acts as a slave, its power is regulated by a
PWM signal from a master device. This allows multiple isoPower
parts to be combined in parallel while sharing the load equally.
When the ADuM620x is configured as a standalone unit, it
generates its own PWM feedback signal to regulate itself.
The ADuM620x devices can function as slave or standalone
devices. All devices in the ADuM5xxx and ADuM6xxx family
can function as standalone devices. Some of these devices also
function as master devices or slave devices, but not both (see
Table 25).
Table 25. Function of isoPower Parts
Part No.
ADuM6000
ADuM620x
ADuM640x
ADuM5000
ADuM520x
ADuM5400
ADuM5401 to
ADuM5404
Master
Yes
No
No
Yes
No
No
Yes
Function
Slave
Yes
Yes
No
Yes
Yes
No
No
Standalone
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Table 26 illustrates how isoPower devices can provide many
combinations of data channel count and multiples of the singleunit power.
Table 26. Configurations for Power and Data Channels
Power Units
1-Unit Power
0 Channels
ADuM6000 or ADuM5000 (standalone)
Number of Data Channels
2 Channels
ADuM620x or ADuM520x (standalone)
2-Unit Power
ADuM6000 or ADuM5000 (master)
ADuM6000 or ADuM5000 (slave)
ADuM6000 or ADuM5000 (master)
ADuM620x or ADuM520x (slave)
3-Unit Power
ADuM6000 or ADuM5000 (master)
ADuM6000 or ADuM5000 (slave)
ADuM6000 or ADuM5000 (slave)
ADuM6000 or ADuM5000 (master)
ADuM6000 or ADuM5000 (slave)
ADuM620x or ADuM520x (slave)
Rev. C | Page 22 of 28
4 Channels
ADuM5401, ADuM5402, ADuM5403,
ADuM5404, or ADuM640x (standalone)
ADuM5401, ADuM5402, ADuM5403,
ADuM5404 (master)
ADuM6000 or ADuM5000 (slave)
ADuM6000 or ADuM5000 (master)
ADuM620x or ADuM520x (slave)
ADuM620x or ADuM520x (slave)
Data Sheet
ADuM6200/ADuM6201/ADuM6202
The insulation lifetime of the ADuM620x devices depends on
the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 28, Figure 29, and Figure 30 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.
RATED PEAK VOLTAGE
08775-121
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 20 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than
the 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
Any cross-insulation voltage waveform that does not conform
to Figure 29 or Figure 30 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 20. The voltage presented in Figure 29 is
shown as sinusoidal for illustration purposes only. It is meant to
represent any voltage waveform varying between 0 V and some
limiting value. The limiting value can be positive or negative,
but the voltage cannot cross 0 V.
0V
Figure 28. Bipolar AC Waveform
RATED PEAK VOLTAGE
08775-122
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM620x devices.
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 20 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.
0V
Figure 29. Unipolar AC Waveform
RATED PEAK VOLTAGE
08775-123
INSULATION LIFETIME
0V
Figure 30. DC Waveform
Rev. C | Page 23 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
13.00 (0.5118)
12.60 (0.4961)
16
9
7.60 (0.2992)
7.40 (0.2913)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
8
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
SEATING
PLANE
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
10-12-2010-A
1
Figure 32. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-1)
Dimensions shown in millimeters and (inches)
Rev. C | Page 24 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
ORDERING GUIDE
Model 1, 2
ADuM6200ARWZ
ADuM6200CRWZ
ADuM6200ARIZ
ADuM6200CRIZ
ADuM6201ARWZ
ADuM6201CRWZ
ADuM6201ARIZ
ADuM6201CRIZ
ADuM6202ARWZ
ADuM6202CRWZ
ADuM6202ARIZ
ADuM6202CRIZ
1
2
Number
of Inputs,
VDD1 Side
2
2
2
2
1
1
1
1
0
0
0
0
Number
of Inputs,
VISO Side
0
0
0
0
1
1
1
1
2
2
2
2
Maximum
Data Rate
(Mbps)
1
25
1
25
1
25
1
25
1
25
1
25
Maximum
Propagation
Delay, 5 V (ns)
100
70
100
70
100
70
100
70
100
70
100
70
Maximum
Pulse Width
Distortion (ns)
40
3
40
3
40
3
40
3
40
3
40
3
Z = RoHS Compliant Part.
Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.
Rev. C | Page 25 of 28
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_IC
16-Lead SOIC_IC
Package
Option
RW-16
RW-16
RI-16-1
RI-16-1
RW-16
RW-16
RI-16-1
RI-16-1
RW-16
RW-16
RI-16-1
RI-16-1
ADuM6200/ADuM6201/ADuM6202
Data Sheet
NOTES
Rev. C | Page 26 of 28
Data Sheet
ADuM6200/ADuM6201/ADuM6202
NOTES
Rev. C | Page 27 of 28
ADuM6200/ADuM6201/ADuM6202
Data Sheet
NOTES
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08775-0-6/12(C)
Rev. C | Page 28 of 28