Fairchild FQI12N20L 200v logic n-channel mosfet Datasheet

FQB12N20L / FQI12N20L
200V LOGIC N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply, motor control.
•
•
•
•
•
•
•
11.6A, 200V, RDS(on) = 0.28Ω @VGS = 10 V
Low gate charge ( typical 16 nC)
Low Crss ( typical 17 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Low level gate drive requirement allowing direct
opration from logic drivers
D
D
!
"
G
S
D2-PAK
G D S
FQB Series
Absolute Maximum Ratings
Symbol
VDSS
ID
! "
"
"
G!
I2-PAK
!
FQI Series
S
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
FQB12N20L / FQI12N20L
200
Units
V
11.6
A
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
(Note 1)
7.35
A
46.4
A
VGSS
Gate-Source Voltage
± 20
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
210
mJ
IAR
Avalanche Current
(Note 1)
11.6
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
(Note 1)
9.0
5.5
3.5
mJ
V/ns
W
90
0.72
-55 to +150
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
Max
1.39
Units
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient *
--
40
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
FQB12N20L / FQI12N20L
February 2001
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
200
--
--
V
--
0.14
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
VDS = 200 V, VGS = 0 V
--
--
1
µA
VDS = 160 V, TC = 125°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 20 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -20 V, VDS = 0 V
--
--
-100
nA
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1.0
--
2.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 5.8 A
VGS = 5 V, ID = 5.8 A
--
0.22
0.25
0.28
0.32
Ω
gFS
Forward Transconductance
VDS = 30 V, ID = 5.8 A
--
12.7
--
S
--
830
1080
pF
--
120
155
pF
--
17
22
pF
IDSS
IGSSF
IGSSR
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 100 V, ID = 11.6 A,
RG = 25 Ω
(Note 4, 5)
VDS = 160 V, ID = 11.6 A,
VGS = 5 V
(Note 4, 5)
--
15
40
ns
--
190
390
ns
--
60
130
ns
--
120
250
ns
--
16
21
nC
--
2.8
--
nC
--
7.6
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
11.6
A
ISM
--
--
46.4
A
--
--
1.5
V
VGS = 0 V, IS = 11.6 A,
dIF / dt = 100 A/µs
--
128
--
ns
--
0.56
--
µC
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 11.6 A
Drain-Source Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 2.3mH, IAS = 11.6A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 11.6A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Electrical Characteristics
FQB12N20L / FQI12N20L
Typical Characteristics
VGS
10 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
Top :
ID , Drain Current [A]
1
10
ID, Drain Current [A]
1
10
0
10
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
-1
150℃
25℃
0
10
-55℃
※ Notes :
1. VDS = 30V
2. 250μs Pulse Test
-1
10
10
-1
0
10
1
10
0
10
2
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS , Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
1.2
1
10
IDR, Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
1.5
VGS = 5 V
0.9
VGS = 10V
0.6
0.3
150℃
25℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
-1
10
0.0
0
6
12
18
24
30
0.2
36
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID , Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
1800
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1200
Ciss
900
Coss
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
600
Crss
300
10
VGS, Gate-Source Voltage [V]
1500
Capacitance [pF]
0
10
VDS = 40V
VDS = 100V
8
VDS = 160V
6
4
2
※ Note : ID = 11.6 A
0
-1
10
0
10
1
10
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2001 Fairchild Semiconductor Corporation
0
0
5
10
15
20
25
30
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Typical Characteristics
(Continued)
3.0
1.2
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 5.8 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
12
Operation in This Area
is Limited by R DS(on)
2
10
9
ID, Drain Current [A]
ID, Drain Current [A]
100 µs
1 ms
1
10
10 ms
DC
0
10
※ Notes :
6
3
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
1
10
0
25
2
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
0
D = 0 .5
※ N o te s :
1 . Z θ J C ( t) = 1 .3 9 ℃ /W M a x .
2 . D u ty F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C ( t)
0 .2
0 .1
10
-1
0 .0 5
PDM
0 .0 2
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
t1
0 .0 1
Z
s i n g l e p u ls e
10
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
5V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
5V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2001 Fairchild Semiconductor Corporation
ID (t)
VDS (t)
VDD
tp
Time
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Package Dimensions
4.50 ±0.20
9.90 ±0.20
+0.10
2.00 ±0.10
2.54 TYP
(0.75)
°
~3
0°
0.80 ±0.10
1.27 ±0.10
2.54 ±0.30
15.30 ±0.30
0.10 ±0.15
2.40 ±0.20
4.90 ±0.20
1.40 ±0.20
9.20 ±0.20
1.30 –0.05
1.20 ±0.20
(0.40)
D2PAK
+0.10
0.50 –0.05
2.54 TYP
9.20 ±0.20
(2XR0.45)
4.90 ±0.20
15.30 ±0.30
10.00 ±0.20
(7.20)
(1.75)
10.00 ±0.20
(8.00)
(4.40)
0.80 ±0.10
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
(Continued)
I2PAK
4.50 ±0.20
(0.40)
9.90 ±0.20
+0.10
MAX13.40
9.20 ±0.20
(1.46)
1.20 ±0.20
1.30 –0.05
0.80 ±0.10
2.54 TYP
2.54 TYP
10.08 ±0.20
1.47 ±0.10
MAX 3.00
(0.94)
13.08 ±0.20
)
5°
(4
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
10.00 ±0.20
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
FQB12N20L / FQI12N20L
Package Dimensions
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HiSeC™
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MICROWIRE™
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OPTOPLANAR™
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PowerTrench®
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QS™
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LILENT SWITCHER®
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SuperSOT™-3
SuperSOT™-6
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when properly used in accordance with instructions for use
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2001 Fairchild Semiconductor Corporation
Rev. G