Revised January 1999 CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate General Description Features The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. ■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range All inputs protected against static discharge with diodes to VDD and VSS. Ordering Code: Order Number CD4071BCM Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4071BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4081BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4081BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC CD4071B CD4081B Top View Top View © 1999 Fairchild Semiconductor Corporation DS005977.prf www.fairchildsemi.com CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate October 1987 CD4071BC • CD4081BC Schematic Diagrams CD4071B 1 /4 of device shown J=A+B Logical “1” = HIGH Logical “0” = LOW *All inputs protected by standard CMOS protection circuit. CD4081B 1/ 4 of device shown J=A•B Logical “1” = HIGH Logical “0” = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to VDD +0.5V Voltage at Any Pin Operating Range (VDD ) Power Dissipation (PD) 3 VDC to 15 VDC Operating Temperature Range (TA) Dual-In-Line 700 mW Small Outline 500 mW −0.5 VDC to +18 VDC VDD Range −65°C to +150°C Storage Temperature (TS) Lead Temperature (TL) (Soldering, 10 seconds) Note 2: All voltages measured with respect to VSS unless otherwise specified. 260°C DC Electrical Characteristics −40°C to +85°C CD4071BC, CD4081BC Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. (Note 2) CD4071BC/CD4081BC Symbol IDD VOL Parameter −40°C Conditions Min IOL IOH IIN Max Min Units Max VDD = 5V 1 0.004 1 7.5 µA VDD = 10V 2 0.005 2 15 µA VDD = 15V 4 0.006 4 30 µA LOW Level VDD = 5V 0.05 0 0.05 0.05 V Output Voltage VDD = 10V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 |IO| < 1 µA HIGH Level VDD = 5V 4.95 VDD = 10V |IO| < 1 µA VDD = 15V VIH +85°C Typ Quiescent Device Output Voltage VIL Min Current VDD = 15V VOH +25°C Max 4.95 5 V 4.95 V 9.95 9.95 10 9.95 V 14.95 14.95 15 14.95 V LOW Level VDD = 5V, VO = 0.5V 1.5 2 1.5 1.5 V Input Voltage VDD = 10V, VO = 1.0V 3.0 4 3.0 3.0 V VDD = 15V, VO = 1.5V 4.0 6 4.0 4.0 V HIGH Level VDD = 5V, VO = 4.5V 3.5 3.5 3 3.5 V Input Voltage VDD = 10V, VO = 9.0V 7.0 7.0 6 7.0 V VDD = 15V, VO = 13.5V 11.0 11.0 9 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA mA Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 (Note 3) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA mA Current VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 (Note 3) VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 Input Current VDD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA VDD = 15V, VIN = 15V 0.30 10−5 0.30 1.0 µA mA Note 3: IOH and IOL are tested one output at a time. AC Electrical Characteristics (Note 4) CD4071BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C Symbol Parameter Conditions Typ tPHL tPLH tTHL, tTLH Max Units Propagation Delay Time, VDD = 5V 100 250 ns HIGH-to-LOW Level VDD = 10V 40 100 ns VDD = 15V 30 70 ns Propagation Delay Time, VDD = 5V 90 250 ns LOW-to-HIGH Level VDD = 10V 40 100 ns VDD = 15V 30 70 ns ns Transition Time VDD = 5V 90 200 VDD = 10V 50 100 ns VDD = 15V 40 80 ns 7.5 pF CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 18 pF Note 4: AC Parameters are guaranteed by DC correlated testing. 3 www.fairchildsemi.com CD4071BC • CD4081BC Absolute Maximum Ratings(Note 1) (Note 2) CD4071BC • CD4081BC AC Electrical Characteristics (Note 5) CD4081BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C Symbol tPHL tPLH tTHL, tTLH Typ Max Units Propagation Delay Time, Parameter VDD = 5V 100 250 ns HIGH-to-LOW Level VDD = 10V 40 100 ns VDD = 15V 30 70 ns Propagation Delay Time, VDD = 5V 120 250 ns LOW-to-HIGH Level VDD = 10V 50 100 ns VDD = 15V 35 70 ns ns Transition Time Conditions VDD = 5V 90 200 VDD = 10V 50 100 ns VDD = 15V 40 80 ns 7.5 pF CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 18 Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics www.fairchildsemi.com Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics 4 pF CD4071BC • CD4081BC Typical Performance Characteristics (Continued) 5 www.fairchildsemi.com CD4071BC • CD4081BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued)