ON MC14015BDR2 4−bit full adder Datasheet

MC14008B
4−Bit Full Adder
The MC14008B 4−bit full adder is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal look−ahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
high−speed operation when used with other adders in a system.
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Features
•
•
•
•
•
•
•
Look−Ahead Carry Output
Diode Protection on All Inputs
All Outputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4008B
Pb−Free Packages are Available*
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC14008BCP
AWLYYWWG
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Vin, Vout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
Iin, Iout
SOIC−16
D SUFFIX
CASE 751B
14008BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
TA
Ambient Temperature Range
−55 to +125
°C
ORDERING INFORMATION
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
Publication Order Number:
MC14008B/D
MC14008B
PIN ASSIGNMENT
A4
1
16
VDD
B3
2
15
B4
A3
3
14
Cout
B2
4
13
S4
A2
5
12
S3
B1
6
11
S2
A1
7
10
S1
VSS
8
9
Cin
TRUTH TABLE
(One Stage)
Cin
B
A
Cout
S
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
BLOCK DIAGRAM
HIGH−SPEED
PARALLEL CARRY
B4 15
A4
1
B3
2
A3
3
B2
4
A2
5
B1
6
A1
7
Cin
9
14C out
ADDER
4
13S4
C4
ADDER
3
12S3
C3
ADDER
2
11S2
C2
ADDER
1
10S1
VDD = PIN 16
VSS = PIN 8
ORDERING INFORMATION
Package
Shipping †
MC14015BCP
PDIP−16
500 Units / Rail
MC14015BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14015BDR2
SOIC−16
2500 Units / Tape & Reel
MC14015BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14008B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
Characteristic
Symbol
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
− 1.3
− 3.4
– 4.2
– 0.88
– 2.25
− 8.8
—
—
—
—
– 1.7
− 0.36
– 0.9
− 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
mAdc
IT
5.0
10
15
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (1.7 mA/kHz) f + IDD
IT = (3.4 mA/kHz) f + IDD
IT = (5.0 mA/kHz) f + IDD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.005.
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3
mAdc
MC14008B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Min
Typ
(Note 6)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
tTLH,
tTHL
Propagation Delay Time
Sum in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns
Sum In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
Carry In to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 290 ns
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 85 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 30 ns
VDD
Vdc
tPLH, tPHL
ns
5.0
10
15
—
—
—
400
160
115
800
320
230
5.0
10
15
—
—
—
305
145
110
610
290
220
5.0
10
15
—
—
—
375
155
115
750
310
230
5.0
10
15
—
—
—
170
75
55
340
150
110
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD = −VGS
Vout
VDD = VGS
16
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
8
16
S3
S2
Cout
VSS
Vout
IOH
EXTERNAL
POWER
SUPPLY
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
8
Figure 1. Typical Source Current
Characteristics Test Circuit
S3
S2
Cout
VSS
IOL
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Sink Current
Characteristics Test Circuit
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4
MC14008B
VDD
16
20 ns
Vin
20 ns
90%
10%
VDD
VSS
PULSE
GENERATOR
B4
A4
B3
A3
B2
A2
S4
B1
A1
Cin
S1
8
S3
S2
Cout
CL
VSS
CL
IDD
500 mF
Figure 3. Dynamic Power Dissipation Test Circuit and Waveform
VDD
16
B4
A4
B3
A3
B2
A2
B1
A1
PULSE
GENERATOR
Cin
8
S4
S3
S2
S1
Cout
CL
VSS
CL
CL
CL
IDD
20 ns
Cin
20 ns
VDD
90%
50%
10%
tPHL
tPLH
90%
50%
10%
S1 − S4
tTHL
Cout
tTLH
50%
tPLH
tPHL
VSS
VOH
VOL
VOH
VOL
Figure 4. Switching Time Test Circuit and Waveforms
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5
CL
CL
CL
CL
MC14008B
Cout
B4
S4
A4
B3
S3
A3
B2
S2
A2
B1
S1
A1
Cin
Figure 5. Logic Diagram
TYPICAL APPLICATION
WORD A + B INPUTS
A1
Cin
S1
B4
CHIP
1
Cout
S4
A1
Cin
S1
B4
CHIP
2
Cout
S4
A1
Cin
S1
B4
CHIP
3
Cout
S4
A1
Cin
B4
CHIP
4
S1
SUM OUTPUTS
Calculation of 16−bit adder speed:
tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16−bit adder speed at 10 V, 25°C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns
Figure 6. Using the MC14008B in a 16−Bit Adder Configuration
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6
Cout
S4
MC14008B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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7
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14008B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
1
8
−B−
P
8 PL
0.25 (0.010)
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
S
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MC14008B/D
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