Freescale MC68HRC705KJ1CP Migrating from the mc68hc705k1 to the mc68hc705kj1 Datasheet

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AN1746
Migrating from the MC68HC705K1 to the MC68HC705KJ1
By Mark Glenewinkel
Field Applications Engineering
Consumer Systems Group
Austin, Texas
Introduction
Freescale provides two different parts to migrate your current
MC68HC705K1 (K1) application easily. Depending on your design,
system enhancements, and cost, the MC68HC705KJ1 (KJ1) and the
MC68HC805K3 (K3) provide two different migration paths.
The major differences between the KJ1 and the K3 are:
•
Price
•
Pinout compatibility
The KJ1 is not pin for pin the same as the K1, but it is roughly 70% the
cost of the K1. Although the K3 is pin for pin the same as the K1, it is
roughly 90% the cost of the K1.
This application note illustrates the differences between the K1 and the
KJ1. Using the KJ1’s additional features can further enhance your
system design. Consult the K1 and KJ1 databooks for detailed design
reference. See References/Additional Reading in this application
note.
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Application Note
For information on migrating your design to the K3, consult the
application note titled Migrating from the MC68HC705K1 to the
MC68HC805K3, Freescale document order number AN1747/D.
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MC68HC705KJ1
Features
•
1240 bytes of user EPROM
•
64 bytes of low-power user RAM
•
4-MHz maximum internal bus frequency at 5 volts
•
15-stage multifunction timer
•
COP watchdog timer
•
10 bidirectional input/output (I/O) pins, including:
– 10-mA sink capability on all I/O pins
– 5.5-mA source capability on six I/O pins
– Software programmable pulldowns on all I/O pins
– Keyboard scan with selectable interrupt on four I/O pins
•
Selectable sensitivity on external interrupt; edge- and levelsensitive or edge-sensitive only
•
On-chip oscillator with options for:
– Crystal
– Ceramic resonator
– Resistor-capacitor (RC) oscillator (MC68HRC705KJ1) with or
without external resistor
– Low-speed (32 kHz) crystal (MC68HLC705KJ1)
– External clock
•
External interrupt mask bit and acknowledge bit
•
EPROM security bit1 to aid in locking out access to programmable
EPROM array
•
Selectable STOP conversion to HALT and option for fast restart
and power-on reset
•
Internal steering diode and pullup device on RESET pin to VDD
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
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Application Note
Migrating to the MC68HC705KJ1
Migrating to the MC68HC705KJ1
Pinouts and
Package Types
The KJ1 has a different pinout from the K1, making layout changes
necessary. See Figure 1 and Figure 2 for pin descriptions.
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Both parts are available in either plastic DIP or SOIC packages.
RESET
1
16
OSC1
PB1/OSC3
2
15
OSC2
PB0
3
14
VSS
IRQ/VPP
4
13
VDD
PA0
5
12
PA7
PA1
6
11
PA6
PA2
7
10
PA5
PA3
8
9
PA4
Figure 1. MC68HC705K1 Pinout
RESET
1
16
IRQ/VPP
OSC1
2
15
PA0
OSC2
3
14
PA1
PB3
4
13
PA2
PB2
5
12
PA3
VDD
6
11
PA4
VSS
7
10
PA5
PA7
8
9
PA6
Figure 2. MC68HC705KJ1 Pinout
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Application Note
Block Diagrams
Throughout this application note, refer to the block diagrams for the K1
in Figure 3 and KJ1 in Figure 4.
USER EPROM/OTPROM — 504 BYTES
MASK OPTION REGISTER (EPROM/OTPROM)
IRQ/VPP
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
PA6*
PA5*
PORT A
DATA DIRECTION REGISTER A
PA7*
USER RAM — 32 BYTES
PA4*
PA3**
PA2**
PA1**
PA0**
*8-mA-sink capability
**External interrupt capability
ACCUMULATOR
M68HC05
MCU
INDEX REGISTER
STACK POINTER
0 0 0 0 0 0 0 0 1 1 1
PROGRAM COUNTER
0 0 0 0 0 0
CONDITION CODE REGISTER
1 1 1 H I N C Z
PB0
TIMER
CLOCK
LOW-VOLTAGE
DETECT
PB1/OSC3
MULTIFUNCTION
TIMER
COP WATCHDOG
AND
ILLEGAL ADDRESS
DETECT
VDD
PORT B
RESET
DATA DIRECTION REGISTER B
RESET
CPU
CLOCK
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PERSONALITY EPROM/OTPROM— 64 BITS
VSS
OSC1
OSC2
INTERNAL
OSCILLATOR
DIVIDE
BY TWO
Figure 3. MC68HC705K1 Block Diagram
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Application Note
Migrating to the MC68HC705KJ1
OSC1
OSC2
INTERNAL
OSCILLATOR
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
DIVIDE
BY 2
CPU CONTROL
ALU
68HC05 CPU
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IRQ/VPP
ACCUMULATOR
CPU REGISTERS
INDEX REGISTER
0 0 0 0 0 0 0 0 1 1 STK PTR
PB3(1)
PORT B
RESET
DATA DIRECTION REGISTER B
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
PB2(1)
STATIC RAM (SRAM) – 64 BYTES
USER EPROM – 1240 BYTES
PA7
PA6
PA5
PORT A
CONDITION CODE
REGISTER 1 1 1 H I N Z C
DATA DIRECTION REGISTER A
PROGRAM COUNTER
PA4
PA3(1) (2)
PA2(1) (2)
PA1(1) (2)
PA0(1) (2)
10-mA sink capability on all I/O pins
MASK OPTION REGISTER (EPROM)
NOTES:
1. 5.5-mA source capability
2. External interrupt capability
Figure 4. MC68HC705KJ1 Block Diagram
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Application Note
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Memory Maps
and Registers
Figure 5 and Figure 6 show the memory maps and registers of the K1
and KJ1. Modify your code to reflect these changes:
•
The KJ1 has a total of 64 bytes of RAM. If you want to utilize this
additional memory of the KJ1, originate RAM memory to start at
$C0.
•
The KJ1 has a total of 1232 bytes of EPROM for code space.
Originate EPROM memory to start at $300.
•
Move the MOR register from location $17 on the K1 to location
$7F1 on the KJ1.
•
Move the location of the COP register from location $3F0 on the
K1 to location $7F0 on the KJ1.
•
Move the start of the interrupt vectors from location $3F8 on the
K1 to location $7F8 on the KJ1.
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Application Note
Migrating to the MC68HC705KJ1
$0000
$001F
$0020
I/O REGISTERS
32 BYTES
UNUSED
192 BYTES
$00DF
$00E0
SRAM
32 BYTES
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STACK
SRAM
32 BYTES
$00FF
$0100
UNUSED
256 BYTES
$01FF
$0200
USER EPROM
496 BYTES
$03EF
$03F0
TEST ROM AND
COP REGISTER
8 BYTES
$03F7
$03F8
USER VECTORS
EPROM
8 BYTES
$03FF
Port A Data Register
Port B Data Register
Unused
Unused
Port A Data Direction Register
Port B Data Direction Register
Unused
Unused
Timer Status and Control Register
Timer Counter Register
IRQ Status and Control Register
Unused
Unused
Unused
PEPROM Bit Select Register
PEPROM Status and Control Register
Pulldown Register A
Pulldown Register B
Unused
Unused
Unused
Unused
Unused
Mask Option Register
EPROM Programming Register
Unused
Unused
Unused
Unused
Unused
Unused
Test
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
COP Register
$03F0
RESERVED
7 BYTES
•
•
•
Timer Interrupt Vector (MSB)
Timer Interrupt Vector (LSB)
External Interrupt Vector (MSB)
External IInterrupt Vector (LSB)
Software Interrupt Vector (MSB)
Software Interrupt Vector (LSB)
Reset Vector (MSB)
Reset Vector (LSB)
$03F8
$03F9
$03FA
$03FB
$03FC
$03FD
$03FE
$03FF
Figure 5. MC68HC705K1 Memory and Register Map
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Application Note
$0000
I/O REGISTERS
32 BYTES
$001F
$0020
UNUSED
160 BYTES
$00BF
$00C0
SRAM
64 BYTES
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STACK
SRAM
64 BYTES
$00FF
$0100
UNUSED
512 BYTES
$02FF
$0300
USER EPROM
1232 BYTES
$07CF
$07D0
UNUSED
30 BYTES
$07ED
$07EE
$07EF
$07F0
TEST ROM
2 BYTES
REGISTERS & VECTORS
(EPROM)
16 BYTES
$07FF
Port A Data Register
Port B Data Register
Unused
Unused
Port A Data Direction Register
Port B Data Direction Register
Unused
Unused
Timer Status and Control Register
Timer Counter Register
IRQ Status and Control Register
Unused
Unused
Unused
Unused
Unused
Pulldown Register A
Pulldown Register B
Unused
Unused
Unused
Unused
Unused
Unused
EPROM Programming Register
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
COP Register
Mask Option Register
RESERVED
6 BYTES
$07F0
$07F1
•
•
•
Timer Interrupt Vector (MSB)
Timer Interrupt Vector (LSB)
External Interrupt Vector (MSB)
External IInterrupt Vector (LSB)
Software Interrupt Vector (MSB)
Software Interrupt Vector (LSB)
Reset Vector (MSB)
Reset Vector (LSB)
$07F8
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
Figure 6. MC68HC705KJ1 Memory and Register Map
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Application Note
Migrating to the MC68HC705KJ1
Ports
The KJ1 I/O pins have expanded high current capabilities that allow
them to source or sink current to a device. Depending on the current
requirements, these pins can be used to switch power to other parts of
the system, light LEDs, or switch opto-coupled triacs without external
transistors. Table 1 shows the maximum ratings for the I/O pins.
Table 1. KJ1 I/O Maximum Current Ratings
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Characteristic
Symbol
High source current
PA7–PA4 pins
PA3–PA0 pins
PB3–PB2 pins
IOH
High sink current
PA7–PA0 pins
PB3–PB2 pins
IOL
Max
2.5
5.5
5.5
10
10
Unit
mA
mA
Consult the KJ1 databook for high-side and low-side driver
characteristics and graphs.
Port A
No changes needed on port A.
Port B
The KJ1 has two bits of the port B register bonded out. These are bits 2
and 3. Change your code by mapping the K1’s port B pins to the KJ1’s
port B pins. This mapping also applies to the port B data direction
register and the port B pulldown register.
K1 PB0 maps to KJ1 PB2.
K1 PB1 maps to KJ1 PB3.
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Application Note
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
PB3
PB2
See
Note
See
Note
Write:
Reset:
Unaffected by reset
= Unimplemented
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PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7. Port B Data Register (PORTB)
$0005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
DDRB3
DDRB2
See
Note
See
Note
0
0
0
0
0
0
Write:
Reset:
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 8. Port B Data Direction Register (DDRB)
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See
Note
See
Note
PDIB3
PDIB2
See
Note
See
Note
0
0
0
0
0
0
Write:
Reset:
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 9. Pulldown Register B (PDRB)
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Application Note
Migrating to the MC68HC705KJ1
Clock
The KJ1 has different clock circuitry than the K1. The main difference is
the RC clock option. The available clocking options on the KJ1 are listed
in Table 2.
Table 2. KJ1 Clock Options
Clock Option
Comments
Part Number
Internal feedback resistor
con gured in MOR
MC68HC705KJ1
Do not use internal
feedback resistor
MC68HLC705KJ1
Internal feedback resistor
con gured in MOR
MC68HC705KJ1
RC oscillator
Uses either external or
internal resistor
MC68HRC705KJ1
External clock
Direct connection of clock
source
MC68HC705KJ1
Crystal oscillator
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Crystal oscillator (32 kHz)
Ceramic resonator
If you are using a crystal or ceramic resonator and want to use the
internal feedback resistor, the OSCRES bit in the mask option register
(MOR) must be set to 1. This enables the 2-MΩ feedback resistor. The
KJ1 has the option of using a 32-kHz crystal. Consult the KJ1 databook
about how to connect a 32-kHz crystal to the KJ1 properly.
The RC option on the KJ1 is quite different from the K1. The RC
oscillator has two options:
•
For more accurate clocks, use an external resistor between the
OSC1 and OSC2 pins. Do not turn on the internal feedback
resistor. Make sure the OSCRES bit in the MOR is 0.
•
For maximum cost reduction, the RC oscillator can utilize the
internal resistor and allow the chip to be driven with no external
components. This is also the least accurate way to clock the chip.
To use this option, make sure that the OSCRES bit in the MOR
is 1.
Like the K1, the KJ1 can be driven by an external clocking source also.
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Application Note
For applications that demand more performance, the KJ1 maximum
internal clock frequency is 4 MHz. The K1 maximum internal clock
frequency is 2 MHz.
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Reset and LVR
Circuitry
The reset function on the KJ1 has additional features:
•
The RESET pin contains a steering diode to discharge any voltage
on the pin to VDD when the power is removed.
•
The RESET pin contains an internal pullup resistor to VDD to allow
the RESET pin to be left unconnected for low-power applications.
•
The KJ1 has all of the K1 reset sources except a low-voltage reset
(LVR). These are:
– Power-on reset
– Logic 0 on the RESET pin
– Computer operating properly (COP)
– Illegal address
The KJ1 does not have an internal LVR. If your K1 design used the LVR,
external LVR circuitry must be added to replace this function.
Interrupts
Like the K1, the KJ1 has the same interrupt sources and functionality.
These are:
•
Software interrupt
•
Logic 0 applied to the IRQ/VPP pin
•
Logic 1 applied to one of the PA3–PA0 pins
•
A timer overflow interrupt
•
A real-time interrupt
The port A interrupt option on the K1 is programmed by writing to the
PIRQ bit (bit 2) of the MOR at location $17. On the KJ1, write to the PIRQ
bit (bit 2) of the MOR at location $7F1.
The external interrupt sensitivity on the K1 is programmed by writing to
the LEVEL bit (bit 1) of the MOR at location $17. On the KJ1, write to the
LEVEL bit (bit 1) of the MOR at location $7F1.
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Application Note
Migrating to the MC68HC705KJ1
Timer
The timer on the KJ1 is identical to the K1. No changes are needed in
software or hardware.
COP
The COP on the K1 is enabled by programming the COPEN bit (bit 0) of
the MOR at location $17 to a 1. On the KJ1, program the COPEN bit (bit
0) of the MOR at location $7F1 to a 1.
The K1 COP timer is cleared by writing a 0 to bit 0 of the COPR
(computer operating properly register) at location $3F0. On the KJ1,
clear the COP by writing a 0 to bit 0 of the COPR located at $7F0.
Just like the K1, the KJ1 COP timeout is set by the RT1 and RT0 bits of
the timer status and control register. No code changes are needed.
Personality EPROM
The K1 provides the user with 64 bits of personality EPROM. The KJ1
does not have a personality EPROM array. Consequently, the
personality EPROM bit select register and the personality EPROM
status and control register are not found on the KJ1.
To provide this functionality within the KJ1, utilize some of the extra
EPROM on the KJ1 to create eight bytes or 64 bits of personality
EPROM. This EPROM memory cannot be programmed by the user’s
code. It can be programmed only at the time the entire EPROM array is
being programmed for production.
The KJ1 gives the designer additional options in the MOR. Table 3
compares the two MOR registers.
MOR
Table 3. MOR Comparison
Part
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
K1
SWPDI
PIN3
RC
SWAIT
LVRE
PIRQ
LEVEL
COPEN
KJ1
SOSCD
EPMSEC
OSCRES
SWAIT
SWPDI
PIRQ
LEVEL
COPEN
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Application Note
SWPDI
The software pulldown inhibit bit has the same functionality on both parts
but is found at bit 3 of the KJ1 MOR.
PIN3
Since the KJ1 does not have a 3-pin oscillator option, this option is not
found on the KJ1 MOR.
RC
The RC option on the K1 was used to distinguish between using an
external RC network or an external crystal, ceramic resonator, or clock
source. The KJ1 configures its oscillator with the OSCRES bit.
SWAIT
The STOP conversion to wait bit has the same functionality on both
parts.
LVRE
The KJ1 does not have a low-voltage reset function. This option is not
found in the KJ1 MOR.
PIRQ
The port A IRQ enable bit has the same functionality on both parts.
LEVEL
The external interrupt sensitivity bit has the same functionality on both
parts.
COPEN
The COP enable bit has the same functionality on both parts.
SOSCD
The short oscillator delay bit controls the oscillator stabilization counter.
The normal stabilization delay following reset or exit from stop mode is
4064 bus cycles. Setting the SOSCD enables a 128-bus cycle
stabilization delay. If your oscillator design has a quick startup time, the
SOSCD bit will allow quicker recovery from oscillator startup. Setting the
bit to a 1 enables the short oscillator delay.
EPMSEC
To protect your software investment, the KJ1 provides the designer the
added functionality of securing the EPROM array. When this bit is set,
external access of the EPROM array is denied.
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Application Note
Ordering Information
The OSCRES bit enables the 2-MΩ internal resistor in the oscillator
circuit. When this bit is set to 1, the internal resistor is enabled.
OSCRES
NOTE:
Program the OSCRES bit to logic 0 in devices using low-speed crystal
oscillators or RC oscillators with external resistors.
Ordering Information
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Table 4 lists the MC order numbers for the KJ1. All parts are specified
to run at –40 to +85 °C temperature.
Table 4. Ordering Information
Package Type
Oscillator Type
Order Number
Plastic DIP
XTAL
MC68HC705KJ1CP
SOIC
XTAL
MC68HC705KJ1CDW
CERDIP
XTAL
MC68HC705KJ1CS
Plastic DIP
RC
MC68HRC705KJ1CP
SOIC
RC
MC68HRC705KJ1CDW
CERDIP
RC
MC68HRC705KJ1CS
Plastic DIP
32-kHz XTAL
MC68HLC705KJ1CP
SOIC
32-kHz XTAL
MC68HLC705KJ1CDW
CERDIP
32-kHz XTAL
MC68HLC705KJ1CS
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Application Note
References/Additional Reading
MC68HC705K1 Technical Data, (MC68HC705K1/D),.
MC68HC705KJ1 Technical Data, (MC68HC705KJ1/D),
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directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
For More Information On This Product,
Go to: www.freescale.com
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