Fujitsu MB90F574PFV 16-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13701-7E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90570 Series
MB90573/574/574C/F574/F574A/V570/V570A
■ DESCRIPTION
The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real time processing. It contains an I2C*2 bus
interface that allows inter-equipment communication to be implemented readily. This product is well adapted to
car audio equipment, VTR systems, and other equipment and systems.
The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and
enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word
data.
The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI),
an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit
free run timer, an input capture (ICU), an output compare (OCU)).
*1: F2MC stands for FUJITSU Flexible Microcontroller.
*2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■ PACKAGE
120-pin plastic LQFP
(
)
(FPT-120P-M05)
120-pin plastic QFP
120-pin plastic LQFP
(FPT-120P-M13)
(FPT-120P-M21)
MB90570 Series
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4× PLL clock, operation at VCC of 5.0 V)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 16 channels
• Embedded ROM size and types
Mask ROM: 128 kbytes/256 kbytes
Flash ROM: 256 kbytes
Embedded RAM size: 6 kbytes/10 kbytes (mask ROM)
10 kbytes (flash memory)
10 kbytes (evaluation device)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
• Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 63 ports
General-purpose I/O ports (with pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 10 ports
Total: 97 ports
(Continued)
2
MB90570 Series
(Continued)
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)
• 16-bit I/O timer
16-bit free run timer: 1 channel
Input capture (ICU): Generates an interrupt request by latching a 16-bit free run timer counter value upon
detection of an edge input to the pin.
Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match
between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
• I2C interface (1 channel)
Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution
Starting by an external trigger input.
Conversion time: 26.3 µs
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• Chip select output (8 channels)
An active level can be set.
• Clock output function
3
MB90570 Series
■ PRODUCT LINEUP
Part number
MB90573
Item
Classification
MB90574/C
Mask ROM products
ROM size
128 kbytes
RAM size
6 kbytes
MB90F574/A
MB90V570/A
Flash ROM products Evaluation product
256 kbytes
None
10 kbytes
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)
CPU functions
General-purpose I/O ports (CMOS output): 63
General-purpose I/O ports (with pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 10
Total: 97
Ports
UART0 (SCI), UART1 (SCI)
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
8/10-bit A/D converter
Resolution: 8/10-bit
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
program up to 8 channels.)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 1 (or 8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)
8/16-bit up/down counter/
timer
16-bit
free run timer
16-bit
I/O timer
Output
compare
(OCU)
Input capture
(ICU)
Number of channels: 1 (or 8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
Number of channel: 1
Overflow interrupts
Number of channels: 4
Pin input factor: A match signal of compare register
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
MB90570 Series
(Continued)
Part number
MB90573
MB90574/C
MB90F574/A
MB90V570/A
Item
DTP/external interrupt circuit
Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Delayed interrupt generation
module
An interrupt generation module for switching tasks used in real time operating
systems.
Extended I/O serial interface
Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
Serial I/O port for supporting Inter IC BUS
I2C interface
Timebase timer
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
8-bit D/A converter
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(standby) mode
Sleep/stop/CPU intermittent operation/clock timer/hardware standby
Process
CMOS
Power supply voltage for
operation*
4.5 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0 to +25°C, and an operating frequency of 1 MHz to 16 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90573
MB90574
MB90F574/A
MB90574C
×
FPT-120P-M05
FPT-120P-M13
FPT-120P-M21
×
×
: Available ×: Not available
Note: For more information about each package, see section “■ Package Dimensions.”
5
MB90570 Series
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V570/A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and
FF0000H to FF3FFFH to bank FF only.
• The products designated with /A or /C are different from those without /A or /C in that they are DTP/externallyinterrupted types which return from standby mode at the ch.0 to ch.1 edge request.
6
MB90570 Series
■ PIN ASSIGNMENT
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P30/ALE
VSS
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
(Top view)
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
HST
PC3
PC2
PC1
PC0
PB7
PB6/ADTG
PB5/IRQ5
PB4/IRQ4
PB3/IRQ3
PB2/IRQ2
PB1/IRQ1
X0A
X1A
PB0/IRQ0
PA7/SCL
PA6/SDA
PA5/ZIN1
PA4/BIN1
PA3/AIN1/IRQ7
PA2/ZIN0
PA1/BIN0
PA0/AIN0/IRQ6
VSS
P97/CS7
P96/CS6
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P66/OUT2
P67/OUT3
VSS
C
P70
P71
P72
DVCC
DVSS
P73/DA0
P74/DA1
AVCC
AVRH
AVRL
AVSS
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
VCC
P90/CS0
P91/CS1
P92/CS2
P93/CS3
P94/CS4
P95/CS5
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
VCC
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1
P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3
P56/IN0
P57/IN1
P60/SIN4
P61/SOT4
P62/SCK4
P63/CKOT
P64/OUT0
P65/OUT1
(FPT-120P-M05)
(FPT-120P-M13)
(FPT-120P-M21)
7
MB90570 Series
■ PIN DESCRIPTION
Pin no.
LQFP-120 *1
QFP-120 *2
Pin name
Circuit type
92,93
X0,X1
A
High speed oscillator input pins
74,73
X0A,X1A
B
Low speed oscillator input pins
MD0 to MD2
C
These are input pins used to designate the operating mode. They should
be connected directly to Vcc or Vss.
90
RST
C
Reset input pin
86
HST
C
Hardware standby input pin
P00 to P07
D
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR0).
When set for output, this setting will be invalid.
89 to 87
95 to 102
AD00 to AD07
103 to 110
P10 to P17
In external bus mode, these pins function as address low output/data low
I/O pins.
D
AD08 to AD15
111 to 118
P20 to P27
120
P30
E
P31
E
P32
E
P33
E
P34
E
P35
E
P36
RDY
*1: FPT-120P-M05
*2: FPT-120P-M13,FPT-120P-M21
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold request signal input
pin.
E
HAK
6
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus upper 8-bit write
strobe signal output pin.
HRQ
5
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the data bus lower 8-bit write
strobe signal output pin.
WRH
4
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the read strobe signal output
pin.
WRL
3
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the address latch enable signal
output pin.
RD
2
In single chip mode this is a general-purpose I/O port.
In external bus mode, these pins function as address high output pins.
ALE
1
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register (RDR1).
When set for output, the setting will be invalid.
In external bus mode, these pins function as address middle output/data
high I/O pins.
A16 to A23
8
Function
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the hold acknowledge signal
output pin.
E
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the ready signal input pin.
(Continued)
MB90570 Series
Pin no.
LQFP-120 *1
QFP-120 *2
7
Pin name
Circuit type
P37
E
CLK
9
P40
P41
F
P42
F
P43
F
P44
F
P45
F
P46,P47
F
P50
SIN2
*1: FPT-120P-M05
*2: FPT-120P-M13,FPT-120P-M21
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid when
UART ch.1 is enabled for clock output.
F
PPG0,PPG1
17
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
SCK1
15,16
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
SOT1
14
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid when
UART ch.0 is enabled for clock output.
SIN1
13
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
SCK0
12
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
SOT0
11
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the clock (CLK) signal output
pin.
SIN0
10
Function
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
These are also the PPG0, 1 output pins. This function is valid when PPG0,
1 output is enabled.
E
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.
(Continued)
9
MB90570 Series
Pin no.
LQFP-120 *1
QFP-120 *2
18
Pin name
Circuit type
P51
E
SOT2
19
P52
P53
E
P54
E
P55
E
P56,P57
E
P60
E
P61
F
P62
F
P63
CKOT
*1: FPT-120P-M05
*2: FPT-120P-M13,FPT-120P-M21
10
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 data output pin. This function is valid when
serial ch.2 is enabled for serial data output.
F
SCK4
28
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 data input pin. During serial data input this
function is in continuous use, and therefore the output function should
only be used when needed.
SOT4
27
In single chip mode this is a general-purpose I/O port.
These are also the input capture ch.0/1 trigger input pins. During input
capture signal input on ch.0/1 this function is in continuous use, and
therefore the output function should only be used when needed.
SIN4
26
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 clock I/O pin. This function is valid when
serial ch.1 is enabled for serial data output.
IN0,IN1
25
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data output pin. This function is valid when
serial ch.1 is enabled for serial data output.
SCK3
23,24
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.
SOT3
22
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 clock I/O pin. This function is valid when
serial ch.0 is enabled for serial data output.
SIN3
21
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data output pin. This function is valid when
serial ch.0 is enabled for serial data output.
SCK2
20
Function
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the I/O serial ch.2 serial clock I/O pin. This function is valid
when serial ch.2 is enabled for serial data output.
F
In single chip mode this is a general-purpose I/O port. When set for input
it can be set by the pull-up resistance register (RDR6). When set for
output this setting will be invalid.
This is also the clock monitor output pin. This function is valid when clock
monitor output is enabled.
(Continued)
MB90570 Series
Pin no.
Pin name
LQFP-120 *1
QFP-120 *2
29 to 32
Circuit type
Function
F
In single chip mode these are general-purpose I/O ports. When set for
input they can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
P64 to P67
OUT0 to
OUT3
35 to 37
40,41
These are also the output compare ch.0 to ch.3 event output pins. This
function is valid when the respective channel(s) are enabled for output.
P70 to P72
E
These are general purpose I/O ports.
P73,P74
I
These are general purpose I/O ports.
DA0,DA1
46 to 53
P80 to P87
These are also the D/A converter ch.0,1 analog signal output pins.
K
AN0 to AN7
55 to 62
P90 to P97
These are general purpose I/O ports.
These are also A/D converter analog input pins. This function is valid
when analog input is enabled.
E
CS0 to CS7
These are general purpose I/O ports.
These are also chip select signal output pins. This function is valid when
chip select signal output is enabled.
34
C
G
This is the power supply stabilization capacitor pin. It should be
connected externally to an 0.1 µF ceramic capacitor. Note that this is
not required on the FLASH model (MB90F574/A) and MB90574C.
64
PA0
E
This is a general purpose I/O port.
65
AIN0
This pin is also used as count clock A input for 8/16-bit up-down counter
ch.0.
IRQ6
This pin can also be used as interrupt request input ch. 6.
PA1
E
BIN0
66
PA2
This pin is also used as count clock B input for 8/16-bit up-down counter
ch.0.
E
ZIN0
67
68
PA3
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.0.
E
This is a general purpose I/O port.
AIN1
This pin is also used as count clock A input for 8/16-bit up-down counter
ch.1.
IRQ7
This pin can also be used as interrupt request input ch.7.
PA4
E
BIN1
69
This is a general purpose I/O port.
PA5
ZIN1
*1: FPT-120P-M05
*2: FPT-120P-M13,FPT-120P-M21
This is a general purpose I/O port.
This pin is also used as count clock B input for 8/16-bit up-down counter
ch.1.
E
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down counter
ch.1.
(Continued)
11
MB90570 Series
(Continued)
Pin no.
LQFP-120 *1
QFP-120 *2
70
Pin name
Circuit type
PA6
L
SDA
71
PA7
PB0,
PB1 to PB5
L
PB6
E
E
This is a general purpose I/O port.
This is also the A/D converter external trigger input pin. While the A/D
converter is in input operation, this input signal is in continuous use, and
therefore the output function should only be used when needed.
PB7
E
This is a general purpose I/O port.
82 to 85
PC0 to PC3
E
These are general purpose I/O ports.
8,54,94
VCC
Power
supply
These are power supply (5V) input pins.
33,63,
91,119
VSS
Power
supply
These are power supply (0V) input pins.
42
AVCC
H
This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.
43
AVRH
J
This is the A/D converter Vref+ input pin. The input voltage should not
exceed Vcc.
44
AVRL
H
This is the A/D converter Vref-input pin. The input voltage should not
less than Vss.
45
AVSS
H
This is the analog macro (D/A, A/D etc.) Vss power supply input pin.
38
DVCC
H
This is the D/A converter Vref input pin. The input voltage should not
exceed Vcc.
39
DVSS
H
This is the D/A converter GND power supply pin. It should be set to Vss
equivalent potential.
*1: FPT-120P-M05
*2: FPT-120P-M13,FPT-120P-M21
12
These are general-purpose I/O ports.
These pins are also the external interrupt input pins. IRQ0, 1 are
enabled for both rising and falling edge detection, and therefore cannot
be used for recovery from STOP status for MB90V570, MB90F574,
MB90573 and MB90574. However, IRQ0, 1 can be used for recovery
from STOP status for MB90V570A, MB90F574A and MB90574C.
ADTG
81
This is a general purpose I/O port.
This pin is also used as the clock I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While the
I2C interface is operating, this port should be set to the input level
(DDRA: bit7 = 0).
IRQ0,
IRQ1 to IRQ5
80
This is a general purpose I/O port.
This pin is also used as the data I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While the
I2C interface is operating, this port should be set to the input level
(DDRA: bit6 = 0).
SCL
72,
75 to 79
Function
MB90570 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillator circuit
Oscillator recovery resistance for high
speed = approx. 1 MΩ
X1
X0
Standby control signal
B
• Oscillator circuit
Oscillator recovery resistance for low
speed = approx. 1 MΩ
X1A
X0A
Standby control signal
C
• Hysteresis input pin
Resistance value = approx. 50 kΩ (typ.)
R
Hysteresis input
D
VCC
VCC
P-ch
Selective signal either
with a pull-up resistor or
without it.
P-ch
N-ch
R
Hysteresis input
• CMOS hysteresis input pin with input pullup control
• CMOS level output.
• CMOS hysteresis input
(Includes input shut down standby control
function)
• Pull-up resistance value =
approx. 50 kΩ(typ.)
IOL = 4mA
Standby control for input interruption
IOL = 4 mA
(Continued)
13
MB90570 Series
Type
Circuit
Remarks
E
• CMOS hysteresis input/output pin.
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby control
function)
IOL = 4 mA
VCC
P-ch
N-ch
R
Hysteresis input
Standby control for input interruption
IOL = 4 mA
F
• CMOS hysteresis input/output pin.
• CMOS level output
• CMOS hysteresis input
(Includes input shut down standby control
function)
IOL = 10 mA (Large current port)
VCC
P-ch
N-ch
R
IOL = 10 mA
G
Hysteresis input
Standby control for input interruption
• C pin output
(capacitance connector pin).
VCC
On the MB90F574 this pin is not
connected (NC).
P-ch
N-ch
H
• Analog power supply protector
circuit.
VCC
P-ch
AVP
N-ch
I
VCC
P-ch
N-ch
R
Hysteresis input
• CMOS hysteresis input/output
• Analog output/CMOS output
dual-function pin (CMOS output is not
available during analog output.)
(Analog output priority: DAE = 1)
• Includes input shout down standby
control function.
IOL = 4mA
Standby control for input interruption
DAO
IOL = 4 mA
(Continued)
14
MB90570 Series
Type
Circuit
Remarks
J
• A/D converter ref+ power supply input
pin(AVRH), with power supply
protector circuit.
VCC
P-ch
P-ch
N-ch
ANE
AVR
N-ch
K
ANE
• CMOS hysteresis input /analog input
dual-function pin.
• CMOS output
• Includes input shut down function at input
shut down standby.
VCC
P-ch
N-ch
R
Hysteresis input
Standby control for input interruption
Analog input
IOL = 4 mA
L
• Hysteresis input
• N-ch open-drain output
• Includes input shut down standby control
function.
IOL= 4mA
VCC
N-ch
N-ch
R
Hysteresis input
IOL = 4 mA
Standby control for input interruption
15
MB90570 Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC)and
analog input voltages not exceed the digital voltage (VCC).
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be
more than 2 k<Symbol>W.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
MB90570 series
X0
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise
in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
16
MB90570 Series
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
• Using power supply pins
VCC
VSS
VCC
VSS
VSS
MB90570 series
VCC
VCC
VSS
VSS
VCC
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL,
DVCC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9. N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)
17
MB90570 Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs
should not become indeterminate. (MB90F574,MB90F574A,MB90574C)
Timing chart of indeterminate outputs from ports 0 and 1
Oscillation setting time *2
Step-down circuit setting time *1
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Period of indeterminate
*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time
218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again
to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal
state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
18
MB90570 Series
■ BLOCK DIAGRAM
Interrupt controller
F2MC–16LX
CPU
3
Port 7
X0, X1
X0A, X1A
Main clock
2
RST
P73/DA0
P74/DA1
8-bit
D/A
converter
× 2 ch.
Clock control
block
(including timebase
timer)
Sub clock
DVCC
DVSS
HST
P00/AD00 to P07/AD07
P10/AD08 to P17/AD15
P20/A16 to P27/A23
8
8
Port 0, 1, 2
P70 to P72
Port 9
16
8
Chip select
output
8
P30/ALE
8
8
P90/CS0 to P97/CS7
Port A
P31/RD
2
P32/WRL
P33/WRH
P34/HRQ
6
PA1/BIN0
External bus
interface
PA2/ZIN0
P35/HAK
P36/RDY
P37/CLK
Port 3
P40/SIN0
Port 4
P41/SOT0
2
P42/SCK0
P43/SIN1
2
P44/SOT1
2
UART0
(SCI),
UART1
(SCI)
Internal data bus
8/16-bit up/down
counter/timer
PA3/AIN1/IRQ7
6
PA4/BIN1
PA5/ZIN1
I2C bus
2
PA6/SDA
PA7/SCL
DTP/
external
interrupt
circuit
× 8 ch.
PA0/AIN0/IRQ6
6
6
PB0/IRQ0 to
PB5/IRQ5
P45/SCK1
P46/PPG0
8/16-bit
PPG timer
ch.0
P47/PPG1
P50/SIN2
Port 5
P51/SOT2
P52/SCK2
2
P53/SIN3
2
P54/SOT3
2
8/10-bit
A/D converter
× 8 ch.
8
8
AVRL
AVRH
AVCC
AVSS
P80/AN0 to
P87/AN7
Port 8
2
P57/IN1
PB6/ADTG
SIO × 2 ch
P55/SCK3
P56/IN0
PB7
Port B
Input capture
(ICU)
Port C
4
PC0 to PC3
16-bit free run timer
P64/OUT0 to P67/OUT3
4
4
Output
compare
(OCU)
P60/SIN4
P61/SOT4
SIO × 1 ch.
RAM
ROM
P62/SCK4
Port 6
P63/CKOT
Other pins
MD0 to MD2,
C, VCC, VSS
Clock output
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor
P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
P40 to P47 (8 ports): Heavy-current (IOL = 10 mA) port
P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
19
MB90570 Series
■ MEMORY MAP
Single chip mode
A mirror function is
supported.
Internal ROM
external bus mode
A mirror function
is supported.
External ROM
external bus mode
FFFFFFH
ROM area
ROM area
ROM area
(image of
Address #2 bank FF)
ROM area
(image of
bank FF)
Address #1
FC0000H
010000H
004000H
Address #3
RAM Register
RAM Register
RAM Register
Peripheral
Peripheral
Peripheral
000100H
0000C0H
000000H
Address #1*
Address #2 *
Address #3 *
MB90573
Part number
FE0000H
004000H
001800H
MB90574/C
FC0000H
004000H
002900H
MB90F574/A
FC0000H
004000H
002900H
: Internal access memory
: External access memory
: Inhibited area
*: Addresses #1, #2 and #3 are unique to the product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,
enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are
accessed actually. Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected
in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image
for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H
to FFFFFFH.
20
MB90570 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
: Accumulator (A)
Dual 16-bit register used for storing results of calculation etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
USP
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
SSP
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
PS
: Processor status (PS)
The 16-bit register indicating the system status.
PC
: Program counter (PC)
The 16-bit register indicating storing location of the current instruction code.
DPR
: Direct page register (DPR)
The 8-bit register indicating bit 8 through 15 of the operand address in the short
direct addressing mode.
PCB
: Program bank register (PCB)
The 8-bit register indicating the program space.
DTB
: Data bank register (DTB)
The 8-bit register indicating the data space.
USB
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
SSB
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
ADB
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
8-bit
16-bit
32-bit
21
MB90570 Series
• General-purpose registers
Maximum of 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + (RP × 10H)
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
PS
Initial value
— : Reserved
X : Undefined
22
ILM2 ILM1 ILM0
0
0
0
bit 5 bit 4
bit 3 bit 2
bit 1
bit 0
B4
B3
B2
B1
B0
—
I
S
T
N
Z
V
C
0
0
0
0
0
—
0
1
X
X
X
X
X
MB90570 Series
■ I/O MAP
Address
Abbreviated
register
name
000000H
PDR0
000001H
Read/
write
Resource name
Initial value
Port 0 data register
R/W
Port 0
XXXXXXXXB
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
Port 8
XXXXXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9
XXXXXXXXB
00000AH
PDRA
Port A data register
R/W
Port A
XXXXXXXXB
00000BH
PDRB
Port B data register
R/W
Port B
XXXXXXXXB
00000CH
PDRC
Port C data register
R/W
Port C
XXXXXXXXB
Register name
00000DH
to
00000FH
(Disabled)
000010H
DDR0
Port 0 direction register
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
Port 4
00000000B
000015H
DDR5
Port 5 direction register
R/W
Port 5
00000000B
000016H
DDR6
Port 6 direction register
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
Port 7
–––00000B
000018H
DDR8
Port 8 direction register
R/W
Port 8
00000000B
000019H
DDR9
Port 9 direction register
R/W
Port 9
00000000B
00001AH
DDRA
Port A direction register
R/W
Port A
00000000B
00001BH
DDRB
Port B direction register
R/W
Port B
00000000B
00001CH
DDRC
Port C direction register
R/W
Port C
00000000B
00001DH
ODR4
Port 4 output pin register
R/W
Port 4
00000000B
00001EH
ADER
Analog input enable register
R/W
Port 8,
8/10-bit
A/D converter
11111111B
00001FH
(Disabled)
000020H
SMR0
Serial mode register 0
R/W
000021H
SCR0
Serial control register 0
R/W
UART0
(SCI)
00000000B
00000100B
(Continued)
23
MB90570 Series
Address
Abbreviated
register
name
000022H
SIDR0/
SODR0
000023H
Read/
write
Resource
name
Initial value
Serial input data register 0/
serial output data register 0
R/W
XXXXXXXXB
SSR0
Serial status register 0
R/W
UART0
(SCI)
000024H
SMR1
Serial mode register 1
R/W
000025H
SCR1
Serial control register 1
R/W
000026H
SIDR1/
SODR1
Serial input data register 1/
serial output data register 1
R/W
000027H
SSR1
Serial status register 1
R/W
000028H
CDCR0
Register name
Communications prescaler control
register 0
000029H
00002AH
000031H
000032H
000033H
00000000B
UART1
(SCI)
00000100B
XXXXXXXXB
00001–00B
R/W
Communications
prescaler
register 0
0–––1111B
R/W
Communications
prescaler
register 0
0–––1111B
(Disabled)
CDCR1
Communications prescaler control
register 1
00002BH
to
00002FH
000030H
00001–00B
(Disabled)
ENIR
DTP/interrupt enable register
R/W
EIRR
DTP/interrupt factor register
R/W
ELVR
Request level setting register
R/W
000034H
00000000B
DTP/external
interrupt circuit
XXXXXXXXB
00000000B
00000000B
(Disabled)
000035H
000036H
ADCS1
A/D control status register lower
digits
R/W
000037H
ADCS2
A/D control status register upper
digits
R/W or W
000038H
ADCR1
A/D data register lower digits
R
XXXXXXXXB
000039H
ADCR2
A/D data register upper digits
W
0 0 0 0 1 – XXB
00003AH
DADR0
D/A converter data register ch.0
R/W
XXXXXXXXB
00003BH
DADR1
D/A converter data register ch.1
R/W
00003CH
DACR0
D/A control register 0
R/W
00003DH
DACR1
D/A control register 1
R/W
00003EH
CLKR
Clock output enable register
R/W
00003FH
00000000B
8/10-bit A/D
converter
8-bit D/A
converter
00000000B
XXXXXXXXB
–––––––0B
–––––––0B
Clock monitor
function
––––0000B
(Disabled)
000040H
PRLL0
PPG0 reload register L ch.0
R/W
000041H
PRLH0
PPG0 reload register H ch.0
R/W
8/16-bit PPG
timer 0
XXXXXXXXB
XXXXXXXXB
(Continued)
24
MB90570 Series
Address
Abbreviated
register
name
000042H
PRLL1
000043H
Read/
write
Resource name
Initial value
PPG1 reload register L ch.1
R/W
XXXXXXXXB
PRLH1
PPG1 reload register H ch.1
R/W
8/16-bit PPG
timer 1
000044H
PPGC0
PPG0 operating mode control
register ch.0
R/W
8/16-bit PPG
timer 0
0 X 0 0 0 XX 1 B
000045H
PPGC1
PPG1 operating mode control
register ch.1
R/W
8/16-bit PPG
timer 1
0X000001B
000046H
PPGOE
PPG0 and 1 output control registers
ch.0 and ch.1
R/W
8/16-bit PPG
timer 0, 1
0 0 0 0 0 0XXB
Register name
000047H
(Disabled)
000048H
SMCSL0
Serial mode control lower status
register 0
R/W
000049H
SMCSH0
Serial mode control upper status
register 0
R/W
00004AH
SDR0
Serial data register 0
R/W
00004BH
SMCSL1
Serial mode control lower status
register 1
R/W
00004DH
SMCSH1
Serial mode control upper status
register 1
R/W
00004EH
SDR1
Serial data register 1
R/W
00004FH
000051H
000052H
000053H
000054H
000057H
000058H
IPCP0
ICU data register ch.0
IPCP1
ICU data register ch.1
ICS01
ICU control status register
00005BH
00005CH
00005DH
00005EH
00005FH
00000010B
XXXXXXXXB
––––0000B
Extended I/O
serial interface 1
00000010B
XXXXXXXXB
XXXXXXXXB
R
R
16-bit I/O timer
(input capture
(ICU) section)
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
(Disabled)
TCDT
Free run timer data register
R/W
TCCS
Free run timer control status register
R/W
000059H
00005AH
Extended I/O
serial interface 0
(Disabled)
000055H
000056H
––––0000B
(Disabled)
00004CH
000050H
XXXXXXXX B
16-bit I/O timer
(16-bit free run
timer section)
00000000B
00000000B
00000000B
(Disabled)
OCCP0
OCU compare register ch.0
XXXXXXXXB
R/W
OCCP1
OCU compare register ch.1
R/W
OCCP2
OCU compare register ch.2
R/W
XXXXXXXXB
16-bit I/O timer
(output compare
(OCU) section)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
25
MB90570 Series
Address
000060H
000061H
Abbreviated
register
name
OCCP3
Read/
write
Register name
OCU compare register ch.3
R/W
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
16-bit I/O timer
(output compare
(OCU) section)
000062H
OCS0
OCU control status register ch.0
R/W
000063H
OCS1
OCU control status register ch.1
R/W
000064H
OCS2
OCU control status register ch.2
R/W
0000––00B
000065H
OCS3
OCU control status register ch.3
R/W
–––00000B
000066H
0000––00B
–––00000B
(Disabled)
000067H
000068H
IBSR
I2C bus status register
R
00000000B
000069H
IBCR
I2C bus control register
R/W
00000000B
00006AH
ICCR
I2C bus clock control register
R/W
00006BH
IADR
00006CH
IDAR
R/W
– XXXXXXXB
2
R/W
XXXXXXXXB
I C bus address register
I C bus data register
(Disabled)
00006EH
00006FH
ROMM
ROM mirroring function selection
register
W
000070H
UDCR0
Up/down count register 0
R
000071H
UDCR1
Up/down count register 1
R
000072H
RCR0
Reload compare register 0
W
000073H
RCR1
Reload compare register 1
W
000074H
CSR0
Counter status register 0
000075H
CCRL0
CCRH0
000078H
CSR1
ROM mirroring
function
selection module
00000000B
8/16-bit up/down
counter/timer
00000000B
00000000B
00000000B
3
Counter control register 0
R/W
Counter status register 1
R/W
000079H
–––––––1B
00000000B
R/W
(Reserved area)*
000077H
–0000000B
8/16-bit up/down
counter/timer
00000000B
00000000B
(Reserved area)*3
00007AH
CCRL1
00007BH
CCRH1
00007CH
Counter control register 1
R/W
SMCSL2
Serial mode control lower status
register 2
R/W
00007DH
SMCSH2
Serial mode control higher status
register 2
R/W
00007EH
SDR2
Serial data register 2
R/W
00007FH
– – 0 XXXXXB
2
00006DH
000076H
I2C interface
8/16-bit up/down
counter/timer
–0000000B
–0000000B
––––0000B
Extended I/O
serial interface 2
00000010B
XXXXXXXXB
(Disabled)
(Continued)
26
MB90570 Series
Address
Abbreviated
register
name
000080H
CSCR0
Chip selection control register 0
R/W
––––0000B
000081H
CSCR1
Chip selection control register 1
R/W
––––0000B
000082H
CSCR2
Chip selection control register 2
R/W
Read/
write
Register name
Resource name
Initial value
––––0000B
Chip select
output
000083H
CSCR3
Chip selection control register 3
R/W
000084H
CSCR4
Chip selection control register 4
R/W
––––0000B
000085H
CSCR5
Chip selection control register 5
R/W
––––0000B
000086H
CSCR6
Chip selection control register 6
R/W
––––0000B
000087H
to
00008BH
––––0000B
(Disabled)
00008CH
RDR0
Port 0 input pull-up resistor setup
register
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 input pull-up resistor setup
register
R/W
Port 1
00000000B
00008EH
RDR6
Port 6 input pull-up resistor setup
register
R/W
Port 6
00000000B
R/W
Address match
detection
function
00000000B
Delayed
interrupt
generation
module
–––––––0B
00008FH
to
00009DH
(Disabled)
PACSR
Program address detection control
status register
00009FH
DIRR
Delayed interrupt factor generation/
cancellation register
R/W
0000A0H
LPMCR
Low-power consumption mode
control register
R/W
0000A1H
CKSCR
Clock select register
R/W
00009EH
0000A2H
to
0000A4H
Low-power
consumption
(standby) mode
00011000B
11111100B
(Disabled)
0000A5H
ARSR
Automatic ready function select
register
W
0000A6H
HACR
Upper address control register
W
0000A7H
ECSR
Bus control signal select register
W
0000A8H
WDTC
Watchdog timer control register
R/W
Watchdog timer
XXXXXXXX B
0000A9H
TBTC
Timebase timer control register
R/W
Timebase timer
1––00100B
0000AAH
WTC
Clock timer control register
R/W
Clock timer
1X000000B
0011––00B
External bus pin
00000000B
00000000B
(Continued)
27
MB90570 Series
(Continued)
Address
Abbreviated
register
name
Read/
write
Register name
0000ABH
to
0000ADH
0000AEH
Initial value
Flash interface
0 0 0 X 0 XX 0 B
(Disabled)
FMCS
Flash control register
R/W
0000AFH
(Disabled)
0000B0H
ICR00
Interrupt control register 00
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
00000111B
0000C0H
to
0000FFH
(External area)*1
000100H
to
000###H
(RAM area)*2
000###H
to
001FEFH
(Reserved area)*3
001FF0H
001FF1H
PADR0
Program address detection register 0
R/W
Program address detection register 1
R/W
Interrupt
controller
00000111B
00000111B
XXXXXXXXB
XXXXXXXXB
Address match
detection
function
001FF2H
Program address detection register 2
R/W
001FF3H
Program address detection register 3
R/W
Program address detection register 4
R/W
XXXXXXXXB
Program address detection register 5
R/W
XXXXXXXXB
001FF4H
001FF5H
001FF6H
to
001FFFH
28
Resource name
PADR1
(Reserved area)
XXXXXXXXB
XXXXXXXXB
MB90570 Series
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
– : This bit is unused. The initial value is undefined.
*1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*2: For details of the RAM area, see “■ MEMORY MAP”.
*3: The reserved area is disabled because it is used in the system.
Notes: • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an
initial value. Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
• The addresses following 0000FFH are reserved. No external bus access signal is generated.
• Boundary ####H between the RAM area and the reserved area varies with the product model.
29
MB90570 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt vector
Interrupt control register
EI2OS
support
Number
Address
ICR
Address
Reset
×
# 08
FFFFDCH
—
—
INT9 instruction
×
# 09
FFFFD8H
—
—
Exception
×
# 10
FFFFD4H
—
—
8/10-bit A/D converter
# 11
FFFFD0H
ICR00
0000B0H
Input capture 0 (ICU) include
# 12
FFFFCCH
DTP0 (external interrupt 0)
# 13
FFFFC8H
ICR01
0000B1H
Input capture 1 (ICU) include
# 14
FFFFC4H
Output compare 0 (OCU) match
# 15
FFFFC0H
ICR02
0000B2H
Output compare 1 (OCU) match
# 16
FFFFBCH
Output compare 2 (OCU) match
# 17
FFFFB8H
ICR03
0000B3H
Output compare 3 (OCU) match
# 18
FFFFB4H
Extended I/O serial interface 0
# 19
FFFFB0H
ICR04
0000B4H
# 20
FFFFACH
# 21
FFFFA8H
ICR05
0000B5H
# 22
FFFFA4H
Extended I/O serial interface 2
# 23
FFFFA0H
ICR06
0000B6H
DTP1 (external interrupt 1)
# 24
FFFF9CH
DTP2/DTP3 (external interrupt 2/
external interrupt 3)
# 25
FFFF98H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
Interrupt source
16-bit free run timer
×
Extended I/O serial interface 1
Clock timer
8/16-bit PPG timer 0 counter
borrow
×
×
DTP4/DTP5 (external interrupt 4/
external interrupt 5)
8/16-bit PPG timer 1 counter
borrow
×
# 26
FFFF94H
# 27
FFFF90H
# 28
FFFF8CH
8/16-bit up/down counter/timer 0
borrow/overflow/inversion
# 29
FFFF88H
8/16-bit up/down counter/timer 0
compare match
# 30
FFFF84H
8/16-bit up/down counter/timer 1
borrow/overflow/inversion
# 31
FFFF80H
8/16-bit up/down counter/timer 1
compare match
# 32
FFFF7CH
DTP6 (external interrupt 6)
# 33
FFFF78H
# 34
FFFF74H
Timebase timer
Priority
High
0000BAH
ICR10
×
0000BAH
ICR11
0000BBH
Low
(Continued)
30
MB90570 Series
(Continued)
Interrupt source
EI2OS
support
DTP7 (external interrupt 7)
I2C interface
×
UART1 (SCI) reception complete
Interrupt vector
Number
Address
# 35
FFFF70H
# 36
FFFF6CH
# 37
FFFF68H
UART1 (SCI) transmission
complete
# 38
FFFF64H
UART0 (SCI) reception complete
# 39
FFFF60H
UART0 (SCI) transmission
complete
# 40
FFFF5CH
Flash memory
×
# 41
FFFF58H
Delayed interrupt generation
module
×
# 42
FFFF54H
Interrupt control register
ICR
Address
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
Priority
High
Low
: Can be used
× : Can not be used
: Can be used. With EI2OS stop function.
31
MB90570 Series
■ PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus
pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, however, values of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the
DDR register as output after writing output data to the PDR register when configuring the bit used as
input as outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
MB90570 Series
(2) Register Configuration
• Port 0 data register (PDR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR1)
000000H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 1 data register (PDR1)
Address bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
P17
P16
P15
P14
P13
P12
P11
P10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000001H
Initial value
XXXXXXXX B
(PDR0)
• Port 2 data register (PDR2)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR3)
000002H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P27
P26
P25
P24
P23
P22
P21
P20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 3 data register (PDR3)
Address bit 15
000003H
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
P37
P36
P35
P34
P33
P32
P31
P30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
(PDR2)
• Port 4 data register (PDR4)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000004H
(PDR5)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 5 data register (PDR5)
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
P57
P56
P55
P54
P53
P52
P51
P50
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15
000005H
Initial value
XXXXXXXX B
(PDR4)
• Port 6 data register (PDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR7)
000006H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 7 data register (PDR7)
Address bit 15
000007H
bit 14
—
—
—
—
bit 13
—
—
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
P74
P73
P72
P71
P70
R/W
R/W
R/W
R/W
R/W
Initial value
- - - XXXXX B
(PDR6)
• Port 8 data register (PDR8)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000008H
(PDR9)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P87
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Continued)
33
MB90570 Series
• Port 9 data register (PDR9)
Address
000009H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
P97
P96
P95
P94
P93
P92
P91
P90
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
(PDR8)
• Port A data register (PDRA)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00000AH
(PDRB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
• Port B data register (PDRB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
—
—
PC3
PC2
PC1
PC0
XXXXXXXX B
—
—
—
—
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(PDRA)
00000BH
• Port C data register (PDRC)
(Disabled)
00000CH
• Port 0 direction register (DDR0)
(DDR1)
000010H
• Port 1 direction register (DDR1)
Address
000011H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
D17
D16
D15
D14
D13
D12
D11
D10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
(DDR0)
• Port 2 direction register (DDR2)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(DDR3)
000012H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
D27
D26
D25
D24
D23
D22
D21
D20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 3 direction register (DDR3)
Address
000013H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
D37
D36
D35
D34
D33
D32
D31
D30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
(DDR2)
• Port 4 direction register (DDR4)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000014H
(DDR5)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D47
D46
D45
D44
D43
D42
D41
D40
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Continued)
34
MB90570 Series
• Port 5 direction register (DDR5)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
000015H
D57
D56
D55
D54
D53
D52
D51
D50
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
(DDR4)
• Port 6 direction register (DDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000016H
D67
D66
D65
D64
D63
D62
D61
D60
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DDR7)
• Port 7 direction register (DDR7)
Address
000017H
bit 15
bit 14
—
—
—
—
bit 13
—
—
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
D74
D73
D72
D71
D70
R/W
R/W
R/W
R/W
R/W
Initial value
- - - 00000 B
(DDR6)
• Port 8 direction register (DDR8)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(DDR9)
000018H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D87
D86
D85
D84
D83
D82
D81
D80
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 9 direction register (DDR9)
Address bit 15
000019H
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
D97
D96
D95
D94
D93
D92
D91
D90
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
(DDR8)
• Port A direction register (DDRA)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(DDRB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00001AH
• Port B direction register (DDRB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
—
—
DC3
DC2
DC1
DC0
00000000 B
—
—
—
—
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
OD45
OD44
OD43
OD42
OD41
OD40
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
00001BH
(DDRA)
• Port C direction register (DDRC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00001CH
(ODR4)
• Port 4 output pin register (ODR4)
00001DH
(DDRC)
OD47 OD46
R/W
R/W
• Port 0 input pull-up resistor setup register (RDR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00008CH
(RDR1)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
RD07
RD06
RD05
RD04
RD03
RD02
RD01
RD00
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Continued)
35
MB90570 Series
(Continued)
• Port 1 input pull-up resistor setup register (RDR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
00008DH
RD17
RD16
RD15
RD14
RD13
RD12
RD11
RD10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
(RDR0)
• Port 6 input pull-up resistor setup register (RDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00008EH
(Disabled)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
RD67
RD66
RD65
RD64
RD63
RD62
RD61
RD60
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
ADE0
11111111 B
R/W
• Analog input enable register (ADER)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00001EH
(Disabled)
R/W : Readable and writable
— : Reserved
X : Undefined
36
ADE7
ADE6 ADE5
ADE4 ADE3
ADE2
ADE1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90570 Series
(3) Block Diagram
• Input/output port
PDR (port data register)
Internal data bus
PDR read
Output latch
P-ch
PDR write
Pin
DDR (port direction register)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Output pin register (ODR)
To resource input
PDR (port data register)
From resource output
Resource output enable
PDR read
P-ch
Output latch
PDR write
Pin
Internal data bus
DDR (port direction register)
N-ch
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
ODR (output pin register)
ODR latch
ODR write
ODR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
37
MB90570 Series
• Input pull-up resistor setup register (RDR)
To resource input
PDR (port data register)
Pull-up resistor
About 5.0 kΩ
(5.0 V)
PDR read
Output latch
P-ch
P-ch
PDR write
Pin
Internal data bus
DDR (port direction register)
N-ch
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
RDR latch
RDR write
RDR
(input pull-up resistor setup register)
RDR read
Standby control: Stop, timebase timer mode and SPL=1
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
To analog input
ADER write
Internal data bus
PDR (port data register)
RMW
(read-modify-write
type instruction)
PDR read
Output latch
P-ch
PDR write
Pin
DDR (port direction register)
Direction latch
N-ch
DDR write
DDR read
Standby control: Stop, timebase timer mode and SPL=1
38
Standby control
(SPL=1)
MB90570 Series
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
0000A9H
RESV
—
—
TBIE
TBOF
TBR
TBC1
TBC0
—
—
—
R/W
R/W
W
R/W
R/W
bit 7 . . . . . . . . . . . .bit 0
(WDTC)
Initial value
1--00100B
R/W : Readable and writable
W : Write only
— : Unused
RESV: Reserved bit
(2) Block Diagram
To watchdog timer
To 8/16-bit PPG timer
Timebase timer counter
Divided-by-2
of HCLK
× 21 × 22 × 2 3
...
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Start stop mode
CKSCR: MCS = 1→0*1
Counter
clear circuit
Interval
timer selector
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
RESV
—
—
TBIE TBOF TBR
TBC1 TBC0
Timebase timer
interrupt signal
#34*2
OF: Overflow
HCLK: Oscillation clock
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt signal
39
MB90570 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
0000A8H
(TBTC)
bit 6
bit 5
bit 4
PONR STBR WRST ERST
R
R
R
bit 3
bit 2
bit 1
bit 0
SRST
WTE
WT1
WT0
R
W
W
W
R
Initial value
XXXXXXXX B
R : Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1
WT0
2
Watchdog timer
CLR and start
Overflow
Start sleep mode
Start hold status
Start stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
CLR
Watchdog timer
reset generation
circuit
CLR
4
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
× 21 × 22
HCLK: Oscillation clock
40
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
To internal reset
generation circuit
MB90570 Series
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-CH independent operation mode
This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same
output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0
is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0
and PPG1 respectively.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
41
MB90570 Series
(1) Register Configuration
• PPG0 operating mode control register ch.0 (PPGC0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PPGC1)
000044H
bit 6
bit 5
bit 4
bit 3
PEN0
—
PE00
PIE0
PUF0
R/W
—
R/W
R/W
R/W
bit 2
bit 1
bit 0
Initial value
—
—
RESV
0X0 0 0XX1 B
—
—
—
• PPG1 operating mode control register ch.1 (PPGC1)
Address bit 15
000045H
bit 8 bit 7 . . . . . . . . . . . . bit 0
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
PEN1
—
PEI0
PIE1
PUF1
MD1
MD0
RESV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0X0 0 0 0 0 1 B
(PPGC0)
• PPG0, 1 output control register ch.0, ch.1(PPGOE)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(Disabled)
000046H
bit 6
PCS2 PCS1
R/W
R/W
bit 5
bit 4
PCS0
PCM2 PCM1 PCM0
R/W
R/W
bit 3
R/W
bit 2
R/W
bit 1
bit 0
Initial value
—
—
0 0 0 0 0 0XX B
—
—
• PPG0 reload register H ch.0 (PRLH0)
Address bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
(PRLL0)
000041H
R/W
R/W
R/W
R/W
R/W
R/W
bit 12
bit 11
bit 10
R/W
R/W
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
Initial value
XXXXXXXX B
• PPG1 reload register H ch.1 (PRLH1)
Address bit 15
bit 14
bit 13
(PRLL1)
000043H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
R/W
• PPG0 reload register L ch.0 (PRLL0)
Address
000040H
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(PRLH0)
Initial value
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
• PPG1 reload register L ch.1 (PRLL1)
000042H
R/W
R/W : Readable and writable
— : Reserved
X : Undefined
RESV: Reserved bit
42
Initial value
XXXXXXXX B
(PRLH1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90570 Series
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer (ch.0)
Data bus for “H” digits
Data bus for “L” digits
PPG0 reload
register
PEN0
PRLL0
PRLH0
PPG0 output
control register
ch.0 (PPGOE0)
PPG0 operating mode
control register ch.0 (PPGC0)
—
PE00 PIE0 PUF0
—
—
RESV
PCM2 PCM1 PCM0
R
Temporary buffer
(PRLBH0)
S
Interrupt request
#26*
Q
2
Reload register
(L/H selector)
Mode control signal
Select signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Count value
Re-load
Clear
Pulse selector
Down counter
(PCNT0)
Underflow
CLK
Reverse
PPG0
output latch
Pin
P46/PPG0
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
PPG output
control circuit
Count
clock
selector
3
Select signal
* : Interrupt number
HCLK : Oscillation clock
φ : Machine clock frequency
43
MB90570 Series
• Block diagram of 8/16-bit PPG timer (ch.1)
Data bus for “H” digits
Data bus for “L” digits
PPG1 reload
register
PRLL1
PRLH1
PEI0 PIE1 PUF1 MD1 MD0 RESV PCS2 PCS1 PCS0
PEN1 —
Operating mode
control signal
2
R
Temporary buffer
(PRLBH1)
Count value
Select signal
Re-load
Down counter
(PCNT1)
PPG1 underflow
(to PPG0)
Interrupt request
#28*
S Q
Reload selector
(L/H selector)
Clear
Underflow
Reverse
PPG1
output latch
CLK
MD0
PPG output control circuit
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Count clock selector
Select signal
* : Interrupt number
HCLK : Oscillation clock
φ : Machine clock frequency
Pin
P47/PPG1
PPG0 underflow
44
PPG1 output control
register ch.1 (PPGOE1)
PPG1 operating mode
control register ch.1 (PPGC1)
MB90570 Series
5. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output
comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run
timer. Input pulse width and external clock periods can, therefore, be measured.
• Block Diagram
Internal data bus
Input capture
Dedicated
bus
16-bit
free run timer
Dedicated
bus
Output compare
45
MB90570 Series
(1) 16-bit free run Timer
The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler
register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/32 and φ/64).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0.
(Compare match requires mode setup.)
• The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0.
• Register Configuration
• free run timer data register (TCDT)
Address
000056H
000057H
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
T15 T14 T13 T12 T11 T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
• free run timer control status register (TCCS)
bit 15. . . . . . . . . . . . .bit 8 bit 7
Address
000058H
(Disabled)
bit 3
bit 6
bit 5
bit 4
RESV
IVF
IVFE
STOP MODE
R/W
R/W
R/W
R/W
R/W
bit 2
bit 1
bit 0
Initial value
CLR
CLK1
CLK0
00000000B
R/W
R/W
R/W
R/W : Readable and writable
RESV: Reserved bit
• Block Diagram
Count value output
to ICO and OCU
free run timer data register (TCDT)
OF
16-bit counter
φ
STOP
CLR
Communications
prescaler register
OCU compare register ch.0
match signal
2
free run timer
control status register
(TCCS)
RESV
IVF
IVFE STOP MODE CLR CLK1 CLK0
16-bit free run timer
interrupt request
#20*
* : Interrupt number
φ : Machine clock frequency
OF : Overflow
46
Internal data bus
CLK
MB90570 Series
(2) Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture external pins and ICU data registers, enabling
measurements of maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling
measurements of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths.
• Register Configuration
• ICU data register ch.0, ch.1 (IPCP0, IPCP1)
Address
IPCP0(high): 000051H
IPCP1(high): 000053H
Address
IPCP0(low): 000050H
IPCP1(low): 000052H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . . bit 0
Initial value
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
XXXXXXXXB
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
R
R
R
R
R
R
bit 15. . . . . . . . . . . . bit 8
(IPCP0 high, IPCP1 high) CP07
R
(IPCP0 low, IPCP1 low)
Initial value
XXXXXXXXB
Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is
detected. (You can word-access this register, but you cannot program it.)
• ICU control status register (ICS01)
Address
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
000054H
(Disabled)
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01 EG00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 0
Initial value
00000000B
R/W
R/W : Readable and writable
R : Read only
X : Undefined
47
MB90570 Series
• Block Diagram
Internal data bus
Latch
signal
Output latch
ICU data register (IPCP)
Edge detection circuit
P56/IN0
Pin
P57/IN1
Data latch signal
IPCP0H
IPCP0L
2
Pin
IPCP1H
IPCP1L
2
ICU control status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Interrupt request
#12*
Interrupt request
#14*
* : Interrupt number
48
16
16
16-bit free run
timer
MB90570 Series
(3) Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a
comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit.
• Register Configuration
• OCU control status register ch.1, ch.3 (OCS1, OCS3)
Address
bit 15
bit 14
bit 13
000063H
000065H
—
—
—
—
—
—
bit 12
bit 11
bit 10
CMOD OTE1
R/W
bit 9
OTE0 OTD1
R/W
R/W
R/W
bit 8 bit 7 . . . . . . . . . . . . . bit 0
OTD0
(OCS0, OCS2)
Initial value
- - - 00000 B
R/W
• OCU control status register ch.0, ch.2 (OCS0, OCS2)
Address
000062H
000064H
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
(OCS1, OCS3)
ICP1
ICP0
ICE1
ICE0
—
—
CST1
CST0
0000 - - 00 B
R/W
R/W
R/W
R/W
—
—
R/W
R/W
bit 10
bit 9
• OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)
Address
OCCP0 (high order address): 00005BH
OCCP1 (high order address): 00005DH
OCCP2 (high order address): 00005FH
OCCP3 (high order address): 000061H
Address
OCCP0 (low order address): 00005AH
OCCP1 (low order address): 00005CH
OCCP2 (low order address): 00005EH
OCCP3 (low order address): 000060H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 8
Initial value
XXXXXXXXB
C15
C14
C13
C12
C11
C10
C09
C08
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXXB
C07
C06
C05
C04
C03
C02
C01
C00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
— : Reserved
X : Undefined
49
MB90570 Series
• Block diagram
#16*
OCU control
status register ch.0, ch.1 (OCS0, OCS1)
—
—
—
Output compare
interrupt request
#15*
CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0
ICE1
ICE0
—
—
CST1 CST0
2
2
16-bit free run timer
Compare control circuit 3
OCCP3
OCU compare register ch.3
Internal data bus
Compare control circuit 2
P67/OUT3
Output
control circuit 3
OCCP2
Pin
OCU compare register ch.2
P66/OUT2
Output
control circuit 2
Pin
Compare control circuit 1
P65/OUT1
OCCP1
Output
control circuit 1
Pin
OCU compare register ch.1
P64/OUT0
Output
control circuit 0
Compare control circuit 0
Pin
OCCP0
OCU compare register ch.0
2
2
OCU control status register
ch.2, ch.3 (OCS2, OCS3)
—
—
—
CMOD OTE1 OTE0 OTD1 OTD0 ICP1
ICP0
ICE1
ICE0
—
—
CST1 CST0
#18*
#17*
* : Interrupt number
50
Output compare
interrupt request
MB90570 Series
6. 8/16-bit up/down counter/timer
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
reload compare registers, and their controllers.
(1) Register configuration
• Up/down count register 0 (UDCR0)
Address
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000 B
R
R
R
R
R
R
R
R
000070H
(UDCR1)
• Up/down count register 1 (UDCR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
000071H
D17
D16
D15
D14
D13
D12
D11
D10
(UDCR0)
00000000 B
R
R
R
R
R
R
R
R
• Reload compare register 0 (RCR0)
Address
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
00000000 B
W
W
W
W
W
W
W
W
(RCR1)
000072H
• Reload compare register 1 (RCR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
000073H
D17
D16
D15
D14
D13
D12
D11
D10
(RCR0)
00000000 B
W
W
W
W
W
W
W
W
• Counter status register 0, 1 (CSR0, CSR1)
Address
000074H
000078H
bit 15 . . . . . . . . . . . . bit 8 bit 7
(Reserved area)
bit 6
bit 5
bit 4
CSTR
CITE
UDIE
CMPF
R/W
R/W
R/W
bit 3
bit 2
bit 1
OVFF UDFF UDF1
bit 0
Initial value
UDF0
00000000 B
R/W
R/W
R/W
R
R
bit 4
bit 3
bit 2
bit 1
bit 0
• Counter control register 0, 1 (CCRL0, CCRL1)
Address
000076H
00007AH
bit 15 . . . . . . . . . . . . bit 8 bit 7
(CCRH0, CCRH1)
—
—
bit 6
bit 5
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
- 0000000 B
R/W
• Counter control register 0 (CCRH0)
Address
bit 15
000077H
bit 14
bit 13
bit 12
M16E CDCF
CFIE
CLKS CMS1 CMS0 CES1 CES0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
(CCRL0)
00000000 B
bit 7 . . . . . . . . . . . . . bit 0
Initial value
(CCRL1)
- 0000000 B
• Counter control register 1 (CCRH1)
Address
bit 15
bit 14
bit 13
00007BH
—
CDCF
CFIE
CLKS CMS1 CMS0 CES1 CES0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
R : Read only
W : Write only
— : Undefined
51
MB90570 Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Reload compare register 0
Re-load
control
circuit
UDCR0
CARRY/
BORRW
Up/down count register 0
(to channel 1)
Counter control
register 0 (CCRL0)
Counter clear
circuit
PA2/ZIN0
Pin
Edge/level
detection circuit
φ
Prescaler
PA0/AIN0/IRQ6
Pin
Underflow
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow
—
Compare
control circuit
Count clock
Counter status
register 0 (CSR0)
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
PA1/BIN0
Interrupt request
#29*
Interrupt request
#30*
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 0 (CCRH0)
* : Interrupt number
φ: Machine clock frequency
52
M16E
(to channel 1)
MB90570 Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Reload compare register 1
Re-load
control
circuit
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
PA5/ZIN1
Counter clear
circuit
Edge/level
detection circuit
Pin
CARRY/BORRW
(from channel 0)
Compare
control circuit
Count clock
Counter status
register 1 (CSR1)
φ
PA3/AIN1/IRQ7
Underflow
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow
—
Prescaler
Pin
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
PA4/BIN1
M16E
(from channel 1)
Interrupt request
#31*
Interrupt request
#32*
—
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 1 (CCRH1)
* : Interrupt number
φ: Machine clock frequency
53
MB90570 Series
7. Extended I/O serial interface
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)
Address
SMCSH0: 000049H
SMCSH1: 00004DH
SMCSH2: 00007DH
bit 15
bit 14
bit 13
SMD2 SMD1 SMD0
R/W
R/W
R/W
bit 12
bit 11
SIE
SIR
R/W
R/W
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
(SMCSL)
00000010 B
BUSY STOP STRT
R
R/W
R/W
• Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)
Address
SMCSL0: 000048H
SMCSL1: 00004CH
SMCSL2: 00007CH
bit 15 . . . . . . . . . . . . bit 8 bit 7
Address
SDR0: 00004AH
SDR1: 00004EH
SDR2: 00007EH
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
—
—
• Serial data register 0 to 2 (SDR0 to SDR2)
—
—
—
—
MODE
BDS
SOE
SCOE
- - - - 0000 B
R/W
R/W
R/W
R/W
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(SMCSH)
(Disabled)
R/W : Readable and writable
R : Read only
— : Reserved
X : Undefined
54
MB90570 Series
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7
D7 to D0 (LSB first)
Pin
P40/SIN0
Transfer direction selection
Pin
Read
Write
Serial data register
(SDR)
P43/SIN1
Pin
P41/SOT0
Pin
Pin
P50/SIN2
P44/SOT1
Pin
P51/SOT2
Pin
P45/SCK1
Control circuit
Shift clock counter
Pin
P52/SCK2
Pin
P42/SCK0
Internal clock
2
1
0
SMD2 SMD1 SMD0
Serial mode control
status register (SMCS)
*: Interrupt number
SIE SIR BUSY STOP STRT
—
—
—
—
MODE
BDS SOE SCOE
Interrupt request
#19 (SMCS0)*
#21 (SMCS1)*
#23 (SMCS2)*
55
MB90570 Series
8. I2C Interface
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus.
The MB90570/A series contains one channel of an I2C interface, having the following features.
•
•
•
•
•
•
•
Master/slave transmission/reception
Arbitration function
Clock synchronization function
Slave address/general call address detection function
Transmission direction detection function
Repeated generation function start condition and detection function
Bus error detection function
(1) Register Configuration
• I2C bus status register (IBSR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(IBCR)
000068H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
00000000B
R
R
R
R
R
R
R
R
• I2C bus control register (IBCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . bit 0
Initial value
000069H
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
(IBSR)
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus clock control register (ICCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00006AH
(IADR)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
EN
CS4
CS3
CS2
CS1
CS0
--0XXXXXB
—
—
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus address register (IADR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . bit 0
Initial value
00006BH
—
A6
A5
A4
A3
A2
A1
A0
(ICCR)
-XXXXXXXB
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus data register (IDAR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00006CH
(Disabled)
R/W : Readable and writable
R : Read only
— : Reserved
X
: Indeterminate
56
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXXB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90570 Series
(2) Block Diagram
Internal data bus
I2C bus status register
(IBSR)
Start stop condition
generation circuit
General call
Slave
Transmit/receive
Last bit
Repeat start
Transmission
complete flag
Interrupt enable
GC-ACK enable
ACK enable
BB RSC AL LRB TRX AAS GCA FBT
Detection of first byte
Number of
interrupt
request
generated
Master
Start
Error
BER BEIE SCC MSS ACK GCAA INTE INT
Bus busy
I2C bus control register
(IBCR)
Start stop condition
detection circuit
Interrupt request signal
#36*
SDA line
SCL line
Pin
PA6/SDA
I2C enable
Pin
IDAR register
PA7/SCL
Arbitration lost
detection circuit
Slave address
comparison circuit
IADR register
Clock control block
Sync
Clock
divider 1 4
(1/5 to
1/8)
φ
Count
clock
selector 1
Clock
8
divider 2
Count
clock
selector 2
Shift clock
generation
circuit
I2C enable
—
—
EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register
(ICCR)
φ: Machine clock frequency
* : Interrupt number
57
MB90570 Series
9. UART0 (SCI), UART1 (SCI)
UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing
synchronous or asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: Embedded dedicated baud rate generator
External clock input possible
Internal clock (a clock supplied from 16-bit reload timer 0 can be used.)
Internal machine clock
Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps
For 6 MHz, 8 MHz, 10 MHz
CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps
12 MHz and 16 MHz
• Data length: 7 bit to 9 bit selective (without a parity bit)
6 bit to 8 bit selective (with a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection: Framing error
Overrun error
Parity error (multi-processor mode is supported, enabling setup of any baud rate
by an external clock.)
• Interrupt request: Receive interrupt (receive complete, receive error detection)
Transmit interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
}
58
MB90570 Series
(1) Register Configuration
• Serial control register 0,1 (SCR0, SCR1)
Address
000021H
000025H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
(SMR0, SMR1)
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
Initial value
00000100 B
• Serial mode register 0, 1 (SMR0, SMR1)
Address
000020H
000024H
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(SCR0, SCR1)
MD1
MD0
CS2
CS1
CS0
RESV
SCKE
SOE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
• Serial status register 0,1 (SSR0, SSR1)
Address
000023H
000027H
bit 15
bit 14
bit 13
bit 12
bit 11
PE
ORE
FRE
RDRF TRDE
R
R
R
R
R
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
—
RIE
TIE
(SIDR0, SIDR1/SODR0,SODR1)
—
R/W
R/W
Initial value
00001 - 00 B
• Serial input data register 0,1 (SIDR0, SIDR1)
Address
000022H
000026H
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(SSR0, SSR1)
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX B
• Serial output data register 0,1 (SODR0, SODR1)
Address
000022H
000026H
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(SSR0, SSR1)
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Initial value
XXXXXXXX B
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address
000028H
00002AH
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(Disabled)
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W: Readable and writable
R : Read only
W : Write only
— : Reserved
X : Undefined
RESV: Reserved bit
Initial value
0 - - - 1111 B
59
MB90570 Series
(2) Block Diagram
• UART0 (SCI)
Control bus
Dedicated baud
rate generator
8/16-bit PPG
timer 1 (upper)
External clock
Receive
interrupt signal
#39*
Transmit
interrupt signal
#40*
Transmit
clock
Clock
selector
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P42/SCK0
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P41/SOT0
Shift register for
transmission
Shift register for
reception
Pin
P40/SIN0
Reception
complete
SIDR0
Start transmission
SODR0
Receive condition
decision circuit
To I2C reception
error generation
signal (to CPU)
Internal data bus
SMR0
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
* : Interrupt number
60
SCR0
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
MB90570 Series
• UART1 (SCI)
Control bus
Dedicated baud
rate generator
8/16-bit PPG
timer 1 (upper)
Receive
interrupt signal
#37*
Transmit
interrupt signal
#38*
Transmit
clock
Clock
selector
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P45/SCK1
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P44/SOT1
Shift register for
transmission
Shift register for
reception
Pin
P43/SIN1
Reception
complete
SIDR1
Start transmission
SODR1
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
SMR1
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
* : Interrupt number
61
MB90570 Series
10. DTP/External Interrupt Circuit
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing.
As request levels for IRQ2 to IRQ7, two types of “H” and “L” can be selected for the intelligent I/O service. Rising
and falling edges as well as “H” and “L” can be selected for an external interrupt request. For IRQ0 and IRQ1,
a request by a level cannot be entered, but both edges can be entered.
* : The external peripheral circuit is connected outside the MB90570/A series device.
Note: IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000031H
(ENIR)
Initial value
XXXXXXXX B
• DTP/interrupt enable register (ENIR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000030H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(EIRR)
Initial value
00000000 B
• Request level setting register (ELVR)
Low order address 000032H
(ELVR upper)
Address bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
High order address 000033H
R/W: Readable and writable
X : Undefined
62
(ELVR lower)
Initial value
00000000 B
Initial value
00000000 B
Pin
PB0/IRQ0
Pin
PB1/IRQ1
Pin
PB2/IRQ2
Pin
PB3/IRQ3
*: Interrupt number
Internal data bus
Pin
PB4/IRQ4
Pin
PB5/IRQ5
Pin
PA0/AIN0/IRQ6
Pin
PA3/AIN1/IRQ7
Level edge
selector 6
Level edge
selector 7
2
EN7
ER7
LB7
EN6
ER6
LA7
EN5
ER5
2
LB6
EN4
ER4
LA6
2
LA5
EN3
ER3
EN2
ER2
Level edge
selector 4
EN1
ER1
LB4
Level edge
selector 5
LB5
Request level setting register (ELVR)
2
LB3
2
LA3
LA2
Level edge
selector 2
Level edge
selector 3
LB2
2
LB1
Interrupt request signal
EN0 DTP/interrupt enable register (ENIR)
#13*
#24*
#25*
#27*
#33*
#35*
LB0
Level edge
selector 0
Level edge
selector 1
LA0
DTP/external interrupt
input detection circuit
2
LA1
ER0 DTP/interrupt factor register (EIRR)
LA4
2
MB90570 Series
(2) Block Diagram
63
MB90570 Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00009FH
—
—
—
—
—
—
—
R0
—
—
—
—
—
—
—
R/W
(PACSR)
Initial value
- - - - - - -0B
Note: Upon a reset, an interrupt is canceled.
R/W: Readable and writable
— : Reserved
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either “0” or “1”.
For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
(2) Block Diagram
Internal data bus
—
—
—
—
—
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
64
—
—
R0
S factor
R latch
Interrupt request signal
#42*
MB90570 Series
12. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 26.3 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 4 µs/256 µs (at machine clock of 16 MHz)
• Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below
8 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• 8-bit or 10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation (conversion can be started synchronously.)
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selected from software activation, and external trigger (falling edge).
65
MB90570 Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
000037H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT RESV
R/W
R/W
R/W
R/W
R/W
R/W
W
(ADCS1)
Initial value
00000000 B
R/W
• A/D control status register lower digits (ADCS1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000036H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(ADCS2)
Initial value
00000000 B
• A/D data register upper digits (ADCR2)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
000039H
DSEL
ST1
ST0
CT1
XCT0
—
D9
D8
W
W
W
W
W
—
—
—
(ADCR1)
Initial value
0 0 0 0 1 - XX B
• A/D data register lower digits (ADCR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000038H
(ADCR2)
R/W: Readable and writable
R : Read only
W : Write only
— : Reserved
X : Undefined
RESV: Reserved bit
66
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX B
MB90570 Series
(2) Block Diagram
A/D control status
register (ADCS)
Interrupt request #11*
BUSY INT INTE PAUS STS1 STS0 STRT
DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
6
2
Clock selector
Decoder
Internal data bus
PB6/ADTG
TO
φ
Comparator
P87/AN7
P86/AN6
P85/AN5
P84/AN4
P83/AN3
P82/AN2
P81/AN1
P80/AN0
Sample hold
circuit
Control circuit
Analog
channel
selector
A/D data register RESV
ST1 ST0 CT1 CT0
(ADCR)
AVRH, AVRL
AVCC
AVSS
—
D9
D8
8-bit D/A converter
D7
D6
D5
D4
D3
D2
D1
D0
φ : Machine clock frequency
TO : 8/16-bit PPG timer channel 1 output
* : Interrupt number
67
MB90570 Series
13. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00003AH
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DADR1)
Initial value
XXXXXXXX B
• D/A converter data register ch.1 (DADR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
00003BH
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DADR0)
Initial value
XXXXXXXX B
• D/A control register 0 (DACR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
00003CH
(DACR1)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
—
—
—
—
—
—
—
DAE0
—
—
—
—
—
—
—
R/W
Initial value
- - - - - - -0B
• D/A control register 1 (DACR1)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00003DH
—
—
—
—
—
—
—
DAE1
—
—
—
—
—
—
—
R/W
R/W: Readable and writable
— : Reserved
X : Undefined
68
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
(DACR0)
Initial value
- - - - - - -0B
MB90570 Series
(2) Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)
D/A converter data register ch.0 (DADR0)
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
D/A converter 1
D/A converter 0
DVRH
DVRL
DA07
DA17
Pin
2R
DA16
2R
DA15
2R
DA14
2R
DA13
2R
DA12
2R
DA11
2R
DA10
2R
P74/DA1
R
Pin
2R
DA06
2R
R
DA05
R
DA04
R
DA03
R
DA02
R
DA01
R
DA00
2R
2R
2R
2R
2R
2R
2R
DVSS
—
—
R
R
R
R
R
2R
Standby control
D/A control register 1 (DACR1)
—
R
DVSS
Standby control
—
P73/DA0
R
—
D/A control register 0 (DACR0)
—
— DAE1
—
—
—
—
—
—
— DAE0
Internal data bus
69
MB90570 Series
14. Clock Timer
The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt.
(1) Register Configuration
• Clock timer control register (WTC)
. . . . . . . . . . . . bit 8 bit 7
Address bit 15
(Disabled)
0000AAH
bit 6
bit 5
WDCS
SCE
WTIE WTOF
R/W
R
R/W
bit 4
R/W
bit 3
WTR
R/W
bit 2
bit 1
bit 0
WTC2 WTC1 WTC0
R
R/W
Initial value
1X0 0 0 0 0 0 B
R/W
R/W: Readable and writable
R : Read only
X : Undefined
(2) Block Diagram
To watchdog timer
Clock counter
LCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF
OF
OF
OF
OF
OF
OF
Power-on reset
Shift to a hardware standby
Counter
clear circuit
To sub-clock oscillation stabilization
time controller
Shift to stop mode
Interval
timer selector
Clock timer interrupt request
#22*
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Clock timer control register (WTC)
* : Interrupt number
OF : Overflow
LCLK : Oscillation sub-clock frequency
70
MB90570 Series
15. Chip Select Output
This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip
select output pins. When access to an address is detected with a hardware-set area set for each pin register,
a select signal is output from the pin.
(1) Register Configuration
• Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7)
Address
CSCR1: 000081H
CSCR3: 000083H
CSCR5: 000085H
CSCR7: 000087H
bit 8 bit 7 . . . . . . . . . . . . bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
—
—
—
—
ACTL
OPEL
CSA1
CSA0
—
—
—
—
R/W
R/W
R/W
R/W
(CSCR0, CSCR2, CSCR4, CSCR6)
Initial value
- - - - 0000 B
• Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
CSCR0: 000080H
CSCR2: 000082H (CSCR1, CSCR3, CSCR5, CSCR7) —
CSCR4: 000084H
—
CSCR6: 000086H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
—
—
—
ACTL
OPEL
CSA1
CSA0
—
—
—
R/W
R/W
R/W
R/W
Initial value
- - - - 0000 B
R/W: Readable and writable
— : Reserved
71
MB90570 Series
(2) Block Diagram
From address (CPU)
A23
A22
⋅⋅⋅⋅⋅
A17
A16
A15
Address decoder
A14
⋅⋅⋅⋅⋅
A01
A00
Address decoder
Decode signal
Program area
Decode
P90/CS0
(Program ROM area application)
2
Select and set
Selector
Chip selection control register 0 (CSCR0)
Select and set
Chip selection control register 1 (CSCR1)
Selector
P91/CS1
Select and set
Chip selection control register 2 (CSCR2)
Selector
P92/CS2
Select and set
Selector
Chip selection control register 3 (CSCR3)
P93/CS3
Select and set
Chip selection control register 4 (CSCR4)
Selector
P94/CS4
Select and set
Selector
Chip selection control register 5 (CSCR5)
P95/CS5
Select and set
Chip selection control register 6 (CSCR6)
Selector
P96/CS6
Chip selection control register 7 (CSCR7)
Select and set
Selector
P97/CS7
72
MB90570 Series
(3) Decode Address Spaces
Pin
name
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CSA
Decode space
Number of
area bytes
1
0
0
0
F00000H to FFFFFFH
1 Mbyte
0
1
F80000H to FFFFFFH
512 kbyte
1
0
FE0000H to FFFFFFH
128 kbyte
1
1
0
0
E00000H to EFFFFFH
1 Mbyte
0
1
F00000H to F7FFFFH
512 kbyte
1
0
FC0000H to FDFFFFH
128 kbyte
1
1
68FF80H to 68FFFFH
128 byte
0
0
003000H to 003FFFH
4 kbyte
0
1
FA0000H to FBFFFFH
128 kbyte
1
0
68FF80H to 68FFFFH
128 byte
1
1
68FF00H to 68FF7FH
128 byte
0
0
F80000H to F9FFFFH
128 kbyte
0
1
68FF00H to 68FF7FH
128 byte
1
0
68FE80H to 68FEFFH
128 byte
1
1
0
0
002800H to 002FFFH
2 kbyte
0
1
68FE80H to 68FEFFH
128 byte
1
0
—
Disabled
1
1
—
Disabled
0
0
0
1
—
Disabled
1
0
—
Disabled
1
1
—
Disabled
0
0
0
1
—
Disabled
1
0
—
Disabled
1
1
—
Disabled
—
—
—
Disabled
—
—
68FF80H to 68FFFFH
68FF00H to 68FF7FH
Remarks
Becomes active when the program ROM
area or the program vector is fetched.
Disabled
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Disabled
128 byte
128 byte
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Adapted to the data ROM and RAM areas,
and external circuit connection
applications.
Disabled
73
MB90570 Series
16. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O
serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000028H
00002AH
(Disabled)
R/W: Readable and writable
— : Reserved
74
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
R/W
—
—
—
R/W
R/W
R/W
R/W
Initial value
0 - - - 1111 B
MB90570 Series
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PADR0 (Low order address): 001FF0H
Address
PADR0 (Middle order address): 001FF1H
Address
PADR0 (High order address): 001FF2H
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
• Program address detection register 3 to 5 (PADR1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 3
bit 2
PADR1 (Low order address): 001FF3H
Address
PADR1 (Middle order address): 001FF4H
Address
PADR1 (High order address): 001FF5H
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
• Program address detection control status register (PACSR)
Address
bit 7
00009EH
RESV
R/W
bit 6
bit 5
RESV RESV
R/W
R/W
bit 4
RESV AD1E RESV
R/W
R/W
R/W
bit 1
bit 0
AD0E
RESV
R/W
R/W
Initial value
00000000 B
R/W: Readable and writable
X : Undefined
RESV: Reserved bit
75
MB90570 Series
Internal data bus
Address latch
76
Address detection
register
Enable bit
Compare
(2) Block Diagram
INT9
instruction
F2MC-16LX
CPU core
MB90570 Series
18. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
00006FH
—
—
—
—
—
—
—
MI
—
—
—
—
—
—
—
W
(Disabled)
Initial value
- - - - - - -1B
W : Write only
— : Reserved
Note: Do not access this register during operation at addresses 004000H to 00FFFFH.
(2) Block Diagram
Internal data bus
ROM mirroring function selection
register (ROMM)
Address area
Address
FF bank
00 bank
Data
ROM
77
MB90570 Series
19. Low-power Consumption (Standby) Mode
The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
• Clock mode
PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock (HCLK).
Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the
oscillation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
• Hardware standby mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions
(timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes,
modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
0000A1H
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
(LPMCR)
Initial value
11111100 B
• Low-power consumption mode control register (LPMCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0000A0H
STP
SLP
SPL
RST
TMD
CG1
CG0
SSR
W
W
R/W
W
R/W
W
R/W
R/W
(CKSCR)
R/W: Readable and writable
R : Read only
W : Write only
78
Initial value
00011000 B
MB90570 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register
(LPMCR)
STP SLP SPL RST TMD CG1 CG0 SSR
CPU intermittent
operation cycle
selector
2
CPU clock
control circuit
CPU operation
clock
Clock mode
Sleep signal
Stop signal
Hardware
standby
Peripheral clock
control circuit
S
Q
S
R
Reset
Interrupt
Q
R
S
Q
S
R
Peripheral function
operation clock
Machine clock
Q
R
Clock selector
Oscillation
stabilization
time selector
2
2
PLL multiplication
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0
X1
Pin
Oscillation
clock
Pin
1/2
Clock oscillator
Main
clock
1/2048
1/4
1/4
1/8
Timebase timer
To watchdog timer
X0A Pin
X1A Pin
Oscillation
sub-clock
1/1024
1/8
1/2
1/2
Clock timer
Sub-clock oscillator
S: Set
R: Reset
Q: Output
79
MB90570 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 6.0
V
AVCC
VSS – 0.3
VSS + 6.0
V
*1
AVRH,
AVRL
VSS – 0.3
VSS + 6.0
V
*1
DVRH
VSS – 0.3
VSS + 6.0
V
*1
Input voltage
VI
VSS – 0.3
VSS + 6.0
V
*2
Output voltage
VO
VSS – 0.3
VSS + 6.0
V
*2
“L” level maximum output current
IOL

15
mA
*3
“L” level average output current
IOLAV

4
mA
*4
“L” level total maximum output current
ΣIOL

100
mA
“L” level total average output current
ΣIOLAV

50
mA
*5
“H” level maximum output current
IOH

–15
mA
*3
“H” level average output current
IOHAV

–4
mA
*4
“H” level total maximum output current ΣIOH

–100
mA

–50
mA
*5

300
mW
MB90573/4
MB90V570/A

500
mW
MB90574C

800
mW
MB90F574/A
Power supply voltage
“H” level total average output current
Power consumption
ΣIOHAV
PD
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
*1:
*2:
*3:
*4:
*5:
AVCC, AVRH, AVRL, and DVRH shall never exceed VCC. AVRL shall never exceed AVRH.
VI and VO shall never exceed VCC + 0.3 V.
The maximum output current is a peak value for a corresponding pin.
Average output current is an average current value observed for a 100 ms period for a corresponding pin.
Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
MB90570 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
3.0
5.5
V
Normal operation (MB90574/C)
VCC
4.5
5.5
V
Normal operation (MB90F574/A)
VCC
3.0
5.5
V
Retains status at the time of
operation stop
Smoothing capacitor
CS
0.1
1.0
µF
*
Operating temperature
TA
–40
+85
°C
Power supply voltage
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin connection circuit
C
CS
81
MB90570 Series
3. DC Characteristics
Parameter Symbol
“H” level
input
voltage
“L” level
input
voltage
VIHS
VIHM
VILS
Pin name
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
CMOS
hysteresis input
0.8 VCC
pin
VCC = 3.0 V to 5.5 V
(MB90573)
MD pin input
VCC – 0.3
(MB90574)
CMOS
VCC = 4.5 V to 5.5 V
hysteresis input (MB90F574)
VSS – 0.3
pin
—
VCC + 0.3
V
—
VCC + 0.3
V
—
0.2 VCC
V
VILM
MD pin input
VSS – 0.3
—
VSS + 0.3
V
“H” level
output
voltage
VOH
Other than PA6 VCC = 4.5 V
and PA7
IOH = –2.0 mA
VCC – 0.5
—
—
V
“L” level
output
voltage
VOL
All output pins
—
—
0.4
V
—
0.1
5
µA
VCC = 4.5 V
IOL = 2.0 mA
Open-drain
output
Ileak
leakage
current
PA6, PA7
Input
leakage
current
IIL
Other than PA6 VCC = 5.5 V
and PA7
VSS < VI < VCC
–5
—
5
µA
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P60 to P67,
RST, MD0,
MD1
—
15
30
100
kΩ
Pull-down
resistance
RDOWN
MD0 to MD2
—
15
30
100
kΩ
ICC
VCC
—
30
40
mA MB90574
ICC
VCC
—
85
130
mA MB90F574/A
ICC
VCC
—
50
80
mA MB90574C
ICC
VCC
—
35
45
mA MB90574
ICC
VCC
—
90
140
mA MB90F574/A
ICC
VCC
—
55
85
mA MB90574C
ICC
VCC
—
40
50
mA MB90574
ICC
VCC
—
95
145
mA MB90F574/A
ICC
VCC
—
65
85
mA MB90574C
Power
supply
current*
—
Internal operation
at 16 MHz
VCC at 5.0 V
Normal operation
Internal operation
at 16 MHz
VCC at 5.0 V
A/D converter
operation
Internal operation
at 16 MHz
VCC at 5.0 V
D/A converter
operation
(Continued)
82
MB90570 Series
(Continued)
Parameter Symbol
Power
supply
current*
Pin name
ICC
VCC
ICCS
VCC
ICCS
VCC
ICCS
VCC
ICCL
VCC
ICCL
VCC
ICCL
VCC
ICCLS
VCC
ICCLS
VCC
ICCLS
VCC
ICCT
VCC
ICCT
VCC
ICCT
VCC
ICCH
VCC
ICCH
VCC
Input
CIN
capacitance
Other than AVCC,
AVSS, VCC, VSS
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
When data written
in flash mode
programming of
erasing
—
95
140
mA MB90F574/A
Internal operation
at 16 MHz
VCC = 5.0 V
In sleep mode
—
7
12
mA MB90574
—
5
10
mA MB90F574/A
—
15
20
mA MB90574C
Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
Subsystem
operation
—
0.1
1.0
mA MB90574
—
4
7
mA MB90F574/A
—
0.03
1
mA MB90574C
Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
In subsleep mode
—
30
50
mA MB90574
—
0.1
1
mA MB90F574/A
—
10
50
µA
MB90574C
Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
In clock mode
—
15
30
µA
MB90574
—
30
50
µA
MB90F574/A
—
1.0
30
µA
MB90574C
—
5
20
µA
MB90574
—
0.1
10
µA
MB90F574/A
MB90574C
—
10
80
pF
TA = +25°C
In stop mode
—
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous
notice.
83
MB90570 Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
Parameter
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
Max.
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
—
4 tCP*
—
ns
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
• Measurement conditions for AC characteristics
Pin
CL
CL is a load capacitance connected to a pin under test.
Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must
be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.
84
MB90570 Series
(2) Specification for Power-on Reset
Parameter
Symbol Pin name Condition
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
—
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Max.
0.05
30
ms *
Due to repeated
4
—
ms
operations
* : VCC must be kept lower than 0.2 V before power-on.
Notes: • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per
second, however, you can use the PLL clock.
VCC
3.0 V
VSS
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
85
MB90570 Series
(3) Clock Timings
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Typ. Max.
FC
X0, X1
3
—
16
MHz
Clock frequency
FCL
X0A, X1A
—
32.768
—
kHz
tHCYL
X0, X1
62.5
—
333
ns
Clock cycle time
tLCYL
X0A, X1A
—
30.5
—
µs
Recommend
PWH,
X0
10
—
—
ns duty ratio of
PWL
30% to 70%
Input clock pulse width
PWLH,
X0A
—
15.2
—
µs
PWLL
tCR,
External clock
Input clock rising/falling time
X0, X0A
—
—
5
ns
—
tCF
operation
Main clock
—
1.5
—
16
MHz
fCP
operation
Internal operating clock
frequency
Subclock
—
—
8.192
—
kHz
fLCP
operation
External clock
tCP
—
62.5
—
333
ns
operation
Internal operating clock cycle
time
Subclock
—
—
122.1
—
µs
tLCP
operation
Frequency fluctuation rate
∆f
—
—
—
5
% *
locked
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+α
∆f = | α | × 100 (%)
fO
Center frequency fO
–α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
86
MB90570 Series
• X0, X1 clock timing
tHCYL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
X0
PWH
0.2 VCC
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
X0A
PWLH
0.2 VCC
PWLL
tCF
tCR
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
Operation guarantee range (MB90F574/A)
(V)
Power supply voltage VCC
Operation guarantee range MB90574C
5.5
4.5
PLL operation
guarantee range
Operation guarantee range
MB90V570/A
3.3
3.0
Operation guarantee range
MB90573/4
1.5
3
8
12
Internal clock fCP
16
(MHz)
Relationship between oscillating frequency, internal
operating clock frequency, and power supply voltage
(MHz)
Multipliedby-4
16
MultipliedMultiplied-by-2
by-3
Multiplied-by-1
Internal clock fCP
12
9
8
Not multiplied
6
4
3
2
1.5
3
4
6
8
12
16
(MHz)
Oscillation clock FC
87
MB90570 Series
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hystheresis input pin
Hystheresis input pin
0.8 VCC
2.4 VCC
0.2 VCC
0.8 VCC
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
(4) Recommended Resonator Manufacturers
• Sample application of ceramic resonator
X0
X1
R
*
C1
C2
• Mask ROM product (MB90574)
Resonator
Resonator
manufacturer*
CSA2.00MG040
CSA4.00MG040
Murata Mfg. Co., Ltd. CSA8.00MTZ
CSA16.00MXZ040
CSA32.00MXZ040
CCR3.52MC3 to
CCR6.96MC3
CCR7.0MC5 to
TDK Corporation
CCR12.0MC5
CCR20.0MSC6 to
CCR32.0MSC6
Frequency (MHz)
C1 (pF)
C1 (pF)
R
2.00
4.00
8.00
16.00
32.00
100
100
30
15
5
100
100
30
15
5
No required
No required
No required
No required
No required
3.52 to 6.96
Built-in
Built-in
No required
7.00 to 12.00
Built-in
Built-in
No required
20.00 to 32.00
Built-in
Built-in
No required
(Continued)
88
MB90570 Series
(Continued)
• Flash product (MB90F574)
Resonator
Resonator
manufacturer*
CSA2.00MG040
CSA4.00MG040
Murata Mfg. Co., Ltd. CSA8.00MTZ
CSA16.00MXZ040
CSA32.00MXZ040
CCR3.52MC3 to
CCR6.96MC3
CCR7.0MC5 to
TDK Corporation
CCR12.0MC5
CCR20.0MSC6 to
CCR32.0MSC6
Frequency (MHz)
C1 (pF)
C2 (pF)
R
2.00
4.00
8.00
16.00
32.00
100
100
30
15
5
100
100
30
15
5
No required
No required
No required
No required
No required
3.52 to 6.96
Built-in
Built-in
No required
7.00 to 12.00
Built-in
Built-in
No required
20.00 to 32.00
Built-in
Built-in
No required
Inquiry: Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.): TEL 65-758-4233
TDK Corporation
• TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
• TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
• TDK Singapore (PTE) Ltd.: TEL 65-273-5022
• TDK Hongkong Co., Ltd.: TEL: 852-736-2238
• Korea Branch, TDK Corporation: TEL 82-2-554-6636
(5) Clock Output Timing
Parameter
Cycle time
CLK ↑ → CLK ↓
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
tCYC
CLK
62.5
—
ns
—
tCHCL
CLK
20
—
ns
tCYC
tCHCL
2.4 V
CLK
2.4 V
0.8 V
89
MB90570 Series
(6) Bus Read Timing
Parameter
Symbol
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Pin name
Condition
Min.
Max.
ALE pulse width
tLHLL
ALE
1 tCP*/2 – 20
—
ns
Effective address →
ALE ↓ time
tAVLL
ALE,
A23 to A16,
AD15 to AD00
1 tCP*/2 – 20
—
ns
ALE ↓ → address
effective time
tLLAX
ALE,
AD15 to AD00
1 tCP*/2 – 15
—
ns
Effective address →
RD ↓ time
tAVRL
RD,
A23 to A16,
AD15 to AD00
1 tCP* – 15
—
ns
Effective address →
valid data input
tAVDV
A23 to A16,
AD15 to AD00
—
RD pulse width
tRLRH
RD
RD ↓ → valid data input tRLDV
RD,
AD15 to AD00
RD ↑ → data hold time
tRHDX
RD,
AD15 to AD00
RD ↑ → ALE ↑ time
tRHLH
RD ↑ → address
effective time
3 tCP*/2 – 20
—
ns
—
—
3 tCP*/2 – 60 ns
0
—
ns
ALE, RD
1 tCP*/2 – 15
—
ns
tRHAX
ALE,
A23 to A16
1 tCP*/2 – 10
—
ns
Effective address →
CLK ↑ time
tAVCH
CLK,
A23 to A16,
AD15 to AD00
1 tCP*/2 – 20
—
ns
RD ↓ → CLK ↑ time
tRLCH
CLK, RD
1 tCP*/2 – 20
—
ns
ALE ↓ → RD ↓ time
tALRL
ALE, RD
1 tCP*/2 – 15
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
90
5 tCP*/2 – 60 ns
MB90570 Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
2.4 V
0.8 V
2.4 V
tLHLL
tAVLL
ALE
2.4 V
tLLAX
tRLRH
RD
2.4 V
0.8 V
tAVRL
tRHAX
tRLDV
2.4 V
0.8 V
AD23 to AD16
2.4 V
0.8 V
tAVDV
AD15 to AD00
2.4 V
0.8 V
Address
2.4 V
0.8 V
0.8 VCC
0.2 VCC
Read data
tRHDX
0.8 VCC
0.2 VCC
91
MB90570 Series
(7) Bus Write Timing
Parameter
Symbol
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Pin name
Condition
Min.
Max.
Effective address →
WR ↓ time
tAVWL
WRL, WRH,
A23 to A16,
AD15 to AD00
WR pulse width
tWLWH
1 tCP – 15
—
ns
WRL, WRH
3 tCP*/2 – 20
—
ns
Write data → WR ↑ time tDVWH
WRL, WRH,
AD15 to AD00
3 tCP*/2 – 20
—
ns
WR ↑ → data hold time
tWHDX
WRL, WRH,
AD15 to AD00
20
—
ns
WR ↑ → address
effective time
tWHAX
WRL, WRH,
A23 to A16
1 tCP*/2 – 10
—
ns
WR ↑ → ALE ↑ time
tWHLH
ALE, WRL
1 tCP*/2 – 15
—
ns
WR ↓ → CLK ↑ time
tWLCH
CLK, WRH
1 tCP*/2 – 20
—
ns
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
WRL, WRH
2.4 V
0.8 V
tWHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
0.8 V
92
Address
2.4 V
0.8 V
tWHDX
2.4 V
Write data
0.8 V
MB90570 Series
(8) Ready Input Timing
Parameter
RDY setup time
RDY hold time
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
tRYHS
RDY
45
—
ns
—
RDY
0
—
ns
tRYHH
Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
2.4 V
2.4 V
CLK
ALE
RD/WRL, RD/WRH
tRYHS
RDY
(wait inserted)
0.2 VCC
RDY
(wait not inserted)
0.8 VCC
tRYHS
0.2 VCC
0.8 VCC
tRYHH
(9) Hold Timing
Parameter
Symbol
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Pins in floating status →
tXHAL
HAK ↓ time
HAK
HAK ↑ → pin valid time
HAK
tHAHV
—
30
1 tCP*
ns
1 tCP*
2 tCP*
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK
2.4 V
0.8 V
tXHAL
Pins
2.4 V
0.8 V
tHAHV
High impedance
2.4 V
0.8 V
93
MB90570 Series
(10) UART0 (SCI), UART1 (SCI) Timing
Parameter
Serial clock cycle time
SCK ↓ → SOT delay
time
Valid SIN → SCK ↑
SCK ↑ → valid SIN
hold time
Serial clock “H” pulse
width
Serial clock “L” pulse
width
SCK ↓ → SOT delay
time
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
tSCYC
8 tCP*
SCK0 to SCK4
—
ns
SCK0 to SCK4, Internal shift clock
– 80
80
ns
tSLOV
SOT0 to SOT4 mode
SCK0 to SCK4, CL = 80 pF
tIVSH
100
—
ns
+ 1 TTL for an
SIN0 to SIN4
SCK0 to SCK4, output pin
60
—
ns
tSHIX
SIN0 to SIN4
tSHSL
SCK0 to SCK4
4 tCP*
—
ns
tSLSH
SCK0 to SCK4 External shift
clock mode
SCK0 to SCK4,
CL = 80 pF
SOT0 to SOT4
+ 1 TTL for an
SCK0 to SCK4, output pin
SIN0 to SIN4
SCK0 to SCK4,
SIN0 to SIN4
4 tCP*
—
ns
—
150
ns
60
—
ns
60
—
ns
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN
hold time
tSHIX
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes: • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
94
MB90570 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK4
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT0 to SOT4
0.2 V
tIVSH
SIN0 to SIN4
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK0 to SCK4
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
SOT0 to SOT4
2.4 V
0.8 V
tIVSH
SIN0 to SIN4
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
95
MB90570 Series
(11) Timer Input Timing
Parameter
Input pulse width
Symbol
tTIWH,
tTIWL
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
IN0, IN1
—
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
IN0, IN1
tTIWH
tTIWL
(12) Timer Output Timing
Parameter
CLK ↑ → TOUT
transition time
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
OUT0 to OUT3,
tTO
—
30
—
ns
PPG0, PPG1
2.4 V
CLK
tTO
TOUT
96
2.4 V
0.8 V
MB90570 Series
(13) Trigger Input Timing
Parameter
Input pulse width
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
IRQ0 to IRQ5,
—
5 tCP*
tTRGL
—
ns
ADTG, IN0, IN1
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
IRQ0 to IRQ5
ADTG, IN0, IN1
tTRGH
0.2 VCC
tTRGL
97
MB90570 Series
(14) Chip Select Output Timing
Parameter
Symbol
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Pin name
Condition
Min.
Max.
Valid chip select output
→ Valid data input time
tSVDV
CS0 to CS7,
AD15 to AD00
RD ↑ → chip select
output effective time
tRHSV
RD,
CS0 to CS7
WR ↑ → chip select
output effective time
tWHSV
CS0 to CS7,
WRL, WRH
Valid chip select output
→ CLK ↑ time
tSVCH
CLK,
CS0 to CS7
—
5 tCP*/2 – 60 ns
1 tCP*/2 – 10
—
ns
1 tCP*/2 – 10
—
ns
1 tCP*/2 – 20
—
ns
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tSVCH
CLK
2.4 V
RD
2.4 V
tRHSV
A23 to A16
CS0 to CS7
2.4 V
0.8 V
tSVDV
AD15 to AD00
2.4 V
0.8 V
Read data
tWHSV
WRL, WRH
2.4 V
AD15 to AD00
98
Write data
MB90570 Series
(15) I2C Timing
Parameter
Symbol
Internal clock cycle time tCP
Start condition output
tSTAO
Stop condition output
tSTOO
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name Condition
Unit
Remarks
Min.
Max.
—
62.5
666
tCP×m×n/2-20 tCP×m×n/2+20
ns All products
ns
Only as master
tCP(m×n/
2+4)-20
tCP(m×n/
2+4)+20
ns
Start condition detection tSTAI
3tCP+40
—
ns
Stop condition detection tSTOI
3tCP+40
—
ns
SDA,SCL
Only as slave
SCL output “L” width
tCP×m×n/2-20 tCP×m×n/2+20
tLOWO
SCL
SCL output “H” width
tHIGHO
SDA output delay time
tDOO
—
ns
Only as master
tCP(m×n/
2+4)-20
tCP(m×n/
2+4)+20
ns
2tCP-20
2tCP+20
ns
4tCP-20
—
ns
3tCP+40
—
ns
tCP+40
—
ns
40
—
ns
0
—
ns
SDA,SCL
Setup after SDA output
interrupt period
tDOSUO
SCL input “L” width
tLOWI
SCL
SCL input “H” width
tHIGHI
SDA input setup time
tSUI
SDA,SCL
SDA input hold time
tHOI
Notes: • “m” and “n” in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
• The SDA and SCL output values indicate that rise time is 0 ns.
99
MB90570 Series
• I2C interface [data transmitter (master/slave)]
tLOWO
tHIGHO
0.8 VCC
SCL
0.8 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
1
tSTAO
0.8 VCC
8
tDOO
9
tDOO
tSUI
SDA
tHOI
tDOSUO
ACK
• I2C interface [data receiver (master/slave)]
tHIGHI
0.8 VCC
SCL
tLOWI
0.8 VCC
0.8 VCC
0.2 VCC
6
7
tSUI
SDA
100
tHOI
0.2 VCC
8
0.2 VCC
0.2 VCC
9
tSTOI
tDOO
tDOO
ACK
tDOSUO
MB90570 Series
(16) Pulse Width on External Interrupt Pin at Return from STOP Mode
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Input pulse width
Symbol
tIRQWH
tIRQWL
Pin name
Condition
IRQ2 to IRQ7

Value
Min.
Max.
6tCP

Unit
Remarks
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.80.8
VCCVCC
0.80.8
VCCVCC
0.20.2
VCCVCC
IRQ2
IRQ2
∼ IRQ7
∼ IRQ7
tIRQWH
tIRQWH
0.20.2
VCCVCC
tIRQWL
tIRQWL
101
MB90570 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Parameter
Min.
Typ.
Max.
Resolution
—
—
—
8/10
—
bit
Total error
—
—
—
—
±5.0
LSB
Non-linear error
—
—
—
—
±2.5
LSB
Differential
—
—
—
—
±1.9
LSB
linearity error
—
Zero transition
AN0 to
VOT
–3.5 LSB +0.5 LSB +4.5 LSB mV
voltage
AN7
Full-scale
AN0 to
AVRH
AVRH
AVRH
mV
transition
VFST
AN7
–6.5 LSB –1.5 LSB +1.5 LSB
voltage
VCC = 5.0 V ±10%
352tCP
Conversion time
—
—
—
—
µs
at machine clock of 16 MHz
VCC = 5.0 V ±10% at
64tCP
Sampling period
—
—
—
—
µs
machine clock of 6 MHz
AN0 to
Analog port
—
—
10
µA
IAIN
AN7
input current
Analog input
AN0 to
VAIN
AVRL
—
AVRH
V
voltage
AN7
AVRL
—
—
AVCC
—
AVRH
V
+2.7
Reference
voltage
AVRH
—
AVRL
0
—
V
–2.7
AVCC
—
5
—
mA
IA
CPU
stopped
and
8/10-bit
Power supply
A/D converter not in
current
—
—
5
µA
AVCC
IAH
operation
(VCC = AVCC = AVRH = 5.0 V)
IR
AVRH
—
—
400
—
µA
Reference
CPU stopped and 8/10-bit
voltage supply
A/D converter not in
—
—
5
µA
AVRH
IRH
current
operation
(VCC = AVCC = AVRH = 5.0 V)
Offset between
AN0 to
—
—
—
—
4
LSB
channels
AN7
102
MB90570 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB
Actual conversion
value
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH – AVRL
1024
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
Analog input
[V]
AVRH
Total error for digital output N =
VNT – {1 LSB × (N – 1) + 0.5 LSB}
[LSB]
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
(Continued)
103
MB90570 Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
Actual conversion
value
{1 LSB × (N – 1)+ VOT}
3FE
N+1
Actual conversion value
VFST
(measured value)
Digital output
Digital output
3FD
VNT
004
Actual conversion
characteristics
003
N
N–1
V(N + 1)T
(measured value)
N–2
VNT (measured
002
Theoretical
characteristics
001
Actual conversion
value
VOT (measured value)
AVRL
Analog input
AVRH
AVRL
Analog input
AVRH
VNT – {1 LSB × (N – 1) + VOT}
Linearity error of
[LSB]
digital output N =
1 LSB
Differential linearity error
=
of digital N
1 LSB =
V(N + 1)T – VNT
– 1 LSB [LSB]
1 LSB
VFST – VOT
[V]
1022
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 7 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
C0
Analog input
Comparator
C1
MB90573/4, MB90V570/A
MB90F574/A
MB90574C
Note: Listed values must be considered as standards.
• Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
104
R ≅ 1.5 kΩ, C ≅ 30 pF
R ≅ 3.0 kΩ, C ≅ 65 pF
MB90570 Series
8. D/A Converter Electrical Characteristics
Parameter
(AVCC = VCC = DVCC = 5.0 V ±10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Symbol
Pin name
Min.
Typ.
Max.
Resolution
—
—
—
8
—
bit
Differential linearity
error
—
—
—
—
±0.9
LSB
Absolute accuracy
—
—
—
—
±1.2
%
Linearity error
—
—
—
—
±1.5
LSB
Conversion time
—
—
—
10
20
Analog reference
voltage
—
DVCC
VSS + 3.0
—
AVCC
V
IDVR
DVCC
—
120
300
µA
IDVRS
DVCC
—
—
10
µA In sleep mode
—
20
—
kΩ
Reference voltage
supply current
Analog output
impedance
—
—
µs Load capacitance: 20 pF
Conversion under
no load
105
MB90570 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90574)
ICC - VCC
ICC (mA)
35
ICCS - VCC
ICCS (mA)
10
TA = +25°C
TA = +25°C
9
30
Fc = 16 MHz
25
Fc = 12.5 MHz
8
Fc = 16 MHz
7
Fc = 12.5 MHz
6
20
Fc = 10 MHz
15
Fc = 8 MHz
10
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
5
5
Fc = 10 MHz
4
Fc = 8 MHz
3
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
2
1
3.0
4.0
5.0
ICC - TA
ICC (mA)
35
3.0
6.0
VCC (V)
5.0
6.0
VCC (V)
ICCS - TA
ICCS (mA)
10
VCC = 5.0 V
4.0
VCC = 5.0 V
9
30
Fc = 16 MHz
8
Fc = 12.5 MHz
7
25
20
Fc = 10 MHz
Fc = 16 MHz
Fc = 12.5 MHz
6
Fc = 10 MHz
5
15
Fc = 8 MHz
10
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
5
Fc = 8 MHz
4
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
3
2
1
–20
+10
+40
+70
+100
TA (°C)
ICCLS (mA)
70
ICCL - VCC
ICCL (µA)
160
–20
+10
+40
+70
+100
TA (°C)
ICCLS - VCC
TA = +25°C
TA = +25°C
60
140
Fc = 8 kHz
120
100
50
Fc = 8 kHz
40
80
30
60
20
40
10
20
3.0
106
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
MB90570 Series
ICC - Fc
ICC (mA)
35
ICCS - Fc
ICCS (mA)
10
TA = +25°C
30
25
20
15
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
9
7
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
6
VCC = 3.0 V
VCC = 2.5 V
5
VCC = 2.5 V
TA = +25°C
8
4
3
10
2
5
1
4.0
6.0
8.0
ICCT - VCC
ICCT (µA)
20
4.0
12.0 16.0
Fc (MHz)
TA = +25°C
9
16
8
14
Fc = 8 kHz
6
10
5
8
4
6
3
4
2
2
1
4.0
5.0
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
8
7
6
5
4
7
6
5
4
3
2
1
1
+70
+100
TA (°C)
6.0
VCC (V)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
8
2
+40
5.0
9
3
+10
4.0
ICCLH - TA
ICCLH (µA)
10
9
–20
TA = +25°C
3.0
6.0
VCC (V)
ICCT - TA
ICCT (µA)
10
12.0 16.0
Fc (MHz)
7
12
3.0
8.0
ICCH - VCC
ICCH (µA)
10
18
6.0
–20
+10
+40
+70
+100
TA (°C)
107
MB90570 Series
ICCL - TA
ICCL (µA)
20
ICCLS - TA
ICCLS (µA)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
18
16
14
12
10
14
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
12
10
8
8
6
6
4
4
2
2
–20
+10
+40
+70
–20
+100
TA (°C)
+10
+40
+70
+100
TA (°C)
(2) Power Supply Current (MB90F574)
ICCS - VCC
ICC - VCC
ICCS (mA)
ICC (mA)
140
40
TA = +25°C
TA = +25°C
Fc = 16 MHz
120
35
Fc = 12.5 MHz
100
Fc = 10 MHz
Fc = 8 MHz
80
60
Fc = 5 MHz
Fc = 4 MHz
40
Fc = 2 MHz
20
30
Fc = 16 MHz
25
Fc = 12.5 MHz
20
Fc = 10 MHz
Fc = 8 MHz
15
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
10
5
3.0
4.0
5.0
ICC - TA
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICCS - TA
ICC (mA)
120
ICCS (mA)
40
VCC = 5.0 V
VCC = 5.0 V
35
100
Fc = 16 MHz
30
Fc = 12.5 MHz
25
Fc = 10 MHz
Fc = 8 MHz
20
80
60
40
20
–20
108
+10
+40
+70
Fc = 16 MHz
Fc = 12.5 MHz
15
Fc = 5 MHz
Fc = 4 MHz
Fc = 10 MHz
10
Fc = 2 MHz
5
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
+100
TA (°C)
–20
+10
+40
+70
+100
TA (°C)
MB90570 Series
ICCLS - VCC
ICCLS (µA)
200
TA = +25°C
180
160
FC = 8 kHz
140
120
100
80
60
40
20
3.0
4.0
5.0
6.0
VCC (V)
ICCS - FC
ICC - FC
ICC (mA)
120
VCC = 6.0 V
TA = +25°C
ICCS (mA)
40
TA = +25°C
35
100
VCC = 5.5 V
80
VCC = 5.0 V
30
VCC = 6.0 V
VCC = 4.5 V
25
VCC = 5.5 V
60
VCC = 4.0 V
20
VCC = 5.0 V
40
VCC = 3.5 V
VCC = 3.0 V
15
20
VCC = 2.5 V
4.0
8.0
12.0
10
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
5
VCC = 2.5 V
4.0
16.0
FC (MHZ)
ICCT - VCC
ICCT (µA)
50
8.0
12.0
16.0
FC (MHZ)
ICCH -VCC
ICCH (µA)
10
9
TA = +25°C
40
TA = +25°C
8
FC = 8 kHZ
7
6
30
5
20
4
3
2
10
1
3
4
5
6
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
109
MB90570 Series
ICCT - TA
ICCT (µA)
10
ICCH - TA
ICCH (µA)
10
9
9
8
8
7
7
6
6
5
5
4
4
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
3
2
1
-20
+10
+40
3
2
1
+70 +100
TA (°C)
+10
-20
+40
ICCLS - TA
ICCLS (µA)
20
18
16
VCC = 6.0 V
14
VCC = 5.5 V
VCC = 5.0 V
12
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
10
8
6
4
2
-20
110
+10
+40
+70
+100
TA (°C)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
+70 +100
TA (°C)
MB90570 Series
(3)Power Supply Current (MB90574C)
ICC (mA)
70
ICC − VCC
TA = +25 °C
60
FC = 16 MHz
50
FC = 12 MHz
40
FC = 10 MHz
FC = 8 MHz
30
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
20
10
0
3.0
3.5
4.0
4.5
ICC (mA)
70
5.0
ICC − FC
5.5
6.0
VCC (V)
TA = +25 °C
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
60
50
40
30
20
10
0
2
ICCS (mA)
18
16
14
12
10
8
6
4
2
0
−50
4
6
8
10
ICCS − TA
12
14 16
FC (MHz)
VCC = 5 V
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 4 MHz
FC = 2 MHz
−20
10
40
70
100
TA (°C)
ICC (mA)
50
45
40
35
30
25
20
15
10
5
0
−50
ICC − TA
VCC = 5.0 V
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
−20
ICCS (mA)
18
16
14
10
40
70
100
TA (°C)
ICCS − VCC
TA = +25 °C
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
12
10
8
FC = 8 MHz
FC = 5 MHz
6
FC = 4 MHz
4
FC = 2 MHz
2
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCS (mA)
18
16
14
12
10
8
6
4
2
0
2
ICCS − FC
TA = +25 °C
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
4
6
8
10
12
14
16
FC (MHz)
111
MB90570 Series
ICCH (µA)
ICCH − VCC
TA = +25 °C
10
9
8
7
6
5
4
3
2
1
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCH − TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
10
40
70
ICCT (µA)
ICCT − VCC
TA = +25 °C
10
9
8
7
6
5
4
3
2
1
FC = 8 kHz
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCT (µA)
10
9
8
7
6
5
4
3
2
1
0
−50
−20
ICCT − TA
ICCL (µA)
70
ICCL (µA)
70
ICCL − TA
ICCL − VCC
TA = +25 °C
60
60
50
50
40
40
30
FC = 8 kHz
100
TA (°C)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
10
40
70
20
10
10
0
−50
100
TA (°C)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
30
20
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
112
ICCH (µA)
10
9
8
7
6
5
4
3
2
1
0
−50
−20
−20
10
40
70
100
TA (°C)
MB90570 Series
ICCLS (µA)
25
ICCLS − VCC
TA = +25 °C
ICCLS (µA)
25
20
20
15
15
10
FC = 8 kHz
ICCLS − TA
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
10
5
5
0
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
0
−50
−20
10
40
70
100
TA (°C)
113
MB90570 Series
■ INSTRUCTIONS (351 INSTRUCTIONS)
Table 1
Item
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
Explanation of Items in Tables of Instructions
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction code.
Indicates the number of bytes.
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
• Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done × the number of cycles suspended as the corrective value to the number of
ordinary execution cycles.
114
MB90570 Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
Meaning
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
rlst
PC relative addressing
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
Register list
115
MB90570 Series
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
116
MB90570 Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register accesses
for each type of addressing
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Listed in tables of instructions
Listed in tables of instructions
Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
Operand
(b) byte
(c) word
(d) long
Cycles
Access
Cycles
Access
Cycles
Access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
117
MB90570 Series
Table 7
Mnemonic
#
Transfer Instructions (Byte) [41 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
3
2
4
3
2
1
2
2
2+ 3+ (a)
3
2
2
2
3
2
10
3
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A,@RWi+disp8
A, @RLi+disp8
3
2
4
3
2
2
2
2
2+ 3+ (a)
3
2
2
2
3
2
5
2
10
3
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
X *
X *
X *
X *
X *
X *
X *
X –
X *
X *
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
0
(b)
byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
4
2
2+ 5+ (a)
7
2
2+ 9+ (a)
2
0
4
2
0
2× (b)
0
2× (b)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
118
MB90570 Series
Table 8
Mnemonic
#
Transfer Instructions (Word/Long Word) [38 Instructions]
~
RG
B
2
3
3
4
1
1
1
2
2
2
2+ 3+ (a)
2
3
2
3
3
2
2
5
3
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8) –
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/MOVW@A, T
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
2
3
0
(c)
XCHW
XCHW
XCHW
XCHW
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
MOVL ear, A
MOVL eam, A
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
A, ear
A, eam
RWi, ear
RWi, eam
Operation
LH AH
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A) –
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
–
word (ear) ← imm16
–
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
2
0
0 2× (c)
4
0
2 2× (c)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
4
2+ 5+ (a)
5
3
2
0
0
0
(d)
0
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2
4
2+ 5+ (a)
2
0
0
(d)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
119
MB90570 Series
Table 9
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
#
~
RG
B
Operation
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
Z
Z
Z
Z
–
Z
Z
Z
Z
byte (A) ← (AH) + (AL) + (C) (decimal) Z
Z
byte (A) ← (A) –imm8
Z
byte (A) ← (A) – (dir)
Z
byte (A) ← (A) – (ear)
Z
byte (A) ← (A) – (eam)
–
byte (ear) ← (ear) – (A)
–
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C) Z
byte (A) ← (A) – (ear) – (C) Z
byte (A) ← (A) – (eam) – (C) Z
byte (A) ← (AH) – (AL) – (C) (decimal) Z
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2× (c)
0
(c)
0
0
(c)
0
0
2× (c)
0
(c)
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
A, ear
2
6
A, eam
2+ 7+ (a)
A, #imm32 5
4
A, ear
2
6
A, eam
2+ 7+ (a)
A, #imm32 5
4
2
0
0
2
0
0
0
(d)
0
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
120
MB90570 Series
Table 10
Mnemonic
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2
2+ 5+ (a)
2
0
0
byte (ear) ← (ear) +1
2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
3
2+ 5+ (a)
2
0
0
byte (ear) ← (ear) –1
2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
3
2+ 5+ (a)
2
0
0
word (ear) ← (ear) +1
2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
3
2+ 5+ (a)
2
0
0
word (ear) ← (ear) –1
2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
7
2+ 9+ (a)
4
0
0
long (ear) ← (ear) +1
2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
7
2+ 9+ (a)
4
0
0
long (ear) ← (ear) –1
2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
2
2+
2
1
2
3+ (a)
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
1
A, ear
2
A, eam
2+
A, #imm16 3
1
2
3+ (a)
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
2
A, eam
2+
A, #imm32 5
6
7+ (a)
3
2
0
0
0
(d)
0
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
121
MB90570 Series
Table 12
Mnemonic
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
1
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
*
*
–
DIVU
A, ear
2
*2
1
0 word (A)/byte (ear)
–
–
–
–
–
–
–
*
*
–
DIVU
A, eam 2+ *3
0
*6 word (A)/byte (eam)
–
–
–
–
–
–
–
*
*
–
*4
1
0 long (A)/word (ear)
–
–
–
–
–
–
–
*
*
–
DIVUW A, eam 2+ *5
0
*7 long (A)/word (eam)
–
–
–
–
–
–
–
*
*
–
MULU
MULU
MULU
0 0 byte (AH) *byte (AL) → word (A)
1 0 byte (A) *byte (ear) → word (A)
0 (b) byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0 0 word (AH) *word (AL) → long (A)
1 0 word (A) *word (ear) → long (A)
0 (c) word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DIVUW A, ear
2
A
1 *8
A, ear
2 *9
A, eam 2+ *10
MULUW A
1 *11
MULUW A, ear
2 *12
MULUW A, eam 2+ *13
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
Quotient → byte (AL) Remainder → byte (AH)
Quotient → byte (A) Remainder → byte (ear)
Quotient → byte (A) Remainder → byte (eam)
Quotient → word (A) Remainder → word (ear)
Quotient → word (A) Remainder → word (eam)
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
122
MB90570 Series
Table 13
Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
Mnemonic
#
~
RG
B
0
DIV
A
2
*1
0
DIV
A, ear
2
*2
1
DIV
A, eam 2 +
*3
0
DIVW
A, ear
2
*4
1
DIVW
A, eam
2+
*5
0
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
2
A, ear
2
A, eam 2 +
A
2
A, ear
2
A, eam 2 +
*8
*9
*10
*11
*12
*13
0
1
0
0
1
0
Operation
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
0
0
(b)
0
0
(c)
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
123
MB90570 Series
Table 14
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
2
3
2+ 5+ (a)
0
2
0
0
byte (A) ← not (A)
0
byte (ear) ← not (ear)
2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
0
2
0
0
word (A) ← not (A)
0
word (ear) ← not (ear)
2× (c) word (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
1
2
2
3
2+ 5+ (a)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
124
MB90570 Series
Table 15
Logical 2 Instructions (Long Word) [6 Instructions]
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
2+
6
7+ (a)
2
0
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
2+
6
7+ (a)
2
0
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ea
XORL A, eam
2
2+
6
7+ (a)
2
0
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
NEG
A
1
NEG
NEG
ear
eam
2
3
2+ 5+ (a)
2
0
NEGW A
1
0
NEGW ear
NEGW eam
2
3
2+ 5+ (a)
2
2
0
0
byte (ear) ← 0 – (ear)
2× (b) byte (eam) ← 0 – (eam)
0
word (A) ← 0 – (A)
0
word (ear) ← 0 – (ear)
2× (c) word (eam) ← 0 – (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17
Mnemonic
#
~
RG
B
NRML A, R0
2
*1
1
0
Normalize Instruction (Long Word) [1 Instruction]
Operation
LH
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
*
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
125
MB90570 Series
Table 18
Mnemonic
RORC A
ROLC A
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
#
~
RG
B
2
2
2
2
0
0
0
0
Operation
LH AH
I
S
T
N
Z
V
C
RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
– – –
– – –
*
*
*
*
–
–
*
*
–
–
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
2
0
0 2× (b)
2
0
0 2× (b)
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
–
–
–
–
–
–
– – * * *
– – * R *
– – – * *
–
–
–
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A,
R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0) –
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
RORC ear
RORC eam
ROLC ear
ROLC eam
ASR
LSR
LSL
A, R0
A, R0
A, R0
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
126
MB90570 Series
Table 19
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Branch 1 Instructions [31 Instructions]
RG
B
Operation
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
0
0
0
(c)
0
(d)
0
CALL
CALL
CALL
CALLV
CALLP
2
@ear *4
@eam *4 2+
addr16 *5 3
1
#vct4 *5
2
@ear *6
6
7+ (a)
6
7
10
1
0
0
0
2
(c)
2× (c)
(c)
2× (c)
2× (c)
CALLP @eam *6
2+ 11+ (a)
0
*2
CALLP addr24 *7
4
0
2× (c)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
10
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
4 when branching, 3 when not branching.
(b) + 3 × (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
127
MB90570 Series
Table 20
Mnemonic
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
ear, #imm8, rel
eam, #imm8, rel*
10
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
Branch 2 Instructions [19 Instructions]
#
~
RG
B
Operation
3
4
1
*
*1
0
0
0
0
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
4
4+
5
5+
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
*5
2
0
DBNZ
ear, rel
3
DBNZ
eam, rel
3+ *6
N
Z
V
C
RMW
–
–
– – – – *
– – – – *
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2 2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
–
– – – – *
*
* –
–
–
– – – – *
*
* –
*
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
–
– – – – *
*
* –
–
–
– – – – *
*
* –
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
– – – – – – – –
–
–
– – – – – – – –
–
Return from subroutine
Return from subroutine
–
–
– – – – – – – –
– – – – – – – –
–
–
DWBNZ ear, rel
3
*5
2
DWBNZ eam, rel
3+ *6
2
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
*7
LINK
#imm8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *8
RETP *9
1
1
4
6
0
0
(c)
(d)
0
LH AH
I
–
–
–
–
R
R
R
R
*
S
–
–
–
–
S
S
S
S
*
T
–
–
–
–
–
–
–
–
*
–
–
–
–
*
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.
*8: Retrieve (word) from stack
*9: Retrieve (long word) from stack
*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
128
MB90570 Series
Table 21
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
#
~
RG
B
Operation
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
JCTX
@A
1
14
0
AND CCR, #imm8
OR CCR, #imm8
2
2
3
3
0
0
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
LH AH
I
S
T
N
Z
V
C
RMW
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
–
– – – – – – –
– – – – – – –
* * * * * * *
– – – – – – –
–
–
–
–
–
–
*
*
*
*
*
*
*
–
0
0
byte (CCR) ← (CCR) and imm8 –
–
byte (CCR) ← (CCR) or imm8
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOVEA RWi, ear
2
3
MOVEA RWi, eam 2+ 2+ (a)
MOVEA A, ear
2
1
MOVEA A, eam
2+ 1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z *
– –
– – –
– – –
*
*
*
*
– –
– –
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
6× (c) Context switch instruction
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
129
MB90570 Series
Table 22
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0
0
0
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
BBS
BBS
BBS
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS addr16:bp, rel
5
*3
0
2× (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*4
0
*5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*4
0
*5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
*5:
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 23
Mnemonic
SWAP
SWAPW/XCHW A,T
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) 0 to 7 ↔ (A) 8 to 15
word (AH) ↔ (AL)
byte sign extension
word sign extension
byte zero extension
word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
130
MB90570 Series
Table 24
Mnemonic
#
~
RG
B
MOVS/MOVSI
MOVSD
2
2
2
*
*2
5
*
*5
3
*
*3
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
FISL/FILSI
2 6m +6 *5
String Instructions [10 Instructions]
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*4
*4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*3
Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI 2
MOVSWD
2
*2
*2
*8
*8
*6
*6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
SCWEQD
2
2
*1
*1
*8
*8
*7
*7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2 6m +6 *8
*6
Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) × n
*8: 2 × (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
131
MB90570 Series
■ ORDERING INFORMATION
Part number
132
Package
MB90573PFF
MB90574PFF
MB90F574PFF
MB90F574APFF
120-pin Plastic LQFP
(FPT-120P-M05)
MB90573PFV
MB90574PFV
MB90574CPFV
MB90F574PFV
MB90F574APFV
120-pin Plastic QFP
(FPT-120P-M13)
MB90574CPMT
MB90F574APMT
120-pin Plastic LQFP
(FPT-120P-M21)
Remarks
MB90570 Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
(FPT-120P-M05)
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8°
LEAD No.
1
30
0.16±0.03
(.006±.001)
0.40(.016)
0.07(.003)
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
0.145±0.055
(.006±.002)
M
0.45/0.75
(.018/.030)
C
Dimensions in mm (inches)
1998 FUJITSU LIMITED F120006S-3C-4
120-pin plastic QFP
(FPT-120P-M13)
22.60±0.20(.890±.008)SQ
3.85(.152)MAX
(Mounting height)
20.00±0.10(.787±.004)SQ
90
0.25(.010)
0.05(.002)MIN
(STAND OFF)
61
91
60
14.50
(.571)
REF
21.60
(.850)
NOM
Details of "A" part
0.15(.006)
0.15(.006)
INDEX
0.15(.006)MAX
0.40(.016)MAX
"A"
120
LEAD No.
1
31
Details of "B" part
30
0.50(.0197)
0.20±0.10
(.008±.004)
0.08(.003)
M
0.125±0.05
(.005±.002)
0
10°
0.50±0.20(.020±.008)
0.10(.004)
C
2000 FUJITSU LIMITED F120013S-2C-4
"B"
Dimensions in mm (inches)
133
MB90570 Series
120-pin plastic LQFP
(FPT-120P-M21)
18.00±0.20(.709±.008)SQ
16.00±0.10(.630±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
LEAD No.
1
0~8°
"A"
31
30
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.45/0.75
(.018/.030)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches)
C
134
1998 FUJITSU LIMITED F120033S-2C-2
MB90570 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
 FUJITSU LIMITED Printed in Japan
136
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.