LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Wide Input Synchronous Boost Controller with Disconnection Switch Control Check for Samples: LM5121/LM5121-Q1 FEATURES 1 • • • • • • • • • • • • • • • • • • 2 • • • • • • • Available in AEC-Q100 (TJ = –40ºC to 125ºC) Maximum Input Voltage: 65 V Min Input Voltage: 3.0 V (4.5 V for startup) Output Voltage up to 100 V Bypass (VOUT = VIN) Operation 1.2 V Reference with ±1.0% Accuracy Free-Run/Synchronizable up to 1 MHz Peak Current Mode Control Robust Integrated 3 A Gate Drivers Adaptive Dead-Time Control Optional Diode Emulation Mode Programmable Cycle-by-Cycle Current Limit Programmable Line UVLO Programmable Soft-Start Thermal Shutdown Protection Low Shutdown Quiescent Current: 9 μA Programmable Slope Compensation Programmable Skip Cycle Mode Reduces Standby Power Supports External VCC Bias Supply Option Load Disconnection in Shutdown Mode (True Shutdown) Inrush Current Limiting Hiccup Mode Short Circuit / Overload Protection Circuit Breaker Function Capable of Input Transient Suppression Capable of Reverse Battery Protection • Thermally Enhanced 20-Pin HTSSOP Package APPLICATIONS • • • • 12 V, 24 V, and 48 V Power Systems Automotive Start-Stop High Current Boost Power Supply Battery Powered System DESCRIPTION The LM5121 is a synchronous boost controller intended for high-efficiency, high power boost regulator applications. The control method is based upon peak current mode control. Current mode control provides inherent line feed-forward, cycle-bycycle current limiting and ease of loop compensation. The switching frequency is programmable up to 1 MHz. Higher efficiency is achieved using two robust N-channel MOSFET gate drivers with adaptive deadtime control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions. The LM5121 provides disconnection switch control which completely disconnects the output from the input during an output short or a shutdown condition. During start-up sequence, inrush current is limited by the disconnection switch control. An internal charge pump allows 100% duty cycle operation of the high-side synchronous switch (Bypass operation). Additional features include thermal shutdown, frequency synchronization, hiccup mode current limit and adjustable line undervoltage lockout. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com SIMPLIFIED APPLICATION DIAGRAM VIN VOUT + VCC DS BST DG CSN CSP VIN UVLO SLOPE SYNCIN/RT LM5121 SW LO HO COMP FB RES SS MODE PGND AGND This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted) VALUE Input Output (3) ESD Rating Thermal (1) (2) (3) MIN MAX VIN, CSP, CSN –0.3 75 BST to SW, FB, MODE, UVLO, VCC (2) –0.3 15 SW –5.0 105 BST –0.3 115 SS, SLOPE, SYNCIN/RT –0.3 7 CSP to CSN, PGND –0.3 0.3 DG to DS –3.0 18 DG to VIN –75 15 DS –3.0 75 HO to SW –0.3 BST to SW+0.3 LO –0.3 VCC+0.3 COMP, RES –0.3 7 Human-Body Model (HBM) JESD22-A114 2 Charged-Device Model (CDM) JESD22-C101 1 Storage Temperature –55 150 Junction Temperature –40 150 UNIT V kV ºC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to AGND pin. See Application Information when input supply voltage is less than the VCC voltage. All output pins are not specified to have an external voltage applied. THERMAL CHARACTERISTICS THERMAL METRIC UNIT θJA Junction-to-ambient thermal resistance (Typ.) 40 θJC Junction-to-case thermal resistance (Typ.) 4 ºC/W RECOMMENDED OPERATING CONDITIONS (1) Over operating free-air temperature range (unless otherwise noted) Input supply voltage (2) MIN MAX VIN 4.5 65 Disconnection switch voltage (2) DG, DS 3.0 65 Low-side driver bias voltage VCC High-side driver bias voltage BST to SW 3.8 Current sense common mode range (2) CSP, CSN 3.0 Switch node voltage SW Junction temperature TJ (1) (2) UNIT 14 14 V 65 100 –40 125 ºC Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not guarantee specific performance limits. Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN voltage is supplied from an available external source. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 3 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VUVLO = 0 V 9 17 µA VUVLO = 2 V, non-switching 4 5 mA 7.6 8.3 VIN SUPPLY ISHUTDOWN VIN shutdown current IBIAS VIN operating current (exclude the current into RT resistor) VCC REGULATOR VCC(REG) VCC regulation No load VVIN = 4.5 V, no external load VCC dropout (VIN to VCC) IVCC 6.9 0.25 VVIN = 4.5 V, IVCC = 25 mA 0.28 VCC sourcing current limit VVCC = 0 V VCC operating current (exclude the current into RT resistor) VVCC = 8.3 V 3.5 5 VVCC = 12 V 4.5 8 4.0 4.1 VCC undervoltage threshold VCC rising, VVIN = 4.5 V 50 3.9 62 VCC falling, VVIN = 4.5 V VCC undervoltage hysteresis V 0.5 mA 3.7 V 1.23 V µA 0.385 UNDERVOLTAGE LOCKOUT UVLO threshold UVLO rising UVLO hysteresis current VUVLO = 1.4 V UVLO standby threshold UVLO rising 1.17 1.20 7 10 13 0.3 0.4 0.5 0.1 0.125 1.24 1.28 UVLO standby hysteresis V MODE Diode emulation mode threshold MODE rising 1.20 Diode emulation mode hysteresis 0.1 Default MODE voltage Default skip cycle threshold Skip cycle hysteresis 145 155 COMP rising, measured at COMP 1.290 COMP falling, measured at COMP 1.245 Measured at COMP 170 V mV V 40 mV ERROR AMPLIFIER VREF FB reference voltage Measured at FB, VFB= VCOMP FB input bias current VFB= VREF VOH COMP output high voltage VOL COMP output low voltage AOL DC gain fBW Unity gain bandwidth 1.188 1.200 1.212 5 ISOURCE = 2 mA, VVCC = 4.5 V 2.75 ISOURCE = 2 mA, VVCC = 12 V 3.40 V nA V ISINK = 2 mA 0.25 80 dB 3 MHz OSCILLATOR fSW1 Switching frequency 1 RT = 20 kΩ 400 450 500 fSW2 Switching frequency 2 RT = 10 kΩ 775 875 975 RT output voltage kHz 1.2 RT sync rising threshold RT rising RT sync falling threshold RT falling Minimum sync pulse width 2.5 1.6 2.9 V 2.0 100 ns DISCONNECTION SWITCH CONTROL IDIS-SOURCE DG current source UVLO = 2 V, Sourcing 25 IDIS-SINK DG current sink Inrush Control, Sinking 67 DG discharge switch RDS-ON Circuit Breaker 38 4 Submit Documentation Feedback uA Ω Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS DG charge pump regulation DG to VIN, No load, VVIN = 4.5 V MIN TYP MAX 9.5 10.5 11.5 DG to VIN, No load, VVIN = 12 V VGS-DET VGS detection threshold DG to DS, Rising, VVIN = 12 V 12.5 4.0 VGS detection hysteresis 5.4 6.5 UNIT V 0.2 Transconductance gain CSP to CSN to IDG 12 uA/mV SLOPE COMPENSATION SLOPE output voltage VSLOPE Slope compensation amplitude 1.17 1.20 1.23 RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty cycle, TJ = –40ºC to +125ºC 1.375 1.650 1.925 RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty cycle, TJ = 25ºC 1.400 1.650 1.900 7.5 10 12 V SOFT-START ISS-SOURCE SS current source VSS = 0 V SS discharge switch RDS-ON µA Ω 13 PWM COMPARATOR tLO-OFF tON-MIN Forced LO off-time Minimum LO on-time COMP to PWM voltage drop VVCC = 5.5 V 420 550 VVCC = 4.5 V 360 500 RSLOPE = 20 kΩ 150 RSLOPE = 200 kΩ 300 TJ = –40ºC to +125ºC 0.95 1.10 1.25 TJ = 25ºC 1.00 1.10 1.20 CSP to CSN, TJ = –40ºC to +125ºC 65.5 75.0 87.5 CSP to CSN, TJ = 25ºC 67.0 75.0 86.0 80 110 133 143 160 170 11.5 16.0 ns V CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT VCS-TH1 Cycle-by-cycle current limit threshold VCS-TH2 –VCS-TH1 VCS-TH2 Inrush current limit threshold CSP to CSN VCS-TH3 Circuit breaker enable threshold CSP to CSN, Rising VCS-TH4 VCS-ZCD Circuit breaker disable threshold Zero cross detection threshold 5 VCS-TH3 – VCS-TH2 20 CSP to CSN, Falling 4.0 CSP to CSN, Rising CSP to CSN, Falling 7 0.3 6 Current sense amplifier gain 10 ICSP CSP input bias current 12 ICSN CSN input bias current 12 V/V 11 Bias current matching ICSP to ICSN CS to LO delay Current sense / current limit delay mV –1.75 1 µA 3.75 150 ns HICCUP MODE RESTART VRES VHCPUPPER VHCP- Restart threshold Hiccup counter upper threshold Hiccup counter lower threshold LOWER RES rising RES rising RES rising, VVIN = VVCC = 4.5 V 1.15 1.20 1.25 4.2 3.6 RES falling 2.15 RES falling, VVIN = VVCC = 4.5 V 1.85 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 V 5 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, these specifications apply for -40°C ≤ TJ ≤ +125°C, VVIN = 12 V, VVCC = 8.3 V, RT = 20 kΩ, no load on LO and HO. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER IRES- TEST CONDITIONS RES current source1 Fault-state charging current RES current sink1 Normal-state discharging current RES current source2 Hiccup mode off-time charging current RES current sink2 Hiccup mode off-time discharging current MIN TYP MAX 20 30 40 UNIT SOURCE1 IRES-SINK1 IRES- 5 µA 10 SOURCE2 IRES-SINK2 5 Hiccup cycle RES discharge switch RDS-ON Ratio of hiccup mode off-time to restart delay time 8 Cycles 40 Ω 122 HO GATE DRIVER VOHH HO high-state voltage drop IHO = –100 mA, VOHH = VBST – VHO VOLH HO low-state voltage drop IOHH 0.15 0.24 IHO = 100 mA, VOLH = VHO – VSW 0.1 0.18 HO rise time (10% to 90%) CLOAD = 4700 pF, VBST = 12 V 25 HO fall time (90% to 10%) CLOAD = 4700 pF, VBST = 12 V 20 VHO = 0 V, VSW = 0 V, VBST = 4.5 V 0.8 VHO = 0 V, VSW = 0 V, VBST = 7.6 V 1.9 VHO = VBST = 4.5 V 1.9 Peak HO source current IOLH Peak HO sink current IBST BST charge pump sourcing current BST charge pump regulation VHO = VBST = 7.6 V A 3.2 90 200 BST to SW, IBST= –70 μA, VVIN = VSW = 9.0 V 5.3 6.2 6.75 7 8.5 9 2.0 3.0 3.5 30 45 BST to SW undervoltage BST DC bias current ns VVIN = VSW = 9.0 V , VBST - VSW = 5.0 V BST to SW, IBST = –70 μA, VVIN = VSW = 12 V V VBST - VSW = 12 V, VSW = 0 V µA V µA LO GATE DRIVER VOHL LO high-state voltage drop ILO = –100 mA, VOHL = VVCC – VLO 0.15 0.25 VOLL LO low-state voltage drop ILO = 100 mA, VOLL = VLO 0.1 0.17 LO rise time (10% to 90%) CLOAD = 4700 pF 25 LO fall time (90% to 10%) CLOAD = 4700 pF 20 VLO = 0 V, VVCC = 4.5 V 0.8 VLO = 0 V 2.0 VLO = VVCC = 4.5 V 1.8 VLO = VVCC 3.2 IOHL Peak LO source current IOLL Peak LO sink current V ns A SWITCHING CHARACTERISTICS tDLH LO fall to HO rise delay No load, 50% to 50% 50 80 115 tDHL HO fall to LO rise delay No load, 50% to 50% 60 80 105 Thermal shutdown Temperature rising ns THERMAL TSD Thermal shutdown hysteresis 6 165 25 Submit Documentation Feedback ºC Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS 6.00 5.00 4.00 3.00 LO PEAK CURRENT [A] HO PEAK CURRENT [A] 5.00 SINK 2.00 SOURCE 1.00 4.00 SINK 3.00 SOURCE 2.00 1.00 VVIN = 12V VSW = 0V VVIN = 12V 0.00 0.00 4 5 6 7 8 9 10 11 12 13 VBST - VSW [V] 4 14 7 8 100 90.00 95 80.00 90 Dead-time [ns] 70.00 60.00 tDHL 50.00 40.00 tDLH VVIN = 12V VSW = 12V CLOAD=2600pF 1V to 1V 20.00 10.00 9 10 11 12 13 14 C001 Figure 2. LO Peak Current vs VVCC 100.00 Dead-time [ns] 6 VVCC [V] Figure 1. HO Peak Current vs VBST - VSW 30.00 5 C001 tDHL 85 80 75 70 tDLH 65 60 55 0.00 50 4 5 6 7 8 9 10 11 VVCC [V] 12 -50 -25 0 25 50 75 100 125 Temperature [C] C001 Figure 3. Dead Time vs VVCC 150 C001 Figure 4. Dead Time vs Temperature 100.0 20 90.0 15 70.0 tDHL ISHUTDOWN [PA] Dead-time [ns] 80.0 60.0 50.0 40.0 tDLH 30.0 VVIN = 12V VVCC = 7.6V CLOAD = 2600pF 1V to 1V 20.0 10.0 10 5 0.0 0 0 10 20 30 40 VSW [V] 50 60 -50 -25 Figure 5. Dead Time vs VSW 0 25 50 75 100 125 Temperature [C] C001 150 C001 Figure 6. ISHUTDOWN vs Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 7 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 8 8 No load 6 VVCC [V] VVCC [V] 6 4 4 2 2 0 0 No load 0 10 20 30 40 50 60 70 0 80 IVCC [mA] 1 2 3 4 5 6 7 Figure 7. VVCC vs IVCC 9 10 11 12 13 14 C001 Figure 8. VVCC vs VVIN 40 15 180 ACL=101, COMP unload ICSP 30 135 PHASE 20 90 10 45 0 10000 100000 FREQUENCY [Hz] 10 ICSN 5 0 GAIN -10 1000 ICSP, ICSN [PA] PHASE [°] GAIN [dB] 8 VVIN [V] C001 0 -45 10000000 1000000 -50 -25 0 25 50 75 100 125 Temperature [C] C002 Figure 9. Error Amp Gain and Phase vs Frequency 150 C001 Figure 10. ICSP, ICSN vs Temperature 15.0 300 280 BST Charging Current [PA] IBST = -70uA VBST-SW [V] 10.0 5.0 VVIN=VSW=9V 260 240 220 200 180 160 140 120 100 0.0 4 9 14 -50 19 VSW [V] -25 VCS-TH1, VCS-TH2, VCS-TH3 [mV] VCS-TH1, VCS-TH2, VCS-TH3 [mV] VCS-TH3 150 VCS-TH2 100 VCS-TH1 50 6 7 8 9 10 11 VVIN [V] 12 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 75 100 125 150 C001 VCS-TH3 VCS-TH2 VCS-TH1 ±50 ±25 C001 Figure 13. VCS-TH1, VCS-TH2, VCS-TH3 vs VVIN 8 50 Figure 12. IBST vs Temperature 200 5 25 Temperature [C] Figure 11. VBST-SW vs VSW 4 0 C001 0 25 50 75 Temperature [C] 100 125 150 C001 Figure 14. VCS-TH1 VCS-TH2, VCS-TH3 vs Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) 12 12 11 10 VDG-DS [V] 11 500 k No Load 8 VDG-DS [V] 9 7 6 5 250 k 10 4 3 9 2 VDS=12V 1 0 8 4 5 6 7 8 9 10 11 VVIN [V] 12 ±50 0 ±25 25 50 75 100 125 Temperature [C] C001 Figure 15. VDG-DS vs VVIN 150 C001 Figure 16. VDG-DS vs Temperature 12.00 11.00 10.00 VSW = 12V 9.00 VBST-SW [V] 8.00 7.00 6.00 5.00 VSW = 9V 4.00 3.00 VVIN = VSW IBST = -70uA 2.00 1.00 0.00 -50 -25 0 25 50 75 100 Temperature [C] 125 150 C001 Figure 17. VBST-SW vs Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 9 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com DEVICE INFORMATION HTSSOP-20 (TOP VIEW) DS 1 20 BST DG 2 19 HO CSN 3 18 SW CSP 4 17 VCC VIN 5 16 LO EP UVLO 6 15 PGND SS 7 14 RES SYNCIN/RT 8 13 MODE AGND 9 12 SLOPE FB 10 11 COMP PIN FUNCTIONS PIN 10 DESCRIPTION NO. AGND 9 G Analog ground connection. Return for the internal voltage reference and analog circuits. BST 20 P/I High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the highside N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation. COMP 11 O Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin. CSN 3 I Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor. CSP 4 I Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense resistor. DG 2 O Disconnection switch control pin. Connect to the gate terminal of the N-channel MOSFET disconnection switch. DS 1 I/O Source connection of N-channel MOSFET disconnection switch. Connect to the source terminal of the disconnection switch, the cathode terminal of the freewheeling diode and the supply input of boost inductor. EP EP N/A Exposed pad of the package. No internal electrical connections. Should be soldered to the large ground plane to reduce thermal resistance. FB 10 I Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. HO 19 O High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous N-channel MOSFET switch through a short, low inductance path. LO 16 O Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel MOSFET switch through a short, low inductance path. I Switching mode selection pin. Internal 700 kΩ pull-up and 100 kΩ pull-down resistor hold MODE pin to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2 V, diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side Nchannel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default condition when the MODE pin is left floating. If the MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load. MODE (1) I/O (1) NAME 13 G = Ground, I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 PIN I/O (1) DESCRIPTION NAME NO. PGND 15 G Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the source terminal of the low-side N-channel MOSFET switch. RES 14 O The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions and hiccup mode short circuit protection. Connect directly to the AGND when hiccup mode operation is not required. SLOPE 12 I Slope compensation is programmed by an external resistor between SLOPE and the AGND. SS 7 I Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp rate of the internal error amplifier reference during soft-start. SW 18 I/O Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET switch through short, low inductance paths. SYNCIN/RT 8 I The internal oscillator frequency is programmed by an external resistor between RT and the AGND. The internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this pin. The recommended maximum internal oscillator frequency is 2 MHz which leads to 1 MHz maximum switching frequency. UVLO 6 I Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external UVLO resistors to provide hysteresis. The UVLO pin should not be left floating. VCC 17 P/O/I VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible. VIN 5 P/I Supply voltage input source for the VCC regulator. Connect to the input capacitor and source power supply connection with short, low impedance paths. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 11 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN QD RS CIN CSP VIN 10µA DF DG Charge Pump STANDBY + 1.1V + UVLO RUV1 CS A=10 AMP 0.4V/0.3V + SHUTDOWN 9 VSLOPE = CHF COMP + + - - ZCD threshold + ERR + PWM Comparator 10µA SW COUT CLK S Q PWM LO Adaptive Timer QL R Q 1.2V RFB2 Skip Cycle Comparator 700k 20mV + MODE 100k VOUT CBST VCC + - SS Level Shift Diode Emulation C/L Comparator AMP CSS BST + - FB 1.2V CVCC DBST HO + 750mV CCOMP RCOMP BST Charge Pump QH VSENSE2 1.2 V VCC VCC Regulator Circuit Breaker Comparator VSENSE1 6 u 10 RSLOPE u FSW VIN + - 1.6V/0.11V SLOPE Generator AMP + Inrush Current Limiter SLOPE RSLOPE VIN 25µA 1.2V RUV2 LIN DS DG CSN 1.2V - + + Diode Emulation Comparator 30µA 40mV Hysteresis Diode Emulation LM5121 CLK 10µA Restart Timer RFB1 Clock Generator /SYNC Detector RES 5µA AGND SYNCIN/RT CRES PGND RT Functional Description The LM5121 wide input range synchronous boost controller features all of the functions necessary to implement a highly efficient synchronous boost regulator. The regulator control method is based upon peak current mode control. Peak current mode control provides inherent line feed-forward and ease of loop compensation. This highly integrated controller provides strong high-side and low-side N-channel MOSFET drivers with adaptive dead-time control. The switching frequency is user programmable up to 1 MHz, either set by a single resistor or synchronized to an external clock. The control mode of high-side synchronous switch can be configured as either forced PWM (FPWM) or diode emulation mode. Fault protection features include cycle-by-cycle current limiting, hiccup mode over load protection, hiccup mode short circuit protection, thermal shutdown and remote shutdown capability by pulling down the UVLO pin. The UVLO input enables the controller when the input voltage reaches a user selected threshold, and provides tiny 9 μA shutdown quiescent current when pulled low. LM5121's unique disconnection switch control provides numerous additional advantages. True Shutdown allows disconnecting load from the input, blocking leakage current paths in shutdown mode. Inrush current control limits input current during initial charging of the output capacitor. Circuit breaker function quickly switches off the disconnection switch, terminating any severe over-current condition. Hiccup mode short circuit protection minimizes power dissipation during prolonged output short condition. Input over voltage suppression can be achieved by connecting a Zener diode from the disconnection MOSFET gate pin to ground. The device is available in 20-pin HTSSOP package featuring an exposed pad to aid in thermal dissipation. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Undervoltage Lockout (UVLO) The LM5121 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4 V UVLO standby threshold, the LM5121 is in the shutdown mode with all functions disabled. The shutdown comparator provides 0.1 V of hysteresis to avoid chatter during transitions. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V during power up, the controller is in the standby mode with the VCC regulator operational, the disconnection switch disabled and no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO pin down below the UVLO standby threshold with an external open collector or open drain device. VIN UVLO Hysteresis Current RUV2 RUV1 STANDBY UVLO UVLO Threshold UVLO Standby Enable Threshold SHUTDOWN + + STANDBY SHUTDOWN Figure 18. UVLO Remote Standby and Shutdown Control If the UVLO pin voltage is above 1.2 V UVLO threshold and VCC voltage exceeds the VCC UV threshold, the startup sequence begins. UVLO hysteresis is accomplished with an internal 10 μA current source that is switched on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds the 1.2 V, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.2 V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. In addition to the UVLO hysteresis current source, a 5 μs deglitch filter on both rising and falling edge of UVLO toggling helps preventing chatter during power up or down. An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO pin is 16 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not be left floating. The values of RUV1 and RUV2 can be determined from Equation 1 and Equation 2. VHYS RUV2 ª: º 10$ ¬ ¼ (1) 1.2V u RUV2 RUV1 ª: º VIN(STARTUP) 1.2V ¬ ¼ (2) where • • VHYS is the desired UVLO hysteresis VIN(STARTUP) is the desired startup voltage of the regulator during turn-on. Typical shutdown voltage during turn-off can be calculated as follows: VIN(SHUTDOWN) VIN(STARTUP) VHYS [V] (3) High Voltage VCC Regulator The LM5121 contains an internal high voltage regulator that provides typical 7.6 V VCC bias supply for the controller and N-channel MOSFET drivers. The input of the VCC regulator, VIN can be connected to a voltage source as high as 65 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V. When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage. The output of the VCC regulator is current limited at 50 mA minimum. Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The recommended range for the VCC capacitor is 1.0 μF to 47 μF and it is recommended to be at least 10 times greater than CBST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor should be 4.7 µF or greater. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 13 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The internal power dissipation of the LM5121 device can be reduced by supplying VCC from an external supply. If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 19. External VCC VCC Supply LM5121 CVCC Figure 19. External Bias Supply when 9 V<VEXT<14.5 V Shown in Figure 20 is a method to derive the VCC bias voltage with an additional winding on the boost inductor. This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC regulator. VCC + nuVOUT nuVIN + + nu(VOUT -VIN) 1:n VIN VOUT + + Figure 20. External Bias Supply using Transformer The VCC regulator series pass transistor includes a diode between VCC and VIN, as shown in Figure 21, that should not be forward biased in normal operation. If the voltage of the external VCC bias supply is greater than the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply through VCC. The need for the blocking diode should be evaluated for all applications when the VCC is supplied by the external bias supply. When the input power supply voltage is less than 4.5 V, an external VCC supply should be used and the external blocking diode is required. VIN VIN LM5121 External VCC Supply VCC Figure 21. VIN Configuration when VVIN<VVCC 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Oscillator The LM5121 switching frequency is programmable by a single external resistor connected between the RT pin and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and AGND pin. To set a desired switching frequency (fSW), the resistor value can be calculated from Equation 4. 9 u 109 ª: º fSW ¬ ¼ RT (4) Slope Compensation For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. Subharmonic oscillation is normally characterized by alternating wide and narrow duty cycles. This sub-harmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope compensation, to the sensed inductor current. Additional slope tON Sensed Inductor Current = ILIN u RS u10 Figure 22. Slope Compensation The slope compensation of the LM5121 is programmable by a single resistor connected between the SLOPE pin and the AGND pin. The amount of slope compensation can be calculated as follows: 6 x109 xD fSW x RSLOPE VSLOPE [V] where D • 1 VIN VOUT (5) RSLOPE value can be determined from the following equation at minimum input voltage: LIN u 6 u 109 ª¬: º¼ ªK u VOUT VIN(MIN) º u RS u 10 ¬ ¼ RSLOPE where • K=0.82~1 as a default (6) From the above equation, K can be calculated over the input range as follows: K § LIN u 6 u 109 ¨1 ¨ VIN u RS u 10 u RSLOPE © · ¸ u D' ¸ ¹ where D' • VIN VOUT (7) In any case, K should be greater than 0.5. At higher switching frequency over 500 kHz, the K factor is recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope compensation due to internal delays. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 15 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The sum of sensed inductor current and slope compensation should be less than COMP output high voltage (VOH) for proper startup with load and proper current limit operation. This limits the minimum value of RSLOPE to be: RSLOPE ! • · ¸ ª¬: º¼ ¸ ¹ This equation can be used in most cases RSLOPE ! • VIN MIN 5.7 u 109 § u ¨ 1.2 ¨ fSW VOUT © 8 u 109 ª: º fSW ¬ ¼ This conservative selection should be considered when VIN(MIN) < 5.5 V The SLOPE pin cannot be left floating. Error Amplifier The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin voltage and the internal precision 1.2 V reference. The output of the error amplifier is connected to the COMP pin allowing the user to provide a Type 2 loop compensation network. RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage loop. This network creates a pole at DC, a mid-band zero (fZ_EA) for phase boost, and a high frequency pole (fP_EA). The minimum recommended value of RCOMP is 2 kΩ (See the Feedback Compensation section). 1 fZ _ EA ªHz º 2S u RCOMP u CCOMP ¬ ¼ (9) fP _ EA 1 § CCOMP u CHF 2S u RCOMP u ¨ © CCOMP CHF · ¸ ¹ ª¬Hz º¼ (10) PWM Comparator The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the voltage at the COMP pin through a 1.2 V internal COMP to PWM voltage drop and terminates the present cycle when the sum of sensed inductor current and slope compensation ramp is greater than VCOMP –1.2 V. ILIN RS CSP CSN + CS A=10 AMP RSLOPE SLOPE Generator VOUT REF + + - + PWM Comparator RFB2 1.2 V FB Error Amplifier COMP RCOMP CCOMP RFB1 CHF (optional) Type 2 Compensation Components Figure 23. Feedback Configuration and PWM Comparator 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Disconnection Switch Control Soft turn-on is achieved by slowly turning on the disconnection switch. When the UVLO pin voltage is greater than 1.2 V UVLO threshold and the VCC voltages exceeds the VCC UV threshold, the internal charge pump at DG starts sourcing current which enhances N-channel MOSFET disconnection switch. The internal charge pump provides bias voltage at DG pin above VIN pin voltage. Additional inrush current limiting helps to limit the maximum inrush current. In the inrush current limiting condition when the voltage across sense resistor RS reaches the inrush current limit threshold, the DG pin voltage is controlled to limit the current flow in RS by controlling DG pull-down current sink. As the source voltage of the disconnection switch is charged during initial charging period, the operating point of the disconnection switch transitions from an active region into the ohmic region and the DG pin voltage is maintained by the charge pump. An internal 10 µA soft-start current source turns on when the DG to DS voltage is greater than VGS detection threshold. VIN voltage is recommended to be greater than or equal to the input power supply voltage because the internal charge pump provides the DG bias voltage above the VIN voltage. The DG pin voltage is clamped to approximately 16 V above the DS pin and 11 V above the VIN pin by internal zener diodes. Standby Shut down 1.2V UVLO 0.4V VCC UV Threshold VCC TURN-ON VGS VGS Detection Threshold TURN-OFF Inrush current limit VGS Detect 10µA current source 1.2V SS LO HO-SW VIN tSS VOUT Startup Delay Figure 24. Start-Up Sequence Hiccup Mode Short Circuit / Overload Protection If cycle-by-cycle current limit or inrush current limit is reached during any cycle, a 30 μA RES current is sourced into the RES capacitor for the remainder of the clock cycle. If the RES capacitor voltage exceeds the 1.2 V restart threshold, a hiccup mode protection sequence is initiated. In the hiccup mode, the DG pin is discharged to GND if the inrush current limit is reached, the SS capacitor is discharged to GND, both LO and HO outputs are disabled, and the voltage on the RES capacitor is ramped up and down between 2 V and 4 V eight times. After the eighth RES pin cycle, the DG pin is released and charged by the DG charge pump. If a 2~3 V zener diode is connected in parallel with the RES capacitor, the regulator enters into the hiccup mode and never restarts until UVLO shutdown is cycled. Connect the RES pin directly to the AGND when the hiccup mode operation is not required. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 17 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com IRES = 10µA IRES = -5µA 4V 2.0V 1.2V tCount to Eightt RES IRES = 30µA Restart Delay tRD tHiccup Mode Off-time tRESt SS HO LO VGS-DET VDG-DS Figure 25. Hiccup Mode Short Circuit Protection (Start-Up With Output Short) IRES = 10µA IRES = -5µA 4V 2.0V 1.2V RES tCount to Eightt IRES = 30µA Restart Delay tRD SS tHiccup Mode Off-time tRESt HO LO VDG-DS VGS-DET DG Pull-down when Inrush Current Limit is Reached Figure 26. Hiccup Mode Overload Protection (Overload After Start-Up) Soft-Start The soft-start feature helps the regulator gradually reach the steady state operating point, thus reducing startup stresses and surges. The LM5121 regulates the FB pin to the SS pin voltage or the internal 1.2 V reference, whichever is lower. The internal 10 μA soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage starting from the input voltage level to the target output voltage. The soft-start time (tSS) varies with the input supply voltage and output set point and is calculated from Equation 11. CSS u 1.2V § V · u ¨ 1 IN ¸ ª¬sec º¼ tSS 10$ 9OUT ¹ © (11) 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 When UVLO pin voltage is greater than 1.2 V UVLO threshold, VCC voltage exceeds the VCC UV threshold and DG to DS voltage is greater than VGS detection threshold, an internal 10 μA soft-start current source turns on. At the beginning of this soft-start sequence, VSS should be allowed to fall down below 25 mV by the internal SS pulldown switch. The SS pin can be pulled down by an external switch to stop switching, but pulling up to enable switching is not recommended. The startup delay (see Figure 24) should be long enough for the high-side boot capacitor to be fully charged by the internal BST charge pump. This defines the recommended minimum CSS value, which is especially important when VVIN is greater than 9 V. §V · CSS ! 0.33 u CBST u ¨ OUT ¸ ª¬F º¼ © VVIN ¹ (12) Also, the value of CSS should be large enough to charge the output capacitor during soft-start time. 10$ u 9OUT &OUT CSS ! u ªF º 1.2V IOUT ¬ ¼ (13) HO and LO Drivers The LM5121 contains two strong N-channel MOSFET gate drivers and a high-side level shifter to drive the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external bootstrap diode DBST, and bootstrap capacitor CBST. During the on-time of the low-side N-channel MOSFET driver, the SW pin voltage is approximately 0 V and the CBST is charged from VCC through the DBST. A 0.1 μF or larger ceramic capacitor, connected with short traces between the BST and SW pin, is recommended. The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO Fall to LO Rise Delay). Similarly, the HO turn-on is delayed until the LO voltage has discharged. HO is then enabled after a small delay (LO Fall to HO Rise Delay). This technique ensures adequate dead-time for any size Nchannel MOSFET or parallel MOSFET configurations especially when VCC is supplied by a higher external voltage source. Use caution when adding series gate resistors, as this may decrease the effective dead-time. Care should be exercised in selecting the N-channel MOSFET devices threshold voltage when the VIN voltage range is below the VCC regulation level or a bypass operation is required. If bypass operation is required when output voltage is less than 12 V, a logic level device should be selected for the high-side N-channel MOSFET. During startup at low input voltages, the low-side N-channel MOSFET's gate plateau voltage should be sufficiently low to completely enhance the N-channel MOSFET device. If the low-side MOSFET drive voltage is lower than the low-side MOSFET gate plateau voltage during startup, the regulator may not start properly and it may operate at the maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET or by increasing VIN(STARTUP) with the UVLO pin programming. MODE Control (Forced PWM Mode and Diode Emulation Mode) A fully synchronous boost regulator implemented with a high-side MOSFET rather than a diode has the capability to sink current from the output in conditions such as light load, overvoltage or load transient. The LM5121 can be configured to operate in either forced PWM mode or diode emulation mode. In forced PWM mode (FPWM), reverse current flow in high-side N-channel MOSFET switch is allowed and the inductor current conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast light load to heavy load transient response and constant frequency operation at light or no load conditions. To enable forced PWM mode, connect the MODE pin to VCC or tie it to a voltage greater than 1.2 V. In the FPWM mode, reverse current flow is not limited. In the diode emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain). Turn-on of the high-side switch is allowed if the CSP to CSN voltage is greater than the 7 mV rising threshold of the zero current detection circuit during low-side switch on-time. If the CSP to CSN voltage is less than 6 mV falling threshold of the zero current detection during high-side switch on-time, reverse current flow from output to input through the high-side N-channel MOSFET is prevented and discontinuous conduction mode of operation is enabled by latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode emulation is lower power loss at light load conditions. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 19 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com 1.2 V COMP + - 40mV Hysteresis 1.2V MODE SkipCycle + 700k Default 150mV 20mV + Skip Cycle Comparator 1.2V 100k + - Diode Emulation Figure 27. MODE Selection During startup the LM5121 forces diode emulation, to support startup into a pre-biased load, until the SS pin voltage exceeds 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater than 1.2 V. If there are no LO pulses during the soft-start period, a 350 ns one-shot LO pulse is forced at the end of soft-start to help charge the bootstrap capacitor. Due to the internal current sense delay, configuring the LM5121 for diode emulation mode should be carefully evaluated if the inductor current ripple ratio is high and the controller is operated at very high switching frequency. The transient performance during full load to no load in FPWM mode should also be verified. MODE Control (Skip Cycle Mode and Pulse Skipping Mode) Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of the converter become a significant percentage of the total power delivered to the load. In order to increase the light load efficiency the LM5121 provides two types of light load operation in diode emulation mode. The skip cycle mode integrated into the LM5121 controller reduces switching losses and improves efficiency in light load conditions by reducing the average switching frequency. Skip cycle operation is achieved by the skip cycle comparator. When a light load condition occurs, the COMP pin voltage naturally decreases, reducing the peak current delivered by the regulator. During COMP voltage falling, the skip cycle threshold is defined as VMODE –20 mV and during COMP voltage rising, it is defined as VMODE +20 mV. There is 40mV of internal hysteresis in the skip cycle comparator. When the voltage at PWM comparator input falls below VMODE –20 mV, both HO and LO outputs are disabled. The controller continues to skip switching cycles until the voltage at PWM comparator input increases to VMODE +20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the response time of the frequency compensation network. The internal hysteresis of skip cycle comparator helps to produce a long skip cycle interval followed by a short burst of pulses. An internal 700 kΩ pull-up and 100 kΩ pulldown resistor sets the MODE pin to 0.15 V as a default. Since the peak current limit threshold is set to 750 mV, the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level will be lower due to the added slope compensation. By adding an external pull-up resistor from MODE to the SLOPE or VCC pin or adding an external pull-down resistor to the ground, the skip cycle threshold can be programmed. Because the skip cycle comparator monitors the PWM comparator input which tracks the COMP voltage, skip cycle operation is not recommended when the bypass operation is required. Pulse skipping operation can be achieved by connecting the MODE pin to ground. The negative 20 mV offset at the positive input of skip cycle comparator ensures the skip cycle comparator will not be triggered in normal operation. At light or no load conditions, the LM5121 skips LO pulses if the pulse width required by the regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as the error amplifier attempts to find the proper pulse width to maintain regulation at light or no load conditions. Bypass Operation (VOUT = VIN) The LM5121 allows 100% duty cycle operation for the high-side synchronous switch when the input supply voltage is equal to or greater than the target output voltage. An internal 200 μA BST charge pump maintains sufficient high-side driver supply voltage to keep the high-side N-channel MOSFET switch on without the power stage switching. The internal BST charge pump is enabled when the UVLO pin voltage is greater than 1.2 V, the VCC voltage exceeds the VCC UV threshold and DG to DS voltage is greater than the VGS detection threshold. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 The BST charge pump generates 5.3 V minimum BST to SW voltage when SW voltage is greater than 9 V. This requires minimum 9 V boost output voltage for proper bypass operation. The leakage current of the boot diode should be always less than the BST charge pump sourcing current to maintain a sufficient driver supply voltage at both low and high temperatures. Forced PWM mode is the recommended PWM configuration when bypass operation is required. Cycle-by-Cycle Current Limit The LM5121 features a peak cycle-by-cycle current limit function. If the CSP to CSN voltage exceeds the 75 mV cycle-by-cycle current limit threshold, the current limit comparator immediately terminates the LO output. For the case where the inductor current overshoots the desired limit, such as inductor saturation, the current limit comparator blocks LO pulses until the current has decayed below the current limit threshold. Peak inductor current in current limit can be calculated as follows: 75mV IPEAK(CL) ªA º RS ¬ ¼ (14) Circuit Breaker Function In addition to the hiccup mode short circuit / overload protection, LM5121 provides a circuit breaker function for maximum safety. If the input current increases rapidly due to a fault, the current through the disconnection switch may exceed the inrush control threshold before the inrush control loop is able to respond. If the sensed current exceeds the circuit breaker threshold, the disconnection switch is quickly turned off through an internal switch at the DG pin until current sense input falls below the circuit breaker disable threshold. If the RES pin voltage is less than 1.2 V, the controller then restarts the inrush control procedure. Clock Synchronization The SYNCIN/RT pin can be used to synchronize the internal oscillator to an external clock. The positive going synchronization clock at the RT pin must exceed the RT sync rising threshold and the negative going synchronization clock at RT pin must exceed the RT sync falling threshold to trip the internal synchronization pulse detector. With the configuration in Figure 28, the frequency of the external synchronization pulse is recommended to be within +/–20% of the internal oscillator frequency programmed by RT resistor. The actual operating range is +/– 100/40% of the programmed frequency. For example, 900 kHz external synchronization clock and 20 kΩ RT resistor are required for 450 kHz switching. The internal oscillator can be synchronized by AC coupling a positive edge into the RT pin. A 5 V amplitude pulse signal coupled through 100 pF capacitor is a good starting point. The RT resistor is always required in this configuration, whether the oscillator is free running or externally synchronized. Care should be taken to guarantee that the RT pin voltage does not go below –0.3 V at the falling edge of the external pulse. This may limit the duty cycle of external synchronization pulse. There is approximately 400 ns delay from the rising edge of the external pulse to the rising edge of LO. fSYNC SYNCIN/RT CSYNC RT LM5121 Figure 28. Oscillator Synchronization Through AC Coupling With the configuration in Figure 29, the internal oscillator can be synchronized by connecting the external synchronization clock to the RT pin through the RT resistor with free of the duty cycle limit. The output stage of the external clock source should be a low impedance totem-pole structure and the default logic state of fSYNC should be low. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 21 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com fSYNC SYNCIN/RT RT LM5121 Figure 29. Oscillator Synchronization Through a Resistor Maximum Duty Cycle When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle. This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with high switching frequency and high duty cycle requirements, check the required maximum duty cycle. The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 15 . VIN(MIN) fSW u VOUT u (750ns margin) [V] (15) 100 ns of margin is recommended. Thermal Protection Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to prevent overheating and destroying the device. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 APPLICATION INFORMATION Feedback Compensation The open loop response of a boost regulator is the product of the modulator transfer function and the feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain. The modulator transfer function of a current mode boost regulator including a power stage transfer function with an embedded current loop can be simplified as one pole, one zero and one Right Half Plane (RHP) zero system. Modulator transfer function is defined as follows: § · § s s ¨1 ¸ u ¨1 ¨ ¸ ¨ Ö & & VOUT (s) Z _ ESR ¹ © Z _ RHP AM u © Ö § VCOMP (s) s · ¨1 ¸ ¨ &P _ LF ¸ © ¹ · ¸ ¸ ¹ where RLOAD D' u RS _ EQ u A S 2 AM (Modulator DC gain) • • &P _ LF /RDG SROH 2 RLOAD u COUT &Z _ ESR (65]HUR 1 RESR u COUT &Z _ RHP 5+3]HUR RLOAD u (D' )2 LIN _ EQ • • • • LIN _ EQ LIN , RS _ EQ n RS n n is the number of the phase. (16) If the ESR of COUT (RESR) is small enough and the RHP zero frequency is far away from the target crossover frequency, the modulator transfer function can be further simplified to one pole system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics, and create a pole at origin, a low frequency zero and a high frequency pole. The feedback transfer function is defined as follows: s 1 &Z _ EA VÖ COMP AFB u § VÖ OUT s · s u ¨1 ¸ ¨ &P _ EA ¸¹ © where AFB (Feedback DC gain) • • 1 RFB2 u CCOMP CHF &Z _ EA /RZIUHTXHQF\]HUR &P _ EA +LJKIUHTXHQF\SROH • 1 RCOMP u CCOMP 1 RCOMP u CHF (17) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 23 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The pole at the origin minimizes output steady state error. The low frequency zero should be set to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost is achieved at the crossover frequency. The high frequency pole should be set above the crossover frequency since the addition of CHF adds a pole in the feedback transfer function. The crossover frequency (open loop bandwidth) is usually selected between one twentieth and one fifth of the switching frequency. In a simplified formula, the estimated crossover frequency can be defined as: RCOMP fCROSS u D' [Hz] S u RS _ EQ u RFB2 u A S u COUT where D' • VIN VOUT (18) For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. The modulator transfer function can be measured using a network analyzer and the feedback transfer function can be configured for the desired open loop transfer function. If the network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response. Sub-Harmonic Oscillation Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding a voltage ramp (slope compensation) on top of the sensed inductor current. By choosing K≥0.82~1.0, the sub-harmonic oscillation will be eliminated even with widely varying input voltage. In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point. When the amplitude of an end cycle current error (dI1) caused by an initial perturbation (dI0) is less than the amplitude of dI0 or dI1/dI0 > –1, the perturbation naturally disappears after a few cycles. When dl1/dl0<-1, the initial perturbation no longer disappear, it results in sub-harmonic oscillation in the steady-state. Steady-State Inductor Current dI0 tON dI1 Inductor Current with Initial Perturbation Figure 30. Effect of Initial Perturbation when dl1/dl0 < -1 dI1/dI0 can be calculated as: dI1 1 1 dI0 K (19) The relationship between dI1/dI0 and K factor is illustrated graphically below. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Figure 31. dl1/dl0 vs K Factor The absolute minimum value of K is 0.5. When K<0.5, the amplitude of dl1 is greater than the amplitude of dl0 and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be under-damped. Any perturbation will be over-damped when 0<dl1/dl0<1. In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as: 1 Q S K 0.5 (20) The relationship between Q and K factor is illustrated in Figure 32 Figure 32. Sampling Gain Q vs K Factor The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results in subharmonic oscillation at fSW/2. A higher value of K factor may introduce additional phase shift near the crossover frequency, but has the benefit of reducing noise susceptibility in the current loop. The maximum allowable value of K factor can be calculated using the maximum crossover frequency equation and frequency analysis formulas in Table 1. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 25 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Table 1. BOOST REGULATOR FREQUENCY ANALYSIS SIMPLIFIED FORMULA MODULATOR TRANSER FUNCTION Modulator DC gain RHP zero VÖ OUT (s) Ö V (s) COMP COMPREHENSIVE FORMULA § · § s s ¨1 ¸ u ¨1 ¨ ¸ ¨ Z ZZ _ RHP Z _ ESR ¹ © © AM u § s · ¨1 ¸ ¨ ZP _ LF ¸¹ © (2) · ¸ ¸ ¹ VÖ OUT s Ö VCOMP s 1 RESR u COUT &Z _ ESR ESR pole Not considered Dominant load pole &P _ LF &Z _ ESR 1 RESR1 u COUT1 &P _ ESR 1 RESR1 u COUT1 / /COUT2 2 RLOAD u COUT &P _ HF Sampled gain inductor pole Not considered Sub-harmonic double pole K factor Not considered Not considered K=1 VÖ (s) COMP VÖ (s) Q 1 S K 0.5 &n &SW 2 S u ISW fn fSW 2 K § LIN u 6 u 109 ¨1 ¨ V u IN RS u 10 u RSLOPE © 1 AFB u OUT AFB Feedback DC gain Mid-band Gain Low frequency zero &Z _ EA 1 RCOMP u CHF · ¸ u D' ¸ ¹ s &Z _ EA § s s u ¨1 ¨ & P _ EA © · ¸ ¸ ¹ 1 RFB2 u (CCOMP CHF ) AFB _ MID &P _ EA 4 u &n or FEEDBACK TRANSFER FUNCTION High frequency pole fSW K 0.5 or &P _ HF Quality factor · ¸ ¸ ¹ RLOAD u (D')2 LIN _ EQ &Z _ RHP ESR zero § s ¨1 ¨ &P_LF © § s · § s · ¨1 ¸ u ¨1 ¸ ¨ &ZESR ¸ ¨© &ZRHP ¸¹ © ¹ · § · § s s s2 2 ¸ u ¨1 ¸ u ¨1 ¸ ¨ ¸ ¨ & & &n p _ ESR ¹ © P_HF ¹ © RLOAD D' u RS _ EQ u A S 2 AM (2) AM u (1) RCOMP RFB2 1 RCOMP u CCOMP ZP _ EA 1 RCOMP u CCHF / /CCOMP (1) Comprehensive equation includes an inductor pole and a gain peaking at fSW/2, which is caused by sampling effect of the current mode control. Also, it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1. (2) With multiphase configuration, number of phases. 26 LIN _ EQ LIN RS _ EQ n , RS R LOAD n , VOUT IOUT of each phase u n , and COUT = COUT of each phase x n, where n = Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Table 1. BOOST REGULATOR FREQUENCY ANALYSIS (continued) SIMPLIFIED FORMULA § · § s s ¨1 ¸ u ¨1 ¨ &Z _ ESR ¸ ¨ &Z _ RHP © ¹ © AM u AFB u § s · ¨1 ¸ ¨ &P _ LF ¸ © ¹ OPEN LOOP RESPONSE T s Crossover frequency (3) (Open loop band width) fCROSS · ¸ ¸ ¹u COMPREHENSIVE FORMULA 1 s &Z _ EA § s s u ¨1 ¨ &P _ EA © RCOMP u D' S u RS _ EQ u RFB2 u A S u COUT · ¸ ¸ ¹ § · § · s s ¨1 ¸ u ¨1 ¸ ¨ &Z _ ESR ¸¹ ¨© &Z _ RHP ¸¹ © AM u AFB u § · § s · § s s s2 ¨1 ¸ u ¨1 ¸ u ¨1 ¨ &P _ LF ¸¹ ¨© &p _ ESR ¸¹ ¨© &PHF &n2 © T s fSW &Z _RHP or whichever is smaller 5 2u Su 4 fCROSS _MAX 1 · ¸ ¸ ¹ u s &Z _ EA § s s u ¨1 ¨ &P _ EA © · ¸ ¸ ¹ Use graphic tool fCROSS _MAX Maximum cross over frequency (4) (1) fSW § u ¨ 1 4 u Q2 1 ·¸ ¹ 4uQ © or &Z _ RHP 2u Su 4 , whichever is smaller (3) (4) f &Z _ RHP CCOMP RLOAD u COUT D' 4 u RCOMP , and Assuming &Z _ EA &P _ LF, &P _ EA &Z _ ESR, CROSS 2 u S u 10 , The frequency at which 45º phase shift occurs in modulator phase characteristics. VIN VOUT . Output Overvoltage Protection Output overvoltage protection can be achieved by adding a simple external circuit. The output overvoltage protection circuit shown in Figure 33 shuts down the LM5121 when the output voltage exceeds the overvoltage threshold set by the zener diode. VOUT LM5121 UVLO Figure 33. Output Overvoltage Protection Input Transient Suppression Input over-voltage transient suppression can be achieved by adding a zener diode from DG to ground. The DS voltage will be clamped to the zener voltage minus the gate threshold voltage of the disconnection MOSFET switch. Since the input clamping occurs in the active region of disconnection MOSFET switch, safe operating area and the thermal properties of the disconnection MOSFET switch should be carefully considered. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 27 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com V SUPPLY V OUT + BST VCC DS SW LO DG HO COMP CSN FB CSP RES VIN UVLO SS MODE PGND AGND SLOPE SYNCIN/RT LM5121 Figure 34. Input Transient Suppression Inrush Current Limit Programming Inrush current limit level can be lower than the cycle-by-cycle current limit level by adding a simple external circuit. The external inrush current limit programming circuit shown in Figure 35 and Figure 36 pull down CSN pin during inrush current limiting. Also, this configuration enables latch-off mode circuit breaker. ILIN CSN 100 k CSP RINRUSH 100 100 RS VCC SLOPE 1.2Vth NMOS Figure 35. Inrush Current Limit Programming #1 ILIN RINRUSH CSN VCC 100 k CSP 100 100 RS SLOPE Figure 36. Inrush Current Limit Programming #2 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 VIN 500k Reverse Battery Protection + Disconnect Switch Control Signal PMOS Power NMOS DG VOUT DS + + VCC DS BST SW LO DG HO CSN COMP CSP FB VIN RES SS UVLO SLOPE SYNCIN/RT LM5121 MODE PGND AGND VIN 500k Figure 37. Reverse Battery Protection + Disconnection Switch Signal PMOS Power NMOS VOUT + 500k 100pF + VCC DS BST DG CSN SW LO HO COMP CSP FB VIN RES UVLO SLOPE SYNCIN/RT LM5121 SS MODE PGND AGND Figure 38. Reverse Battery Protection PC Board Layout Recommendation In a boost regulator, the primary switching loop consists of the output capacitor and N-channel MOSFET power switches. Minimizing the area of this loop reduces the stray inductance and minimizes noise. Especially, placing high quality ceramic output capacitors as close to this loop earlier than bulk aluminum output capacitors minimizes output voltage ripple and ripple current of the aluminum capacitors. In order to prevent a dv/dt induced turn-on of high-side switch, HO and SW should be connected to the gate and source of the high-side synchronous N-channel MOSFET switch through short and low inductance paths. In FPWM mode, the dv/dt induced turn-on can occur on the low-side switch. LO and PGND should be connected to the gate and source of the low-side N-channel MOSFET through short and low inductance paths. All of the power ground connections should be connected to a single point. Also, all of the noise sensitive low power ground connections should be connected together near the AGND pin and a single connection should be made to the single point PGND. CSP and CSN are high impedance pins and noise sensitive. CSP and CSN traces should be routed together with kelvin connections to the current sense resistor as short as possible. If needed, place 100 pF ceramic filter capacitor as close to the device. MODE pin is also high impedance and noise sensitive. If an external pull-up or pull-down resistor is used at MODE pin, the resistor should be placed as close the device. VCC, VIN and BST capacitor must be as physically close as possible to the device. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 29 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com The LM5121 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the device. The junction to ambient thermal resistance varies with application. The most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and the amount of forced air cooling. The integrity of the solder connection from the device exposed pad to the PC board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating components are the two power switches. Selecting N-channel MOSFET switches with exposed pads aids the power dissipation of these devices. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Design Example and Component Selection OPERATING CONDITIONS ● Output Voltage (VOUT) : 12 V ● Full Load Current (IOUT) : 2A ● Output Power : 24 W ● Minimum Input Voltage (VIN(MIN)) : 3 V (5.7 V for start-up) ● Typical Input Voltage (VIN(TYP)) : 9V ● Maximum Input Voltage (VIN(MAX)) : 12 V ● Switching Frequency (fSW) : 250 kHz ● Disconnection Switch Control : Yes TIMING RESISTOR RT Generally, higher frequency applications are smaller but have higher losses. Operation at 250 kHz is selected for this example as a reasonable compromise between small size and high-efficiency. The value of RT for 250 kHz switching frequency is calculated as follows: RT 9 u 109 fSW 9 u 109 250 kHz 36.0 k: (21) A standard value of 36.5 kΩ is chosen for RT. UVLO DIVIDER RUV2, RUV1 The desired startup voltage and the hysteresis are set by the voltage divider RUV2, RUV1. The UVLO shutdown voltage should be high enough to fully enhance the low-side N-channel MOSFET switch. For this design, the startup voltage is set to 5.5 V which is 0.2 V below 5.7 V. VHYS is set to 3.7 V. This results 1.8 V of VIN(SHUTDOWN). The values of RUV2, RUV1 are calculated as follows: VHYS 3.7 V RUV2 370 k: IHYS 10 PA (22) RUV1 1.2V u RUV2 VIN(STARTUP) 1.2V 1.2V u 370 k: 5.5V 1.2V 103 k: (23) A standard value of 365 kΩ is selected for RUV2. RUV1 is selected to be a standard value of 107 kΩ. INPUT INDUCTOR LIN The inductor ripple current is typically set between 20% and 40% of the full load current, as a good compromise between core loss and copper loss of the inductor. Higher ripple current allows a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple ratio (RR) of 0.3, 30% of the input current was chosen. Knowing the switching frequency and the typical output voltage, the inductor value can be calculated as follows: LIN VIN V · 1 § u u ¨ 1 IN ¸ IIN u RR fSW © VOUT ¹ 9V 1 9V · § u u 1 24W 250 kHz ¨© 12V ¸¹ u 0.3 9V 11.3 + (24) The closest standard value of 10 μH was chosen for LIN. The saturation current rating of the inductor should be greater than the peak inductor current, which is calculated at the minimum input voltage and full load. A 2.7 V startup voltage is used to conservatively estimate the peak inductor current. IPEAK IIN § VIN V · 1 u u ¨ 1 IN ¸ 2 LIN u fSW © VOUT ¹ 12V u 2A 1 2.7V § 2.7V · u u 1 2.7V 2 10 + u N+] ©¨ 9 ¹¸ 9.3 A Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 (25) 31 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com CURRENT SENSE RESISTOR RS The peak input current limit threshold should be set 20~50% higher than the required peak current at low input voltage and full load, accounting for tolerances. For this example, 20% is margin is chosen. VCS TH1 75 mV RS 6.7 m : IPEAK(CL) 9.3A u 1.2 (26) A closest standard value of 7 mΩ is selected for RS. The maximum power loss of RS is calculated as follows. PLOSS(RS) I2R (9.3A u 1.2)2 u 7m: 0.87W (27) CURRENT SENSE FILTER RCSFP, RCSFN, CCS The current sense filter is optional. 100 pF for CCS and 100 Ω for RCSFP and RCSFN are normal recommendations. Because CSP and CSN pins are high impedance, CCS should be placed physically as close to the device. VIN RCSFN + RCSFP RS CSN LM5121 CCS CSP Figure 39. Current Sense Filter SLOPE COMPENSATION RESISTOR RSLOPE The K value is selected to be 1 at the minimum input voltage. RSLOPE should be selected such that the sum of sensed inductor current and slope compensation is less than COMP output high voltage. RSLOPE ! RSLOPE 8 u 109 fSW 8 u 109 250 kHz LIN u 6 u 10 32 k: (28) 9 9 ªK u VOUT VIN(MIN) º u RS u 10 ¬ ¼ 10 + u u 1u 12V 3V u 7m: u 10 95 k: (29) A closest standard value of 95.3 kΩ is selected for RSLOPE. OUTPUT CAPACITOR COUT The output capacitors smooth the output voltage ripple and provide a source of charge during transient loading conditions. Also the output capacitors reduce the output voltage overshoot when the load is suddenly disconnected. The ripple current rating of the output capacitor should be carefully considered. In boost regulator, the output is supplied by discontinuous current and the ripple current requirement is usually high. In practice, the ripple current requirement can be dramatically reduced by placing high quality ceramic capacitors closer to the high side MOSFET switch than the bulk aluminum capacitors. The output voltage ripple is dominated by the ESR of the output capacitors. Parallel output capacitors are a good choice to minimize effective ESR and split the output ripple current into multiple capacitors. In this example, three 330 µF aluminum capacitors are used to share the output ripple current and source the required charge. The maximum output ripple current can be calculated at the minimum input voltage as follows: IOUT 2.0A IRIPPLE _ MAX(COUT) 4A VIN(MIN) 3V 2 u 2u 12V VOUT (30) 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Assuming 60 mΩ of ESR per output capacitor, the output voltage ripple at the minimum input voltage is calculated as follows: VRIPPLE _ MAX(COUT) § · IOUT 1 u ¨R ¸ VIN(MIN) © ESR 4 u COUT u fSW ¹ VOUT · 2.0A § 60m: 1 u ¸ 3V ¨© 3 4 u 3 u 330 ) u N+] ¹ 12V 0.168V (31) In practice, four 10 µF ceramic capacitors are additionally placed before the bulk aluminum capacitors to reduce the output voltage ripple and share the output ripple current. INPUT CAPACITOR CIN The input capacitors smooth the input voltage ripple. Assuming high quality ceramic capacitors are used for the input capacitors, the maximum input voltage ripple which occurs when the input voltage is half of the output voltage can be calculated as follows: VOUT 12V VRIPPLE _ MAX(CIN) 0.045V 32 u LIN u CIN u fSW 2 32 u 10 PH u 4 u 3.3 PF u 250 kHz2 (32) The value of input capacitor is also a function of source impedance, the impedance of source power supply. More input capacitor will be required to prevent a chatter condition during power up if the impedance of source power supply is not low. VIN FILTER RVIN, CVIN An R-C filter (RVIN, CVIN) on the VIN pin is optional. It is not required if the CIN capacitors are high quality ceramic capacitors and placed physically close to the device. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. A 0.47 μF ceramic capacitor is used this example. Recommended filter values are 3 Ω for RVIN and 0.47 µF for CVIN . A larger filter with 2.2 µ to 4.7 µF CVIN is recommended when the input voltage is lower than 8 V or when the required duty cycle is close to the maximum duty cycle limit. VIN VIN RVIN CVIN LM5121 Figure 40. VIN Filter BOOTSTRAP CAPACITOR CBST AND BOOST DIODE DBST The bootstrap capacitor between the BST and SW pins supplies the gate current to charge the high-side Nchannel MOSFET gate during each turn-on cycle and also supplies recovery charge for the bootstrap diode. The peak current can be several amperes. The recommended value of the bootstrap capacitor is 0.1 μF. CBST should be a good quality, low ESR, ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance. The minimum value for the bootstrap capacitor is calculated as follows: QG CBST ªF º û9BST ¬ ¼ (33) Where QG is the high-side N-channel MOSFET gate charge and ΔVBST is the tolerable voltage droop on CBST, which is typically less than 5% of VCC or conservatively 0.15 V . In this example, the value of the BST capacitor (CBST) is 0.1 µF. The voltage rating of DBST should be greater than the peak SW node voltage plus 16 V. A low leakage diode is mandatory for bypass operation. The leakage current of DBST should be low enough for the BST charge pump to maintain a sufficient high-side driver supply voltage at high temperature. A low leakage diode also prevents the possibility of excessive VCC voltage during shutdown, in high output voltage applications. If the diode leakage is excessive, a zener clamp or bleed resistor may be required on VCC. High-side driver supply voltage should be greater than the high-side N-channel MOSFET switch gate plateau at the minimum input voltage. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 33 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com VCC CAPACITOR CVCC The primary purpose of the VCC capacitor is to supply the peak transient currents of the LO driver and bootstrap diode as well as to provide stability for the VCC regulator. The peak driver currents can be several amperes. The value of CVCC should be at least 10 times greater than the value of CBST, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed close to the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. A value of 4.7 µF was selected for this design example. OUTPUT VOLTAGE DIVIDER RFB1, RFB2 RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as follows: VOUT RFB2 1 RFB1 1.2V (34) The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation small. A 49.9 kΩ in series with 681 Ω was chosen for high-side feedback resistors in this example, which results in a RFB1 value of 5.62 kΩ for 12 V output. SOFT-START CAPACITOR CSS The soft-start time (tSS) is the time required for the output voltage set point to reach the target voltage from the input voltage. The soft-start time is not only proportional to the soft-start capacitor, but also depends on the input voltage. With 0.1 µF for CSS, the soft-start time is calculated as follows: VIN(STARTUP) · 0.1 ) u 9 § CSS u 1.2V § 9 · u ¨¨ 1 u ¨1 tSS(MAX) 6.3 msec ¸¸ ISS V 10 $ 9 ¸¹ © OUT © ¹ (35) RESTART CAPACITOR CRES The restart capacitor determines the restart delay time tRD and hiccup mode off time tRES (see Figure 25). tRD should be greater than tSS(MAX). The minimum required value of CRES can be calculated at the low input voltage as follows: IRES u tSS(MAX) 30 $ u PVHF CRES(MIN) 0.16 PF VRES 1.2V (36) A standard value of 0.18 µF is selected for CRES. LOW-SIDE POWER SWITCH QL Breaking down the various losses is one way to compare the relative efficiencies of different N-channel MOSFET devices. Losses in the low-side N-channel MOSFET device can be separated into conduction loss and switching loss. Low-side conduction loss is approximated calculated as follows: PCOND(LS) D u IIN2 u RDS _ ON(LS) u 1.3 § VIN ¨1 V OUT © 2 · § IOUT u VOUT · ¸u¨ ¸ u RDS _ ON(LS) u 1.3 [W] VIN ¹ ¹ © (37) Where D is the duty cycle and the factor of 1.3 accounts for the increase in the N-channel MOSFET device onresistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature onresistance of the N-channel MOSFET device can be estimated using the RDS(ON) vs temperature curves in the Nchannel MOSFET datasheet. Switching loss occurs during the brief transition period as the low-side N-channel MOSFET device turns on and off. During the transition period both current and voltage are present in the channel of the N-channel MOSFET device. The low-side switching loss is approximated as follows: PSW(LS) 0.5 u VOUT u IIN u (tR tF ) u fSW [W] (38) tR and tF are the rise and fall times of the low-side N-channel MOSFET device. The rise and fall times are usually mentioned in the N-channel MOSFET datasheet or can be empirically observed with an oscilloscope. 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 An additional Schottky diode can be placed in parallel with the low-side N-channel MOSFET switch, with short connections to the source and drain in order to minimize negative voltage spikes at the SW node. HIGH-SIDE POWER SWITCH QH AND ADDITIONAL PARALLEL SCHOTTKY DIODE Losses in the high-side N-channel MOSFET device can be separated into conduction loss, dead-time loss and reverse recovery loss. Switching loss is calculated only for the low-side N-channel MOSFET device. Switching loss in the high-side N-channel MOSFET device is negligible because the body diode of the high-side N-channel MOSFET device turns on before and after the high-side N-channel MOSFET switches. High-side conduction loss is approximated as follows: 2 PCOND(HS) (1 D) u IIN2 u RDS _ ON(HS) u 1.3 § VIN · § IOUT u VOUT · ¨ ¸u¨ ¸ u RDS _ ON(HS) u 1.3 [W] VIN ¹ © VOUT ¹ © (39) Dead-time loss is approximated as follows: PDT(HS) VD x IIN x (tDLH tDHL ) x fSW [W] where • VD is the forward voltage drop of the high-side N-channel MOSFET body diode. (40) Reverse recovery characteristics of the high-side N-channel MOSFET strongly influences efficiency, especially when the output voltage is high. Smaller reverse recovery charge helps to increase the efficiency while also minimizing switching noise. Reverse recovery loss is approximated as follows: PRR(HS) VOUT u QRR u fSW [W] (41) where • QRR is the reverse recovery charge of the high-side N-channel MOSFET body diode. (42) An additional Schottky diode can be placed in parallel with the high-side switch to improve efficiency. Usually, the power rating of this parallel Schottky diode can be less than the high-side switch ratings because the diode conducts only during dead-times. The power rating of the parallel diode should be equivalent or higher than highside switch ratings if bypass operation is required, hiccup mode operation is required or a heavy load exists before the controller begins switching. SNUBBER COMPONENTS A resistor-capacitor snubber network across the high-side N-channel MOSFET device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50 Ω. Increasing the value of the snubber capacitor results in more damping, but this also increases snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout. Disconnect Switch QD Selection The N-channel MOSFET disconnection switch (QD) should be selected based on the following criteria: • The BVDSS rating must be greater than the maximum input voltage, plus ringing and transients. • The safe operating area (SOA) and the thermal properties should be considered. If required, limit the rise time of the input power supply or the maximum start-up input voltage. • Absolute maximum rating of VGS should be greater than 18 V. • If the minimum VIN voltage is less than 6.5 V, a logic level MOSFET should be used. • The plateau voltage during inrush current limiting is recommended to be less than VGS-DET. If the VPLATEAU is greater than VGS-DET, boost switching might start before finishing the inrush limiting. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 35 LM5121/LM5121-Q1 SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Freewheeling Diode DF Selection If QD turns off quickly by the circuit breaker function, the inductor current continues flowing through a freewheeling diode (DF). DF should have enough capability to handle 150 mV/RS of peak current during inductor current decay and the voltage rating must be greater than the maximum input voltage, plus ringing and transients. The inductor current decay time is calculated from Equation 43. LIN u 0.15 tDF [sec] RS u (VOUT VIN ) (43) LOOP COMPENSATION COMPONENTS CCOMP, RCOMP, CHF RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below: STEP1: Select fCROSS Select the cross over frequency (fCROSS) at one fourth of the RHP zero or one tenth of the switching frequency whichever is lower. fSW 25 kHz 10 (44) VOUT VIN 2 ) u( fZ _ RHP RLOAD u (D')2 IOUT VOUT 13.4 kHz 4 4 u 2S u LIN _ EQ 4 u 2S u LIN _ EQ (45) A 13.4 kHz crossover frequency is selected. RHP zero at minimum input voltage should be considered if the input voltage range is wide. STEP2: Determine required RCOMP Knowing fCROSS, RCOMP is calculated as follows: RCOMP fCROSS u S u RS u RFB2 u 10 u COUT u VOUT VIN 200 k: (46) A standard value of 200 kΩ is selected for RCOMP STEP3: Determine CCOMP to cancel load pole. Place the error amplifier zero at twice the load pole frequency. Knowing RCOMP, CCOMP is calculated as follows: RLOAD x COUT CCOMP 7.6nF 4 xRCOMP (47) A standard value of 8.2 nF is selected for CCOMP STEP4: Determine CHF to cancel the ESR zero. Knowing RCOMP, RESR and CCOMP, CHF is calculated as follows: RESR u COUT u CCOMP CHF 103 pF RCOMP u CCOMP RESR u COUT (48) A standard value of 100 pF is selected for CHF 36 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 LM5121/LM5121-Q1 www.ti.com SNVS963A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Figure 41. Schematic Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5121/LM5121-Q1 37 PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5121MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 MH LM5121MHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 MH LM5121MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 MH LM5121QMH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 QMH LM5121QMHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 QMH LM5121QMHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5121 QMH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LM5121, LM5121-Q1 : • Catalog: LM5121 • Automotive: LM5121-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5121MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 LM5121QMHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5121MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 LM5121QMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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