Fairchild FAN7317M Lcd backlight inverter drive ic Datasheet

FAN7317
LCD Backlight Inverter Drive IC
Features
Description
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
The FAN7317 is a LCD backlight inverter drive IC that
controls P-N full-bridge topology by using the new
patented phase-shift method.
High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range: 6V to 24V
Backlight Lamp Ballast and Soft Dimming
Minimal Required External Components
Precision Voltage Reference Trimmed to 2%
ZVS Full-Bridge Topology
Soft-Start
PWM Control at Fixed Frequency
Burst Dimming Function
Programmable Striking Frequency
Open-Lamp Protection
Open-Lamp Regulation
Arc Protection
Short-Lamp Protection
CMP-High Protection
High-FB Protection
Thermal Shutdown
20-Pin SOIC
The FAN7317 provides a low-cost solution and reduces
external components by integrating full wave rectifiers for
open-lamp protection and regulation (patent pending).
The operating voltage range of the FAN7317 is wide, so
an external regulator isn’t necessary to supply the
voltage to the IC.
The FAN7317 provides various protections, such as
open-lamp regulation, open-lamp protection, arc
protection, short-Lamp protection, CMP-high protection,
and FB-high protection, to increase the system reliability.
The FAN7317 provides burst dimming function and
analog dimming is possible, in a narrow range, by adding
some external components.
The FAN7317 is available in a 20-SOIC package.
Applications
ƒ
ƒ
LCD TV
LCD Monitor
Ordering Information
Part Number
Package
Operating Temperature
Packing Method
FAN7317M
20-SOIC
-25 to +85°C
RAIL
FAN7317MX
20-SOIC
-25 to +85°C
TAPE & REEL
All packages are lead free per JEDEC: J-STD-020B standard.
Protected under U.S. patent nos. 5,652,479 and 7,158,390.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
FAN7317 — LCD Backlight Inverter Drive IC
January 2008
Short Lamp Protection
Min.
OLR1
-
Disable @ striking
1ms delay (operation
@ burst dimming on)
+
0.3V
OUTA
Arc Protection
TSD 150oC
+
-
3V
OLR2
Min. &
Max.
Detector
/Full Wave
Recifier
OLR3
Over-Voltage Protection
Max.
Disable @ striking
OLR output 32 count
@ normal
Reset by BCT edge
detect
+
2V
+
2V
OLR4
OUTB
Protection
Output Driver
7V 0.2A/0.3A
dead time
200ns
1.6s delay @ striking
10ms delay @ normal
-
OUTC
0μA
+
1.8V
Error. Amp. source
current change
Open Lamp Regulation
2.2V
OUTD
1μA
-
Gm Amp.
+
Gm = 350, Max. current 85μA
max. 2V
Oscillator
Control
Logic
On @ striking
-
GND
+
CMP
Error. Amp. source
0μA sink current @ striking
current change
Error Amp.
+
Linear region 0~4V
-
3V
52μA burst
sink current on
High FB Protection
disable @ striking
3.5V
-
Striking off
5V, max. 3mA
Voltage Reference
& Internal Bias
REF
4 Output
Pulses
Counter
Min. & Max.
Detector
/Full Wave
Rectifier
max. 2V
OLP
OLP min.
1V/0.5V
Striking/normal
+
150μs
Delay
52μA burst
sink current on
+
OLP4
ENA
High_FB
OLP1
OLP3
1.35V
200k
+
OLP max.
OLP2
VIN
+
Hys. 0.45V
-
-
High_CMP
UVLO 5.5V
+
+
1.35V
-
High CMP Protection
disable @ striking
-
CT
min. 0.5V
min. 0.5V
BCT
BDIM
Figure 1. Internal Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
2
FAN7317 — LCD Backlight Inverter Drive IC
Block Diagram
FAN7317 — LCD Backlight Inverter Drive IC
Pin Configuration
F
Figure 2. Package Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
3
Pin #
Name
1
REF
This pin is 5V reference output. Typically, resistors are connected to this pin from CT pin
and BCT pin.
2
BDIM
This pin is the input for burst dimming. The voltage range of 0.5 to 2V at this pin controls
burst mode duty cycle from 0% to 100%.
3
BCT
This pin is for programming the frequency of the burst dimming. Typically, a capacitor is
connected to this pin from ground and a resistor is connected to this pin from the REF pin.
OLP1
This pin is for open-lamp protection and feedback control of lamp currents. It has the same
functions as other OLP pins and is connected to the full-wave rectifier internally. In striking
mode, if the minimum of rectified OLP inputs is less than 1V for 1.6s; or in normal mode, if
the minimum of rectified OLP inputs is less than 0.5V for 10ms; the IC shuts down to protect
the system in open lamp condition. The maximum of rectified OLP inputs is inputted to the
negative of the error amplifier for feedback control of lamp current.
5
OLR1
This pin is for open-lamp regulation. It has the same functions as other OLR pins and is
connected to the full-wave rectifier internally. When the maximum of rectified OLR inputs is
between 1.8V and 2V, the error amplifier output current is limited to 1µA; and when the
maximum of rectified OLR inputs reaches 2V, the error amplifier output current is 0A and its
output voltage maintains constant. The maximum of rectified OLR inputs is inputted to the
negative of another error amplifier for feedback control of lamp voltage. When the maximum
of rectified OLR inputs is more than 2.2V, another error amplifier for OLR is operating and
lamp voltage is regulated.
6
OLP2
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
7
OLR2
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
8
GND
This pin is the ground.
9
OUTB
This pin is NMOS gate-drive output.
10
OUTA
This pin is PMOS gate-drive output.
11
OUTC
This pin is PMOS gate-drive output.
12
OUTD
This pin is NMOS gate-drive output.
13
VIN
14
OLR3
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
15
OLP3
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
16
OLR4
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
17
OLP4
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
18
ENA
This pin is for turning on/off the IC.
19
CMP
Error amplifier output. Typically, a compensation capacitor is connected to this pin from the
ground.
20
CT
This pin is for programming the switching frequency. Typically, a capacitor is connected to
this pin from ground and a resistor is connected to this pin from the REF pin.
4
Description
This pin is the supply voltage of the IC.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
4
FAN7317 — LCD Backlight Inverter Drive IC
Pin Definitions
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VIN
IC Supply Voltage
TA
Operating Temperature Range
TJ
Operating Junction Temperature
TSTG
Storage Temperature Range
θJA
Thermal Resistance Junction-Air
PD
Power Dissipation
Min.
Max.
Unit
6
24
V
-25
+85
°C
+150
°C
+150
°C
90
°C/W
1.4
W
-65
(1,2)
Notes:
1. Thermal resistance test board. Size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.
2. Assume no ambient airflow.
Pin Breakdown Voltage
Pin #
Name
Value
1
REF
2
BDIM
Unit
Pin #
Name
Value
7
11
OUTC
24
7
12
OUTD
7
3
BCT
7
13
VIN
24
4
OLP1
±7
14
OLR3
±7
5
OLR1
±7
15
OLP3
±7
6
OLP2
±7
16
OLR4
±7
7
OLR2
±7
17
OLP4
±7
8
GND
7
18
ENA
7
9
OUTB
7
19
CMP
7
10
OUTA
24
20
CT
7
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
V
Unit
V
www.fairchildsemi.com
5
FAN7317 — LCD Backlight Inverter Drive IC
Absolute Maximum Ratings
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Start Threshold Voltage
4.9
5.2
5.5
V
Start Threshold Voltage Hysteresis
0.20
0.45
0.60
V
Under-Voltage Lockout Section (UVLO)
Vth
Vthhys
Ist
Start-up Current
VIN = 4.5V
70
100
µA
Iop
Operating Supply Current
VIN = 15V, Not switching
2.0
3.5
mA
5
V
0.7
V
120
170
µA
130
200
270
kΩ
4.9
5.0
5.1
V
ON/OFF Section
Von
On State Input Voltage
Voff
Off Stage Input Voltage
Isb
Stand-by Current
RENA
2
VIN = 15V, ENA = Low
Pull-down Resistor
Reference Section (Recommend 1µF X7R Capacitor)
5V Regulation Voltage
0 ≤ I5 ≤ 3mA
V5line
5V Line Regulation
6 ≤ VIN ≤ 24V
50
mV
V5load
5V Load Regulation
I5 = 3mA
50
mV
V5
Oscillator Section (Main)
fosc
fstr
Ictdcs
Ictdc
Oscillation Frequency
Oscillator Frequency in Striking Mode
CT Discharge Current
TA = 25°C, CT = 220pF,
RT = 100kΩ
93.9
97.0
100.5
CT = 220pF, RT =
100kΩ
93
97
101
TA = 25°C, CT = 220pF,
RT = 100kΩ
120
124
129
CT = 220pF, RT =
100kΩ
119
124
129
Striking
0.99
1.14
1.29
mA
Normal
740
840
940
μA
Striking
-15
-12
-9
μA
kHz
kHz
Ictcs
CT Charge Current
Vcth
CT High Voltage
2
V
Vctl
CT Low Voltage
0.4
V
Oscillator Section (Burst)
foscb
Burst Oscillation Frequency
TA = 25°C, BCT = 4.7nF,
BRT = 1.4MΩ
303
BCT = 4.7nF, BRT =
1.4MΩ
302
314
326
14
26
38
314
326
Hz
Ibctdc
BCT Discharge Current
Vbcth
BCT High Voltage
2
V
Vbctl
BCT Low Voltage
0.5
V
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
μA
www.fairchildsemi.com
6
FAN7317 — LCD Backlight Inverter Drive IC
Electrical Characteristics
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Error Amplifier Section
(3)
AV
Open-loop Gain
Gm
Error Amplifier Trans-conductance
lsin
Output Sink Current
lsur
Output Source Current
Ibsin
Burst CMP Sink Current
V135p
OLP Input Current
Iolpo
OLP Output Current
OLP Input Voltage Range
dB
20
40
60
µmho
OLP = 2.25V
-50
-35
-20
µA
OLP = 0.8V
12
22
32
µA
38
52
66
µA
1.275
1.350
1.421
1.255
1.350
1.444
OLP = 2V
-1
0
1
µA
OLP = -2V
-30
-20
-10
µA
4
V
-0.1
µA
TA = 25°C
1.35V Regulation Voltage
Iolpi
Volpr
37
(3)
-4
V
Open-Lamp Regulation Section
Iolr1
Iolr2
Error Amplifier Source Current for
Open-Lamp Regulation
Striking, OLR =
Volr1+0.05
-2.0
OLR = 2.1V
-1.0
0
µA
Volr1
Open-Lamp Regulation Voltage 1
Striking
1.65
1.80
1.95
V
Volr2
Open-Lamp Regulation Voltage 2
Striking
1.95
2.05
2.15
V
Volr3
Open-Lamp Regulation Voltage 3
2.1
2.2
2.3
V
OLR Error Amplifier Transconductance
200
350
500
µmho
GmOLR
Iolrsi
OLR Error Amplifier Sink Current
Normal, OLR = 2.5V
50
70
90
µA
Iolri
OLR Input Current
OLR = 1.5V
10
17
24
µA
Iolro
OLR Output Current
OLR = -1.5V
-25
-15
-7
µA
Volrr
OLR Input Voltage Range
4
V
(3)
-4
Note:
3. These parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
7
FAN7317 — LCD Backlight Inverter Drive IC
Electrical Characteristics (Continued)
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Protection Section
Volp0
Open-Lamp Protection Voltage 0
Volp1
Open-Lamp Protection Voltage 1
Vcmpr
Varcp
Open Lamp in Striking
0.95
1.00
1.05
V
Open Lamp
0.44
0.51
0.58
V
CMP-High Protection Voltage
2.95
3.05
3.15
V
Arc Protection Voltage
2.90
3.05
3.20
V
(4)
Vhfbp
High-FB Protection Voltage
Vslp
Short Lamp Protection Voltage
Tolps
Tolpn
Tcmprs
Tcmprn
(4)
(4)
Open-Lamp Protection Delay
(4)
High-CMP Protection Delay
(4)
Tolr
Open-Lamp Regulation Delay
Tslp
Short Lamp Protection Delay
TSD
Thermal Shutdown
(4)
3.4
3.5
3.6
V
0.24
0.32
0.40
V
Striking, foscb = 330Hz
1.6
s
Normal, fosc = 100kHz
10
ms
Striking, foscb = 330Hz
1.6
s
Normal, fosc = 100kHz
10
ms
Normal, fosc = 100kHz
320
µs
Normal, fosc = 100kHz
1
ms
150
°C
VIN
V
(4)
Output Section
(4)
Vpdhv
PMOS Gate High Voltage
Vphlv
PMOS Gate Low Voltage
Vndhv
NMOS Gate High Voltage
Vndlv
Vpuv
Vnuv
Ipdsur
Ipdsin
Indsur
Indsin
tr
tf
NMOS Gate Low Voltage
VIN = 15V
(4)
PMOS Gate Drive Source Current
VIN-7
VIN-7.5
V
VIN = 15V
6.5
7.0
7.5
V
VIN = 4.5V
(4)
NMOS Gate Drive Sink Current
0
(4)
(4)
V
VIN-0.3
V
VIN = 4.5V
(4)
NMOS Gate Drive Source Current
Rising Time
VIN-6.5
VIN = 15V
PMOS Gate Voltage with UVLO
Activated
NMOS Gate Voltage with UVLO
Activated
PMOS Gate Drive Sink Current
VIN = 15V
0.3
V
VIN = 15V
-200
mA
VIN = 15V
300
mA
VIN = 15V
200
mA
VIN = 15V
-300
mA
(4)
VIN = 15V, Cload = 2nF
70
ns
(4)
VIN = 15V, Cload = 2nF
70
ns
fosc = 100kHz
0
%
Falling Time
Maximum / Minimum Overlap
Minimum Overlap Between Diagonal
(4)
Switches
Maximum Overlap Between Diagonal
(4)
Switches
fosc = 100kHz
86
90
%
Dead Time
PDR_A/NDR_B
(4)
150
200
250
ns
(4)
150
200
250
ns
PDR_C/NDR_D
Note:
4. These Parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
8
FAN7317 — LCD Backlight Inverter Drive IC
Electrical Characteristics (Continued)
Figure 3. Start Threshold Voltage vs. Temp.
Figure 4. Start Threshold Voltage Hys. vs. Temp.
Figure 5. Start-up Current vs. Temp.
Figure 6. Operating Current vs. Temp.
Figure 7. Standby Current vs. Temp.
Figure 8. Pull-down Resistor vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
9
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics
Figure 9. 5V Regulation Voltage vs. Temp.
Figure 10. Oscillation Frequency vs. Temp.
Figure 11. Oscillation Frequency in Striking vs. Temp.
Figure 12. CT Discharge Current in Striking vs. Temp.
Figure 13. CT Discharge Current vs. Temp.
Figure 14. CT Charge Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
10
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
Figure 15. CT High Voltage vs. Temp.
Figure 16. CT Low Voltage vs. Temp.
Figure 17. Burst Dimming Frequency vs. Temp.
Figure 18. BCT Discharge Current vs. Temp.
Figure 19. BCT High Voltage vs. Temp.
Figure 20. BCT Low Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
11
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
Figure 21. Error Amp. GM vs. Temp.
Figure 22. Error Amp. Sink Current vs. Temp.
Figure 23. Error Amp. Source Current vs. Temp.
Figure 24. Burst CMP Sink Current vs. Temp.
Figure 25. 1.35V Regulation Voltage vs. Temp.
Figure 26. OLP Input Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
12
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
Figure 27. OLP Output Current vs. Temp.
Figure 28. Error Amp. Source Current 1 vs. Temp.
Figure 29. Error Amp. Source Current 2 vs. Temp.
Figure 30. OLR Error Amp. GM vs. Temp.
Figure 31. OLR Error Amp. Sink Current vs. Temp.
Figure 32. OLR Input Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
13
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
Figure 33. OLR Output Current vs. Temp.
Figure 34. Open-Lamp Protection Voltage1 vs. Temp.
Figure 35. High-CMP Protection Voltage vs. Temp.
Figure 36. Arc Protection Voltage vs. Temp.
Figure 37. Short Lamp Protection Voltage vs. Temp.
Figure 38. PMOS Gate Low Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
14
FAN7317 — LCD Backlight Inverter Drive IC
Typical Performance Characteristics (Continued)
UVLO: The under-voltage lockout (UVLO) circuit
guarantees the stable operation of the IC’s control circuit
by stopping and starting it as a function of the VIN value.
The UVLO circuit turns on the control circuit when VIN
exceeds 5.2V. When VIN is lower than 4.75V, the IC
start-up current is less than 100µA.
Burst Dimming Oscillator: The burst dimming timing
capacitor (BCT) is charged by the current flowing from
the reference voltage source, which is formed by the
burst dimming timing resistor (BRT) and the burst
dimming timing capacitor (BCT). The sawtooth waveform
charges up to 2V. Once the BCT voltage reaches 2V, the
capacitor begins discharging down to 0.5V. Next, the
BCT starts charging again and a new burst dimming
cycle begins, as shown in Figure 40. The burst dimming
frequency is programmed by adjusting the BCT and BRT
values. The burst dimming frequency is calculated as:
ENA: Applying voltage higher than 2V to the ENA pin
enables the IC. Applying voltage lower than 0.7V to the
ENA pin disables the IC.
f OSCB =
Main Oscillator: In normal mode, the external timing
capacitor (CT) is charged by the current flowing from the
reference voltage source, which is formed by the timing
resistor (RT) and the timing capacitor (CT). The sawtooth
waveform charges up to 2V. Once CT voltage reaches
2V, the CT begins discharging down to 0.4V. Next, the
CT starts charging again and a new switching cycle
begins, as shown in Figure 39. The main frequency is
programmed by adjusting the RT and CT value. The
main frequency is calculated as:
f OSC =
1
[Hz]
⎛ 3.864 ⋅ RT − 13800 ⎞
RT ⋅ CT ⋅ ln⎜
⎟
⎝ 2.52 ⋅ RT − 13800 ⎠
1
[Hz]
⎛ 0.039 ⋅ BRT − 4500 ⎞
BRT ⋅ BCT ⋅ ln⎜
⎟
⎝ 0.026 ⋅ BRT − 4500 ⎠
(3)
To avoid visible flicker, the burst dimming frequency
should be greater than 120Hz.
(1)
Figure 40. Burst Dimming Oscillator Circuit
Analog Dimming: For analog dimming, the lamp
intensity is controlled with the external dimming signal
(VADIM) and resistors. Figure 41 shows how to implement
an analog dimming circuit. The polarity of OLP1 should
be reversed with respect to OLP2.
Figure 39. Main Oscillator Circuit
In striking mode, the external timing capacitor (CT) is
charged by the current flowing from the reference
voltage source and 12μA current source, which
increases the frequency. If the product of RT and CT
value is constant, the striking frequency is depending on
CT and is calculated as:
f str =
1
⎛ 13.8 + (3I1 − 4.6I 2 )RT ⎞
⎜
⎟
⎜ − I1 ⋅ I 2 ⋅ RT 2
⎟
RT ⋅ CT ⋅ ln⎜
⎟
(
)
13.8
4.6I
3I
RT
+
−
1
2
⎜
⎟
⎜ − I ⋅ I ⋅ RT 2
⎟
⎝ 1 2
⎠
[Hz]
(2)
Q I1 = 12 ×10 -6 A, I 2 = 1.128 × 10 -3 A
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
15
FAN7317 — LCD Backlight Inverter Drive IC
Functional Description
R1
Fullbridge
output
R2
RS2
R2
R1
RS2
2V
T2
VBDIM
BCT
0.5V
0
RS1
CMP
0.5V
0
iLamp
RS1
0
Figure 41. Analog Implementation Circuit
VIN(V)
In full brightness, the maximum rms value of the lamp
current is calculated as:
i max
rms = 1.35
π
2 2 R S1
[A]
OUTA
VIN-7(V)
7V
OUTB
0
(4)
VIN(V)
OUTC
VIN-7(V)
7V
The lamp intensity is inversely proportional to VADIM. As
VADIM increases, the lamp intensity decreases and the
rms value of the lamp current is calculated as:
R1
VADIM [A ]
2 2 R S2 R 2
R + R2
R S1 [Ω]
= 1
R2
i rms = i max
rms −
Q R S2
OUTD
0
Figure 43. Burst Dimming Waveforms
π
Burst dimming can be implemented not only DC voltage,
but also using PWM pulse as the BDIM signal. Figure 44
shows how to implement burst dimming using PWM
pulse as BDIM signal.
(5)
Figure 42 shows the lamp current waveform vs. VADIM in
an analog dimming mode.
tch
tdch
b
b
i max
Lamp
i min
Lamp
Figure 42. Analog Dimming Waveforms
Figure 44. Burst Dimming Using an External Pulse
During striking mode, burst dimming operation is
disabled to guarantee continuous striking time. Figure 45
shows burst dimming is disabled during striking mode.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
16
FAN7317 — LCD Backlight Inverter Drive IC
Burst Dimming: Lamp intensity is controlled with the
BDIM signal over a wide range. When BDIM voltage is
lower than BCT voltage, the lamp current is turned on;
so, 0V on BDIM commands full brightness. The duty
cycle of the PWM pulse determines the lamp brightness.
The lamp intensity is inversely proportional to BDIM
voltage. As BDIM voltage increases, the lamp intensity
decreases. Figure 43 shows the lamp current waveform
vs. DIM in negative analog dimming mode.
T1
VBDIM
BCT
0.5V
0
CMP
0.5V
0
1V
OLP
Striking
mode
0
-1V
VIN(V)
OUTA
VIN-7(V)
7V
max
At the same time, while VOLR
is more than 2V, the
counter starts counting 32 rectified OLR pulses in normal
mode, then the IC enters shutdown, as shown in Figure
49. This counter is reset by detecting the positive edge
of BCT. This protection is disabled in striking mode to
ignite lamps reliably.
OUTB
0
VIN(V)
OUTC
VIN-7(V)
7V
OUTD
0
Figure 45. Burst Dimming During Striking Mode
Output Drives: FAN7317 uses the new phase-shift
method for full-bridge Cold Cathode Fluorescent Lighting
(CCFL) drive. As a result, the temperature difference
between the left and the right leg is almost zero,
because ZVS occurs in both of the legs by turns. The
detail timing is shown in Figure 46.
Figure 47. Open-Lamp Regulation in Striking Mode
CMP
2V OLR
2.2V OLR
0
2.2V
2V
OLR
0
-2V
-2.2V
iCMP
0
Figure 46. MOSFETs Gate Drive Signal
Figure 48. Open-Lamp Regulation in Normal Mode
Protections: The FAN7317 provides the following latchmode protections: Open-Lamp Regulation (OLR), Arc
Protection, Open-Lamp Protection (OLP), Short-Lamp
Protection (SLP), CMP-High Protection, and Thermal
Shutdown (TSD). The latch is reset when VIN falls to the
UVLO voltage or ENA is pulled down to GND.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
17
FAN7317 — LCD Backlight Inverter Drive IC
Open-Lamp Regulation: When the maximum of the
max
rectified OLR input voltages ( VOLR
) is more than 2V, the
IC enters regulation mode and controls CMP voltage.
The IC limits the lamp voltage by decreasing CMP
max
source current. If VOLR
is between 1.8V and 2V, CMP
source current decreases from 22µA to 1µA. Then, if
max
VOLR
reaches 2V, CMP source current decreases to
0µA, so CMP voltage remains constant and the lamp
voltage also remains constant, as shown in Figure 47.
max
Finally, if VOLR
is more than 2.2V, the error amplifier for
OLR is operating and CMP sink current increases, so
CMP voltage decreases and the lamp voltage maintains
the determined value.
2V
CMP
0
1.6s
0
Shut down
1V
OLP
2V
OLR
0
-1V
0
VIN(V)
OUTA
-2V
32 pulses counting
BCT
VIN-7(V)
7V
Shut down
OUTB
0
0
VIN(V)
Counter reset
OUTC
VIN-7(V)
7V
OUTA
OUTD
OUTB
0
0
OUTC
Figure 51. Open-Lamp Protection in Striking Mode
OUTD
0
5V
Figure 49. Over-Voltage Protection in Normal Mode
CMP
0
Arc Protection: If the maximum of the rectified OLR
max
input voltages ( VOLR
) is higher than 3V, the IC enters
shutdown mode without delay, as shown in Figure 50.
10ms
OLP
Shut down
0.5V
0
-0.5V
VIN(V)
CMP
OUTA
VIN-7(V)
7V
0
OUTB
3V
0
VIN(V)
OLR
OUTC
0
VIN-7(V)
7V
OUTD
Shut down
0
OUTA
Figure 52. Open-Lamp Protection in Normal Mode
OUTB
0
Short-Lamp Protection: If the minimum of the rectified
min
) is less than 0.3V in normal mode,
OLR voltages ( VOLR
the IC is shut down after a delay of 1ms, as shown in
Figure 53. This protection is disabled in striking mode to
ignite lamps reliably.
OUTC
OUTD
0
Figure 50. Arc Protection
Open-Lamp Protection: If the minimum of the rectified
min
) is less than 1V during initial
OLP voltages ( VOLP
operation, the IC operates in striking mode only for 1.6s,
min
is less than
as shown in Figure 51. After ignition, if VOLP
0.5V in normal mode, the IC is shut down after a delay of
10ms, as shown in Figure 52.
Figure 53. Short-Lamp Protection
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
18
FAN7317 — LCD Backlight Inverter Drive IC
5V
CMP
FAN7317 — LCD Backlight Inverter Drive IC
CMP-High Protection: If CMP is more than 3V in
normal mode, the IC is shut down after a delay of 10ms,
as shown in Figure 54. This protection is disabled in
striking mode to ignite lamps reliably.
Figure 54. CMP-High Protection
High-FB Protection: If the minimum of the rectified OLP
max
) is more than 3.5V, the counter starts
voltages( VOLP
counting eight rectified OLP pulses in normal mode, then
the IC enters shutdown, as shown in Figure 55. This
counter is reset by detecting the positive edge of BCT.
This protection is disabled in striking mode to ignite
lamps reliably.
CMP
0
3.5V
OLP
0
-3.5V
8 pulses counting
BCT
0
Shut down
Counter reset
OUTA
OUTB
0
OUTC
OUTD
0
Figure 55. High-FB Protection
Thermal Shutdown: The IC provides the function to
detect the abnormal over-temperature. If the IC
temperature exceeds approximately 150°C, the thermal
shutdown triggers.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
19
Application
Device
Input Voltage Range
Number of lamps
22-Inch LCD Monitor
FAN7317
13±10%
4
1. Features
20
19
18
17
16
15
14
13
12
11
CT
CMP
ENA
OLP4
OLR4
OLP3
OLR3
VIN
OUTD
OUTC
REF
BDIM
BCT
OLP1
OLR1
OLP2
OLR2
GND
OUTB
OUTA
3
4
5
6
7
8
9
10
BDIM(0~3.3V)
IC1
ON/OFF
2
High-Efficiency Single-Stage Power Conversion
P-N Full-Bridge Topology
Reduces Required External Components
Enhanced System Reliability through Protection Functions
1
ƒ
ƒ
ƒ
ƒ
Figure 56. Typical Application Circuit
2. Transformer Schematic Diagram
Figure 57. Transformer Schematic Diagram
3. Core & Bobbin
ƒ
ƒ
ƒ
Core: EFD2126
Material: PL7
Bobbin: EFD2126
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
20
FAN7317 — LCD Backlight Inverter Drive IC
Typical Application Circuit (LCD Backlight Inverter)
Pin No.
Wire
Turns
Inductance
Leakage Inductance
Remarks
5Æ2
1 UEW 0.4φ
17
250µH
16µH
1kHz, 1V
7Æ9
1 UEW 0.04φ
2256( =
0+0+376•6)
4.2H
290mH
1kHz, 1V
5. BOM of the Application Circuit
Part Ref.
Value
F1
24V 3A
Description
Part Ref.
C14
3.3n
50V 1608 K
FUSE
C15
100n
50V 1608 K
C17
1µ
50V 2012 K
1608 J
C18
4.7n
50V 1608 K
Fuse
Resistor (SMD)
R1
10k
Description
Value
R2
10k
1608 J
C19
3.3n
50V 1608 K
R3
200
1608 F
C21
3.3n
50V 1608 K
R5
100k
1608 F
R6
10k
1608 J
C4
3p
R7
200
1608 F
C13
3p
3KV
R8
75k
1608 J
C16
3p
3KV
R9
10k
1608 J
C20
3p
3KV
R10
8.2k
1608 J
Capacitor (DIP)
3KV
Electrolytic capacitor
R12
10k
1608 J
C1
220µ
25V
R13
200
1608 F
C2
220µ
25V
R14
1.5M
1608 F
R15
10k
1608 J
M1
FDD8424H
Fairchild Semiconductor
200
1608 F
M2
FDD8424H
Fairchild Semiconductor
R16
MOSFET (SMD)
Capacitor (SMD)
Wafer (SMD)
C3
1µ
50V 2012 K
CN1
12505WR-10
C5
1µ
50V 2012 K
CN2
35001WR-02A
C6
3.3n
50V 1608 K
CN3
35001WR-02A
C7
10µ
16V 3216
CN4
35001WR-02A
C8
10n
50V 1608 K
CN5
35001WR-02A
C9
10µ
16V 3216
C10
220p
50V 1608 K
TX1
EFD2126
C11
10n
50V 1608 K
TX2
EFD2126
C12
1µ
50V 2012 K
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
Transformer (DIP)
www.fairchildsemi.com
21
FAN7317 — LCD Backlight Inverter Drive IC
4. Winding Specification
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
0.51
0.35
1.27
0.25
M
10
0.65
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
0.10 C
0.30
0.10
X 45°
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 58. 20-SOIC Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
22
FAN7317 — LCD Backlight Inverter Drive IC
Physical Dimensions
FAN7317 — LCD Backlight Inverter Drive IC
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
23