CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
D Qualified for Automotive Applications
D Schmitt-Trigger Action on Each Input With
D
D
D
D
D
D
D 5-V, 10-V, and 15-V Parametric Ratings
D ESD Protection Level Per AEC-Q100
No External Components
Hysteresis Voltage Typically 0.9 V at
VDD = 5 V and 2.3 V at VDD = 10 V
Noise Immunity Greater Than 50%
No Limit on Input Rise and Fall Times
Standardized, Symmetrical Output
Characteristics
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1mA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25°C
D
Classification
− 2000-V (H2) Human-Body Model
− 200-V (M3) Machine-Model
− 1000-V (C5) Charge-Device Model
Applications
− Wave and Pulse Shapers
− High-Noise-Environment Systems
− Monostable Multivibrators
− Astable Multivibrators
− NAND Logic
M PACKAGE
(TOP VIEW)
A
B
J=A•B
K=C•D
C
D
VSS
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
H
G
M=G•H
L=E•F
F
E
description/ordering information
The CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate, with
Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going
signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis
voltage (VH) (see Figure 2).
The CD4093B is available in 14-lead small-outline plastic package (M96) and 14-lead thin shrink small-outline
packages (PWR suffixes).
ORDERING INFORMATION{
PACKAGE‡
TA
−40°C to 125°C
SOIC (M)
Reel of 2000
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
CD4093BQM96Q1
CD4093BQ
†
For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
functional block diagram
logic diagram
Figure 1. Hysteresis Definition, Characteristic, and Test Setup
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
VDD
VP
VN
VOL
VSS
Figure 2. Input and Output Characteristics
TYPICAL CHARACTERISTICS
Figure 3. Typical Current and Voltage Transfer
Characteristics
Figure 4. Typical Voltage Transfer Characteristics
as a Function of Temperature
Figure 5. Typical Output Low (Sink) Current
Characteristics
Figure 6. Minimum Output Low (Sink) Current
Characteristics
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
Figure 7. Typical Output High (Source) Current
Characteristics
Figure 9. Typical Propagation Delay Time
vs Supply Voltage
Figure 11. Typical Trigger Threshold Voltage
vs VDD
4
POST OFFICE BOX 655303
Figure 8. Minimum Output High (Source) Current
Characteristics
Figure 10. Typical Transition Time
vs Load Capacitance
Figure 12. Typical Percent Hysteresis
vs Supply Voltage
• DALLAS, TEXAS 75265
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
Figure 13. Typical Power Dissipation
vs Frequency Characteristics
Figure 14. Typical Power Dissipation
vs Rise and Fall Times
APPLICATION INFORMATION
Figure 15. Wave Shaper
Figure 16. Monostable Multivibrator
tA
To Control
Signal or
VDD
VDD
VSS
ƪǒ Ǔǒ Ǔƫ
t A + RCȏn
VVPP
VN
V DD*VN
V DD*VP
50 kΩ 3 R 3 1 MΩ
100 pF 3 C 3 1 µF
For the Range of R and C
Given 2 ms < tA < 0.4 s
VSS
Figure 17. Astable Multivibrator
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5
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
DC supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 20 V
Input voltage range, VI, all inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
DC input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Device dissipation per output transistor for TA, all package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW
Operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions‡
VCC
‡
6
Supply voltage range (TA = full package temperature range)
MIN
MAX
3
18
For maximum reliability, nominal operating conditions should be selected so that operation is always within the given range.
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UNIT
V
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
static electrical characteristics
CONDITIONS
CHARACTERISTIC
Quiescent device current,
current IDD max
Positive trigger theshold voltage,
voltage VP min
VP max
Negative trigger threshold voltage,
voltage VN min
VN max
Hysteresis voltage,
voltage VH min
VH max
VO
(V)
VI
(V)
LIMITS AT INDICATED TEMPERATURES (°C)
25
VDD
(V)
−40
40
85
125
MIN
UNIT
TYP†
MAX
0,5
5
1
30
30
0.02
1
0,10
10
2
60
60
0.02
2
0,15
15
4
120
120
0.02
4
0,20
20
20
600
600
0.04
20
A
5
2.2
2.2
2.2
2.2
2.9
A
10
4.6
4.6
4.6
4.6
5.9
A
15
6.8
6.8
6.8
6.8
8.8
B
5
2.6
2.6
2.6
2.6
3.3
B
10
5.6
5.6
5.6
5.6
7
B
15
6.3
6.3
6.3
6.3
9.4
A
5
3.6
3.6
3.6
2.9
A
10
7.1
7.1
7.1
5.9
7.1
A
15
10.8
10.8
10.8
8.8
10.8
B
5
4
4
4
3.3
4
B
10
8.2
8.2
8.2
7
8.2
B
15
12.7
12.7
12.7
9.4
12.7
A
5
0.9
0.9
0.9
0.9
1.9
A
10
2.5
2.5
2.5
2.5
3.9
A
15
4
4
4
4
5.8
B
5
1.4
1.4
1.4
1.4
2.3
B
10
3.4
3.4
3.4
3.4
5.1
B
15
4.8
4.8
4.8
4.8
7.3
A
5
2.8
2.8
2.8
1.9
2.8
A
10
5.2
5.2
5.2
3.9
5.2
A
15
7.4
7.4
7.4
5.8
7.4
B
5
3.2
3.2
3.2
2.3
3.2
B
10
6.6
6.6
6.6
5.1
6.6
B
15
9.6
9.6
9.6
7.3
9.6
A
5
0.3
0.3
0.3
0.3
0.9
A
10
1.2
1.2
1.2
1.2
2.3
A
15
1.6
1.6
1.6
1.6
3.5
B
5
0.3
0.3
0.3
0.3
0.9
B
10
1.2
1.2
1.2
1.2
2.3
B
15
1.6
1.6
1.6
1.6
3.5
A
5
1.6
1.6
1.6
0.9
1.6
A
10
3.4
3.4
3.4
2.3
3.4
A
15
5
5
5
3.5
5
B
5
1.6
1.6
1.6
0.9
1.6
B
10
3.4
3.4
3.4
2.3
3.4
B
15
5
5
5
3.5
5
µA
A
V
3.6
V
V
V
V
V
NOTES: A. Inputs on terminals 1, 5, 8, 12 or 2, 6, 9, 13; other inputs to VDD.
B. Inputs on terminals 1 and 2, 5 and 6, 8 and 9, or 12 and 13; other inputs to VDD.
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7
CD4093B-Q1
CMOS QUAD 2-INPUT NAND SCHMITT TRIGGER
SCLS608A − MARCH 2005 − REVISED APRIL 2008
static electrical characteristics (continued)
CONDITIONS
CHARACTERISTIC
VO
(V)
Output low (sink) current, IOL min
Output high (source) current
current, IOH min
Output voltage low level, VOL max
Output voltage high level, VOH min
Input current, IIN max
VI
(V)
LIMITS AT INDICATED TEMPERATURES (°C)
25
VDD
(V)
−40
40
85
125
MIN
UNIT
TYP†
0.4
0,5
5
0.61
0.42
0.36
0.51
1
0.5
0,10
10
1.5
1.1
0.9
1.3
2.6
1.5
0,15
15
4
2.8
2.4
3.4
6.8
4.6
0,5
5
−0.61
−0.42
−0.36
−0.51
−1
2.5
0,5
5
−1.8
−1.3
−1.15
−1.6
−3.2
9.5
0,10
10
−1.5
−1.1
−0.9
−1.3
−2.6
13.5
0,15
15
−4
−2.8
−2.4
−3.4
−6.8
MAX
mA
mA
0,5
5
0.05
0.05
0.05
0
0.05
0,10
10
0.05
0.05
0.05
0
0.05
0,15
15
0.05
0.05
0.05
0
0.05
0,5
5
4.95
4.95
4.95
4.95
5
0,10
10
9.95
9.95
9.95
9.95
10
0,15
15
14.95
14.95
14.95
14.95
0,18
18
±0.1
±1
±1
±10−5
V
V
±0.1
µA
dynamic electrical characteristics
TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ
TEST
CONDITIONS
CHARACTERISTIC
Propagation delay time, tPHL, tPLH
Transition time, tTHL, tTLH
Input capacitance, CIN
8
Any Input
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
LIMITS
VDD (V)
MIN
TYP
MAX
5
190
380
10
90
180
15
65
130
5
100
200
10
50
100
15
40
80
5
7.5
UNIT
ns
ns
pF
PACKAGE OPTION ADDENDUM
www.ti.com
15-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CD4093BQM96G4Q1
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD4093BQM96Q1
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4093B-Q1 :
CD4093B
• Catalog:
• Military: CD4093B-MIL
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Military - QML certified for Military and Defense Applications
Addendum-Page 1
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