AD AD9101 125 msps monolithic sampling amplifier Datasheet

a
125 MSPS Monolithic
Sampling Amplifier
AD9101
FEATURES
350 MHz Sampling Bandwidth
125 MHz Sampling Rate
Excellent Hold Mode Distortion
–75 dB @ 50 MSPS (25 MHz V IN)
–57 dB @ 125 MSPS (50 MHz VIN)
7 ns Acquisition Time to 0.1%
<1 ps Aperture Jitter
66 dB Feedthrough Rejection @ 50 MHz
3.3 nV/√Hz Spectral Noise Density
FUNCTIONAL BLOCK DIAGRAM
AD9101
–
+
SAMPLER
VIN
4X
AMP
CHOLD
+
VOUT
TE
–
3R
GENERAL DESCRIPTION
R
CLOCK
CLOCK
RTN
LE
APPLICATIONS
Direct IF Sampling
Digital Sampling Oscilloscopes
HDTV Cameras
Peak Detectors
Radar/EW/ECM
Spectrum Analysis
Test Equipment/CCD Testers
DDS DAC Deglitcher
A new application made possible by the AD9101 is direct IFto-digital conversion. Utilizing the Nyquist principle, the IF
frequency can be rejected, and the baseband signal can be
recovered. As an example, a 40 MHz IF is modulated by a
10 MHz bandwidth signal. By sampling at 25 MSPS, the signal
of interest is detected.
B
SO
The AD9101 is an extremely accurate, general purpose, high
speed sampling amplifier. Its fast and accurate acquisition speed
allows for a wide range of frequency vs. resolution performance.
The AD9101 is capable of 8 to 12 bits of accuracy at clock rates
of 125 MSPS or 50 MSPS, respectively. This level of performance makes it an ideal driver for almost all 8- to 12-bit A/D
encoders on the market today.
The benefits of using a track-and-hold ahead of a flash converter
have been well known for many years. However, before the
AD9101, there was no track-and-hold amplifier with sufficient
bandwidth and linearity to markedly increase the dynamic performance of such flashes as the AD9002, AD9012, AD9020,
and AD9060.
In effect, the AD9101 is a track-and-hold with a post amplifier.
This configuration allows the front end sampler to operate at
relatively low signal amplitudes. This results in dramatic improvement in both track and hold mode distortion while keeping
power low.
O
The gain-of-four output amplifier has been optimized for fast
and accurate large signal step settling characteristics even when
heavily loaded. This amplifier’s fast Settling Time Linearity
(STL) characteristic causes the amplifier to be transparent to
the low signal level distortion of the sampler. When sampled,
output distortion levels reflect only the distortion performance
of the sampler.
Dramatic SNR and distortion improvements can be realized
when using the AD9101 with high speed flash converters. Flash
converters generally have excellent linearity at dc and low frequencies. However, as signal slew rate increases, their performance degrades due to the internal comparators’ aperture delay
variations and finite gain bandwidth product.
The AD9101 is offered in commercial and military temperature
ranges. Commercial versions include the AD9101AR in plastic
SOIC and AD9101AE in ceramic LCC. Military devices are
available in ceramic LCC. Contact the factory for availability of
versions in DIP and/or military versions.
PRODUCT HIGHLIGHTS
1. Guaranteed Hold-Mode Distortion
2. 125 MHz Sampling Rate to 8 Bits; 50 MHz to 12 Bits
3. 350 MHz Sampling Bandwidth
4. Super-Nyquist Sampling Capability
5. Output Offset Adjustable
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD9101–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V = +5 V, –V = –5.2 V, R
S
Parameter
DC ACCURACY
Gain
Offset
Output Resistance
Output Drive Capability
PSRR
Pedestal Sensitivity to Positive Supply
Pedestal Sensitivity to Negative Supply
S
Temp
Test
Level
∆VIN = 0.5 V
∆VIN = 0.5 V
VIN = 0 V
VIN = 0 V
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Full
I
VI
I
VI
V
VI
VI
V
V
∆VS = 0.5 V p-p
∆VS = 0.5 V p-p
∆VS = 0.5 V p-p
Feedthrough Rejection (50 MHz)
TRACK-TO-HOLD SWITCHING
Aperture Delay
Aperture Jitter
Pedestal Offset
Transient Amplitude
Settling Time to 4 mV
Glitch Product5
HOLD-TO-TRACK SWITCHING
Acquisition Time to 0.1%
Acquisition Time to 0.01%
POWER SUPPLY
+VS Current
–VS Current
Power Dissipation
3.93
3.9
± 60
37
AD9101
Typ
4
±3
Max
Units
4.07
4.1
± 10
± 15
V/V
V/V
mV
mV
Ω
mA
dB
mV/V
mV/V
0.4
± 70
43
4
8
± 2.4
30
25
LE
VI
I
VI
V
VI
VI
± 2.7
±5
Full
Full
Full
VI
VI
VI
VOUT = 1 V p-p
4 Volt Output Step
VIN = ± 1 V to 0 V
(5 MHz–200 MHz)
Full
Full
25°C
25°C
25°C
IV
IV
V
V
V
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VIN = 0.5 V p-p
V
IV
IV
IV
V
V
V
I
VI
V
–75
–62
VOUT = 2 V p-p
25°C
25°C
Full (Ind.)
Full (Mil.)
25°C
25°C
Full
25°C
Full
Full
VIN = 0 V
VIN = 0 V
VIN = 0 V
VIN = 0 V
VIN = 0 V
25°C
25°C
25°C
Full
Full
Full
25°C
V
V
I
VI
V
V
V
–250
<1
±5
2 V Output Step
2 V Output Step
2 V Output Step
25°C
25°C
Full
V
IV
IV
7
11
Full
Full
Full
VI
VI
VI
55
59
570
–2–
3
–1.8
–1.0
160
1300
± 15
± 20
2
125
CL/CL = –1.0 V
VIN = 0.5 V p-p
VIN = 0.5 V p-p
B
SO
O
HOLD MODE DYNAMICS
Worst Harmonic (23 MHz, 50 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 125 MSPS)
Sampling Bandwidth (–3 dB)3
Hold Noise4 (RMS)
Droop Rate
Min
TE
Full
25°C
Full
25°C
25°C–TMAX
TMIN
Input Capacitance
Input Resistance
TRACK MODE DYNAMICS
Bandwidth (–3 dB)
Slew Rate
Overdrive Recovery Time2 (to 0.1%)
Integrated Output Noise
Input RMS Spectral Noise @ 10 MHz
= 100 V, RlN = 50 V unless otherwise noted)
Conditions
ANALOG INPUT/OUTPUT
Output Voltage Range
Input Bias Current
CLOCK/CLOCK INPUTS
Input Bias Current
Input Low Voltage (VIL)1
Input High Voltage (VIH)1
LOAD
3.6
–1.5
–0.8
250
1800
55
210
3.3
–57
350
150 × tH
±5
V
µA
µA
pF
kΩ
kΩ
mA
V
V
MHz
V/µs
ns
µV
µV/√Hz
–57
–53
–51
± 18
± 40
–66
± 20
± 35
8
4
20
dBFS
dBFS
dBFS
dBFS
dBFS
MHz
mV/s
mV/µs
mV/µs
dB
ps
ps rms
mV
mV
mV
ns
pV-s
14
16
ns
ns
ns
70
73
715
mA
mA
mW
REV. 0
AD9101
NOTES
1
If the analog input exceeds ± 300 mV, the clock levels should be shifted as shown in the Theory of Operation section entitled “Driving the Encode Clock.”
2
Time to recover within rated error band from 160% overdrive.
3
Sampling bandwidth is defined as the –3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than
tracking bandwidth because it does not include the bandwidth of the output amplifier.
4
Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H) is 20 ns, the accumulated noise is typically 3 µV
(150 mV/s × 20 ns). This value must be combined with the track mode noise to obtain total noise.
5
Total energy of worst case track-to-hold or hold-to-track glitch.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Pin Description
Description
Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RTN
RTN
CB+
+VS
+VS
GND
GND
+VS
+VS
CLK
CLK
–VS
–VS
N/C
VIN
GND
–VS
–VS
CB–
VOUT
Gain Set Resistor Return*
Gain Set Resistor Return*
Bootstrap Capacitor (Positive Bias)
+5 V Power Supply (Analog)
+5 V Power Supply (Analog)
Hold Capacitor Ground
Hold Capacitor Ground
+5 V Power Supply (Digital)
+5 V Power Supply (Digital)
True ECL T/H Clock
Complement ECL T/H Clock
–5.2 V Power Supply (Digital)
–5.2 V Power Supply (Digital)
No Connection
Analog Signal Input
Ground (Signal Return)
–5.2 V Power Supply (Analog)
–5.2 V Power Supply (Analog)
Bootstrap Capacitor (Negative Bias)
Analog Signal Output
B
SO
LE
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (no air flow, soldered to PC board) are as follows:
Ceramic LCC: θJA = 48°C/W; θJC = 9.9°C/W; Plastic SOIC: θJA = 54°C/W;
θJC = 7.3°C/W.
3
For surface mount devices, mounted by vapor phase soldering. Prior to vapor phase
soldering, plastic units should receive a minimum eight hour bakeout at 110 °C to
drive off any moisture absorbed in plastic during shipping or storage. Through-hole
devices can be soldered at +300°C for 10 seconds.
4
Output is short circuit protected to ground. Continuous short circuit may affect
device reliability.
Pin
TE
Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . –0.5 V to +6 V
Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –6 V to +0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V
CLOCK/CLOCK Input . . . . . . . . . . . . . . . . . –5 V to +0.5 V
Continuous Output Current4 . . . . . . . . . . . . . . . . . . . . 70 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AE, AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Junction Temperature (Ceramic)2 . . . . . . . . . . . . . . . +175°C
Junction Temperature (Plastic)2 . . . . . . . . . . . . . . . . +150°C
Soldering Temperature (1 minute)3 . . . . . . . . . . . . . . +220°C
*See “Matching the AD9101 to A/D Encoders.” Both pins should either be
grounded or connected to voltage source for offset.
EXPLANATION OF TEST LEVELS
Model
Temperature
Range
Package
Description
Package
Option
AD9101AR
AD9101AE
AD9101SE
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Plastic SOIC
LCC
LCC
R-20
E-20A
E-20A
2
19 CB–
–3–
2
3
4
+VS
–VS
17
5
+VS
GND
16
6
GND
16 GND
VIN
15
7
GND
15 V
IN
NC
14
8
+VS
4
+VS
5
AD9101
GND
6
TOP VIEW
(Not to Scale)
GND
7
14 NC
+VS
8
13 –V S
+VS
9
12 –V S
CLK 10
11 CLK
BOTTOM VIEW
13 12 11 10 9
+VS
17 –V S
+VS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
1
18
18 –V S
3
19 20
–VS
CLK
CB+
RTN
RTN
CB+
20 VOUT
VOUT
1
RTN
RTN
20-Contact Ceramic LCC
CB–
20-Pin SOIC
CLK
ORDERING INFORMATION
PIN CONFIGURATIONS
–VS
O
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
–VS
Test Level
WARNING!
ESD SENSITIVE DEVICE
AD9101
Hold-to-Track Switch Delay is the time delay from the track
command to the point when the output starts to change to acquire a new signal level.
Acquisition Time is the amount of time it takes the AD9101
to reacquire the analog input when switching from hold to track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
Pedestal Offset is the offset voltage measured immediately after the AD9101 is switched from track to hold with the input
held at zero volts. It manifests itself as a dc offset during the
hold time.
Aperture Delay establishes when the input signal is actually
sampled. It is the time difference between the analog propagation delay of the front-end buffer and the control switch delay
time (the time from the hold command transition to when the
switch is opened). For the AD9101, this is a negative value,
meaning that the analog delay is longer than the switch delay.
Sampling Bandwidth is the –3 dB frequency response from
the input to the hold capacitor under sampling conditions. It is
greater than the tracking bandwidth because it does not include
the bandwidth of the output amplifier which is optimized for
settling time rather than bandwidth.
Aperture Jitter is the random variation in the aperture delay.
This is measured in ps-rms and is manifested as phase noise on
the held signal.
TE
Track-to-Hold Settling Time is the time necessary for the
track to hold switching transient to settle to within 4 mV of its
final value.
Droop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9101 output with the device in hold mode and the input held at a specified dc value; the
measurement starts immediately after the T/H switches from
track to hold.
Track-to-Hold Switching Transient is the maximum peak
switch induced transient voltage which appears at the AD9101
output when it is switched from track to hold.
B
SO
+2V
LE
Feedthrough Rejection is the ratio of the output signal to the
input signal when in hold mode. This is a measure of how well
the switch isolates the input signal from feeding through to the
output.
ANALOG
INPUT (x 4)
APERTURE
DELAY
(–0.25 ns)
VOLTAGE
LEVEL HELD
0V
ACQUISITION
TIME (SEE
TEXT)
-2V
+2V
O
SAMPLER OUTPUT SIGNAL (x 4)
AND AMPLIFIER OUTPUT SIGNAL
HOLD TO TRACK
SWITCH DELAY
TIME (1.5 ns)
OBSERVED AT
HOLD CAPACITOR
OBSERVED AT
AMPLIFIER OUTPUT
0V
TRACK TO
HOLD
SETTLING
(4 ns)
-2V
CLOCK
CLOCK
CLOCK
"HOLD"
"TRACK"
"HOLD"
"1"
CLOCK
INPUTS
"0"
Timing Diagram (500 ps/div)
–4–
REV. 0
AD9101
THEORY OF OPERATION
VHC
The AD9101 employs a new and unique track-and-hold architecture. Previous commercially available high speed track-andholds used an open loop input buffer, followed by a diode
bridge, hold capacitor, and output buffer (closed or open loop)
with a FET device usually connected to the hold capacitor. This
architecture required mixed device technology and, usually, hybrid construction. The sampling rate of these hybrids has been
limited to 20 MSPS for 12-bit accuracy. Distortion generated in
the front-end amplifier/bridge limited the dynamic range performance to the “mid –70 dBFS” for analog input signals of less
than 10 MHz. Broadband and switch-generated noise limited
the SNR of previous track-and-holds to about 70 dB.
VOUT
AMP
SAMPLER
HC
TRACK-TO-HOLD
INDUCED GLITCH
VHC
VOUT
ACQUISITION TIME
AT HC TO X%
tDHT
1.5ns
TS
TE
TRACK
HOLD
Figure 1. Acquisition Time at Hold Capacitor
during the track time. However, since the output amplifier always “tracks” the front end circuitry, it “catches up” and directly superimposes itself (less about 500 ps of analog delay) to
VHC. Since the small signal settling time of the output amplifier
can be about 1.2 ns to ± 1 mV, and is significantly less than the
hold time, acquisition time should be referenced to the hold
capacitor.
LE
The AD9101 is a monolithic device using a high frequency
complementary bipolar process to achieve new levels of high
speed precision. Its architecture completely breaks from the traditional architecture described above. The hold switch has been
integrated into the first stage closed-loop buffer. This innovation provides error (distortion) correction for both the switch
and buffer while still achieving slew rates representative of an
open-loop design. In addition, acquisition slew current for the
hold capacitor is higher than the traditional diode bridge switch
configurations, removing a main contributor to the limits of
maximum sampling rate, input frequency, and distortion.
The closed-loop output amplifier includes zero voltage bias current cancellation, which results in high-temperature droop rates
close to those found in FET type inputs. This closed-loop amplifier inherently provides high speed loop correction and has
extremely low distortion even when heavily loaded.
B
SO
Extremely fast time constant linearity (7 ns to 0.01% for a 4 V
output step) ensures that the output amplifier does not limit the
AD9101 sampling rate or analog input frequency. (The acquisition and settling time are primarily limited only by the input
sampler.) The output is transparent to the overall AD9101 hold
mode distortion levels for loads as low as 50 Ω.
Most of the hold settling time and output acquisition time are
due to the sampler and the switch network. (Output acquisition
time is as seen on a scope at the output. This is typically 1.7 ns
longer than actual acquisition time.) For track time, the output
amplifier contributes only about 5 ns of the total; in hold mode,
it contributes 1.7 ns (as stated above).
Full-scale track and acquisition slew rates achieved by the
AD9101 are 1800 V/µs and 1700 V/µs, respectively. When combined with excellent phase margin (typically 5% overshoot),
wide bandwidth, and dc gain accuracy, acquisition time to
0.01% is only 11 ns.
Acquisition Time
O
Acquisition time is the amount of time it takes the AD9101 to
reacquire the analog input when switching from hold-to-track
mode. The interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified error band at the hold capacitor.
The hold-to-track switch delay (tDHT) cannot be subtracted
from this acquisition time for 12-bit performance because it is a
charging time and analog output delay that occurs when moving
from hold to track; this delay is typically 1.5 ns. Therefore, the
track time required for the AD9101 is the acquisition time
which includes tDHT. Note that the acquisition time is defined as
the settled voltage at the hold capacitor and does not include the
delay and settling time of the output amplifier. The example in
Figure 1 illustrates why the output amplifier does not contribute
to the overall acquisition time.
The exaggerated illustration in Figure 1 shows that VHC has
settled to within x% of its final value, but VOUT (due to slew rate
limitations, finite BW, power supply ringing, etc.) has not settled
REV. 0
A stricter definition of acquisition would actually include both
the acquisition and track-to-hold settling times to a defined accuracy. To obtain 12-bit+ distortion levels and 50 MSPS operation, the minimum recommended track and hold times are
12 ns and 8 ns, respectively. To drive an 8-bit flash converter
(such as the AD9002) with a 2 V p-p full-scale input, hold time
to 1 LSB accuracy will be limited primarily by the aperture time
of the encoder, rather than by the AD9101. This makes it possible to reduce track time to as little as 5 ns, with hold time chosen to optimize the encoder’s performance.
Though acquisition time and track-to-hold settling time to
1/2 LSB (0.4%) accuracy are 6 ns and 4 ns respectively, it is still
possible to achieve –45 dB SNR performance at clock speeds to
125 MSPS. This is because the settling error is roughly proportional to the signal level and is partially cancelled due to the
high phase margin of the input sampler.
Hold vs. Track Mode Distortion
In many traditional high speed, open-loop track-and-holds,
track mode distortion is often much better than hold mode distortion. Track mode distortion does not include nonlinearities
due to the switch network, and does not correlate to the relevant
hold mode distortion. But since hold mode distortion has traditionally been omitted from manufacturer’s specification tables,
users have had to discover for themselves the effective overall
hold mode distortion of the combined T/H and encoder.
–5–
AD9101
The architecture of the AD9101 minimizes hold mode distortion over its specified frequency range. As an example, in track
mode the worst harmonic generated for a 20 MHz input tone is
typically –65 dBFS. In hold mode, under the same conditions
and sampling at 50 MSPS, the worst harmonic generated is
–75 dBFS. The reason is the output amplifier in hold mode has
only a dc distortion relevancy. With its inherent linearity (7 ns
settling to 0.01%), the output amplifier has essentially settled to
its dc distortion level even for track plus hold times as short as
20 ns. For a traditional open-loop output buffer, the ac (track
mode) and dc (hold mode) distortion levels are often the same.
should be removed from around the VIN and VOUT pins to minimize coupling onto the analog signal path.
While a single ground plane is recommended, the analog signal
and differential ECL clock ground currents follow a narrow path
directly under their common voltage signal line. To reduce reflections, especially when terminations are used for transmission
line efficiency, the clock, VIN, and VOUT signals and respective
ground paths should not cross each other; if they do, unwanted
coupling can result. Analog terminations should be kept as far as
possible from the power supply decoupling capacitors to minimize supply current spike feedthrough.
Droop rate does not necessarily affect a track-and-hold’s distortion characteristics. If the droop rate is constant versus the input
voltage for a given hold time, it manifests itself as a dc offset
to the encoder. For the AD9101, the droop rate is typically
3 mV/µs. If a signal is held for 1 µs, a subsequent encoder will
see a 3 mV offset voltage. If there is no droop sensitivity to the
held voltage value, the offset would be constant and “ride” on
the input signal and introduce no hold-mode nonlinearities.
The AD9101 requires a differential ECL clock command. Due
to the high gain bandwidth of the AD9101 internal switch, the
input clock should have a slew rate of at least 400 V/µs.
To obtain maximum signal to noise performance, especially at
high analog input frequencies, a low jitter clock source is required. The AD9101 clock can be driven by an AD96685, an
ultrahigh speed ECL comparator with very low jitter.
Figure 2 illustrates a recommended termination for the differential encode clock inputs of the AD9101. The 40 Ω RLS is required to level shift the ECL voltages more negative. This
increases the linear signal range of the sampler. When the input
is less than 600 mV (2.4 V p-p output), these level shift resistors
are not required.
LE
When droop rate varies proportionately to the level of the held
voltage signal level, only a gain error is introduced to the A/D
encoder. The AD9101 has a droop sensitivity to the input level
of 20 mV/V µs. For a 2 V p-p output signal, this translates to a
1%/µs gain error and does not cause additional distortion errors.
However, hold times longer than about 500 ns can cause distortion due to the R × HC time constant at the hold capacitor. In
addition, hold mode noise will increase linearly vs. hold time
and thus degrade SNR performance.
RLS
40
B
SO
Layout Considerations
Driving the Encode Clock
TE
Droop Rate
For best performance results, good high speed design techniques must be applied. The component (top) side ground
plane should be as large as possible; two-ounce copper cladding
is preferable. All runs should be as short as possible, and decoupling capacitors must be used.
CLK
CLK
10
11
510
–5.2 V
RLS
40
510
–5.2 V
Figure 2. Recommended Encode Clock Termination
The schematic of a recommended AD9101 evaluation board is
shown. (Contact factory concerning availability of assembled
boards.) All 0.01 µF decoupling capacitors should be low inductance surface mount devices (P/N 05085C103MT050 from
AVX) and connected with short lead lengths to minimize stray
inductance.
When driving the encode clock from a remote circuit via
transmission lines, or where stray capacitance exceeds 2 pF,
Thevenin equivalent terminations should be used (270 Ω to
–5.2 V and 160 Ω to ground). For this 100 Ω equivalent termination, RLS should be 20 Ω.
Driving the Analog Input
O
The 10 µF, low frequency tantalum power supply decoupling
capacitors should be located within 1.5 inches of the AD9101.
The common 0.01 µF supply capacitors can be wired together.
The common power supply bus (connected to the 10 µF capacitor and power supply source) can be routed to the underside of
the board to the daisy chain wired 0.01 µF supply capacitors.
Special care must be taken to ensure that the analog input signal
is not compromised before it reaches the AD9101. To obtain
maximum signal to noise performance, a very low phase noise
analog source is required. In addition, input filtering and/or a
low harmonic signal source is necessary to maximize the spurious free dynamic range. Any required filtering should be located
close to the AD9101 and away from digital lines.
For remote input and/or output drive applications, controlled
impedances are required to minimize line reflections which will
reduce signal fidelity. When capacitive and/or high impedance
levels are present, the load and/or source should be physically
located within approximately one inch of the AD9101. Note
that a series resistance, RS, is required if the load is greater than
6 pF. (The Recommended RS vs. CL chart in the “Typical Performance Section” shows values of RS for various capacitive
loads which result in no more than a 20% increase in settling
time for loads up to 80 pF.) For best results when driving
heavily capacitive or low resistance loads, the AD9630 buffer is
strongly suggested. As much of the ground plane as possible
Matching the AD9101 to A/D Encoders
The AD9101’s analog output level may have to be offset or amplified to match the full-scale range of a given A/D converter.
This can generally be accomplished by inserting an amplifier after the AD9101. For example, the AD671 is a 12-bit 500 ns
monolithic ADC encoder that requires a 0 V to +5 V full-scale
analog input. An AD84X series amplifier could be used to condition the AD9101 output to match the full-scale range of the
AD671.
The AD9101 can perform a dc level shift function when its input
is bipolar and the ADC requires a unipolar signal. The AD9002
–6–
REV. 0
AD9101
provides a good example. It operates on a single negative supply
with the input range from 0 V to –2 V. By connecting Pins 1
and 2 (RTN) to a +0.33 V level, rather than its usual ground
connection, a bipolar ± 0.25 V input is shifted to 0 V to –2 V at
the AD9101’s output (see Figure 3 in the Applications section.)
A
–70
WORST HARMONIC
SNR W/HARMONICS
–65
–60
–55
dB
APPLICATIONS
Because of its rapid acquisition and low distortion, the AD9101
is useful in a wide range of signal processing.
–40
The first obvious difference between the AD9100 and AD9101
is sample rate. Simplistically, any high resolution system (12–16
bits) operating below 25 MSPS will use the AD9100 and 8–12
bit systems operating above 25 MSPS will use the AD9101.
There are, however, some subtle characteristics of these high
performance track-and-hold amplifiers that create some exceptions to these guidelines. The typical curve entitled “Dynamic
Range vs. Analog Frequency” should be considered when
choosing between these two high performance track-and-holds.
–35
10
100
TE
MHz
Figure 4. AD9002 Dynamic Range With and Without
AD9101
27Ω
AD9630
LE
AD9101
AD9060
CLOCK 2
CLOCK 1
CLOCK 1
Flash ADCs typically suffer degradation of dynamic range as
signal frequency increases. The AD9101 was designed specifically for the purpose of boosting this performance and allowing
users to obtain maximum performance with flash ADCs. Figure
3 shows the block diagram and timing relationship for an 8-bit,
125 MSPS converter.
8.5 ns
"HOLD"
"HOLD"
8.5 ns
8 ns
"TRACK"
B
SO
1k
ENCODE = 125 MSPS
–30
1
When speed is critical, the AD9101 should receive strong consideration, even in high resolution systems. Using a reduced signal amplitude through the AD9100 greatly reduces slew limiting
effects and should also be considered when converting high frequency (up to 70 MHz) analog signals with encode rates below
25 MSPS.
+5V
WITH AD9101
–50
–45
Choosing Between the AD9100 and AD9101
Sampler for Flash ADC
WITH AD9101
"TRACK"
8 ns
8.5 ns
"TRACK"
2.5 ns
"HOLD"
CLOCK 2
8.25 ns
"HOLD"
8.25 ns
8.25 ns
"TRACK"
"HOLD"
8.25 ns
8.25 ns
"TRACK"
Figure 5. AD9101 with 10-Bit, 75 MSPS ADC
0.33V
3k
–70
+
1k
–
–65
RTN
–60
40Ω
O
CLOCK 1
HOLD
CLOCK 1
(AD9101)
3.6 ns
4.4 ns
–45
TRACK
ENCODE = 60 MSPS
–35
HOLD
HOLD
HOLD
–30
3.5 ns
4.5 ns
TRACK
3.5 ns
4.5 ns
3.5 ns
1
Figure 4 contrasts performance of the flash converter alone vs.
the circuit of Figure 3.
10
100
MHz
TRACK
Figure 3. AD9101 with 8-Bit, 125 MSPS Flash
Figure 6. AD9060 Dynamic Performance With and Without AD9101
Figures 5 and 6 show the block diagrams and dynamic range
improvement when the AD9101 is used ahead of an 10-bit, 75
MSPS flash converter. The AD9630 is not required if the input
frequency is limited to 40 MHz.
REV. 0
–50
3.6 ns
44 ns
1.6 ns
CLOCK 2
(AD9002)
–55
–40
TRACK
TRACK
CLOCK 2
HOLD
3.6 ns
WITH AD9101
AD9002
AD9101
dB
AC
WORST
HARMONIC
SNR W/
HARMONICS
WITH AD9101
0.1µF
–7–
AD9101
Thus, the final IF signal was mixed with quadrature signals
from the final LO. The two resultant baseband signals representing I and Q were digitized by independent converters.
Deglitcher
Many recently announced video-speed digital-to-analog converters feature very low glitch impulse. This is the result of design emphasis on spurious free dynamic range (SFDR), a key
spec for the emerging direct digital synthesis (DDS) market.
These DACs have extremely low spurs and often do not require
deglitching.
Q
12
DDS
ACCUMULATOR
(AD9955)
DAC
(AD9713)
CLK1
SAMPLING
AMPLIFIER
(AD9101)
CLK2
IF
BPF
LOCAL
OSC.
ADC
DSP
I
QUADRATURE
DEMODULATOR
TE
32
ANALOG
INPUT
BASEBAND
ADCs
90°
Although their specs are impressive, these DACs may suffer harmonic distortion, especially at higher clock rates. Therefore, a
deglitcher using the AD9101 can improve SFDR in some cases.
Figure 7 illustrates the block diagram for deglitching an
AD9713, 12-bit DAC.
TUNING
WORD
MATCHED LPF
WITH GAIN
ADC
Figure 8. Traditional l-Q Demodulation
LOW
DISTORTION
OUTPUT
This method, shown in block form in Figure 8, relies heavily on
accuracy of the phase of the analog I and Q signals applied to
the ADCs. As little as 0.5° of phase error can reduce system dynamic range by 6 dB or more.
CLK3
Figure 7. Deglitcher Block Diagram
IF-to-Digital Conversion
LE
Using the bandwidth and low distortion of the AD9101 greatly
simplifies the analog front end and allows signal processing to
be done in the digital domain which is more predictable and less
susceptible to environmental changes. The simplified front end
is illustrated in Figure 9.
Traditional receivers with information encoded with in phase (I)
and quadrature (Q) signals comprise extensive analog signal
processing ahead of the pair of ADCs.
This I-Q demodulation in the analog domain requires precise
gain and phase matching as well as close matching of the ADCs.
This leads to high cost both in materials and labor to attain the
desired performance. Digital front end designers have paid the
cost for these components because ADCs have limited the dynamic range at higher signal frequencies.
O
ANALOG
INPUT
IF
BPF
12
AD9101
ADC
H (z)
NUMERICALLY
CONTROLLED
OSCILLATOR
(NCO)
Q
DIGITAL
FILTER
B
SO
This configuration removes the burden from the analog section.
The AD9101 expands the dynamic range of the ADC into the
IF bandwidth, allowing straightforward digital algorithms to demodulate the I and Q data.
H (z)
DSP
I
Figure 9. Direct IF-to-Digital
–8–
REV. 0
AD9101
–V S
+VS
3.0 (76.2)
C1
+
1
2
RTN
CB–
CB+
4
5
6
–V S
+VS
–V S
+VS
GND
GND
VIN
GND
NC
+VS
–V S
H2
20
R1
19
27
9
–V S
+VS
18
C7
17
16
13
4
OUT
Q
6
12
R7, 270
R5, 270
–5.2 V
B
SO
LE
NOTES
1. ALL CAPACITORS ARE 0.01 mF UNLESS OTHERWISE
DESIGNATED. SURFACE-MOUNT CAPS PREFERRED.
2. R1 SHOULD BE SELECTED BASED ON CL AND MAY BE
SHORTED FOR CAPACITIVE LOADS OF LESS THAN 6 pF.
3. C1 SHOULD A LOW INDUCTANCE 0.01 mF WITH
CIRCUIT LEADS AS SHORT AS POSSIBLE.
4. PINOUTS FOR AD9101 AND AD96685 ARE FOR SOIC.
Evaluation Circuit
Component Side
O
EVALUATION BOARD ORDERING GUIDE
Part Number
Description
AD9101/PCB
AD9101/PWB
Fully Populated and Tested Evaluation Board
Printed Circuit Board without Components
Ground Plane Bottom
REV. 0
–9–
J1
VIN
C9 U1
R4,160
Q
–
R7
LE
U1
AD96685BR
R3
51
C7 R5
R4 C4
AD9101 Layout
R6,160
11
R2
H1
R2
51
+
C9
C3
R3
C8
CLK
CLK
C1 R1
C5
VIN
3
C6
AD9101
EVALUATION
BOARD
J2
CLOCK IN
15
12
H3
J3
VOUT
11
10
–5.2V
C2
J1
CLOCK
INPUT
GND
TE
8
J2
+5V
VOUT
14
7
C4
VOUT
AD9101
3
C3
RTN
C6
10 µF
3.5 (88.9)
+
C2
10 µF
H4
AD9101 – Typical Performance Curves
Hold Mode Distortion vs. Analog
Input Frequency
Recommended RS vs. CL for Optimal
Settling Time
B
SO
LE
TE
Gain vs. Frequency (Track Mode)
Feedthrough vs. Input Frequency
Droop Rate vs. Temperature
O
Track-to-Hold-to-Track Transients
Settling Tolerance vs. Acquisition
Time
Power Supply Rejection Ratio vs.
Frequency
–10–
REV. 0
AD9101
OUTLINE DIMENSIONS
Dimensions are shown in inches and (mm).
20-Pin SOIC
20-Contact LCC
0.055 (1.40)
0.045 (1.14)
0.512 (13.00)
0.496 (12.60)
20
19
11
0.075
(1.91)
REF.
20
18
0.299 (7.60)
0.291 (7.40)
TOP VIEW
0.419 (10.65)
0.394 (10.00)
1
2
17
NO. 1 PIN
INDEX
16
BOTTOM VIEW
3
4
0.028 (0.71)
0.022 (0.56)
5
6
15
7
14
8
TE
10
1
13 12
0.50 (1.27) BSC
0.019 (0.49)
0.014 (0.35)
11
10
0.050
(1.27)
BSC
9
0.358 (9.09)
0.342 (8.69)
0.104 (2.65)
0.093 (2.35)
0.100 (2.54)
0.064 (1.63)
0.050 (1.27)
0.016 (0.40)
O
B
SO
0.0125 (0.32)
0.0091 (0.23)
LE
0.012 (0.30)
0.004 (0.10)
REV. 0
–11–
PRINTED IN U.S.A.
TE
LE
B
SO
O
C1659–24–5/92