ON ADT7463ARQZ-R7 Db coolâ ¢ remote thermal controller and voltage monitor Datasheet

dB COOL™ Remote Thermal
Controller and Voltage Monitor
ADT7463*
a
FEATURES
Monitors up to 5 Supply Voltages
Controls and Monitors up to 4 Fan Speeds
1 On-Chip and 2 Remote Temperature Sensors
Monitors up to 6 Processor VID Bits
Dynamic TMIN Control Mode Optimizes System
Acoustics Intelligently
Automatic Fan Speed Control Mode Controls System
Cooling Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User
Perception of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel® Pentium® 4
Processor Thermal Control Circuit via THERM Input
2-Wire and 3-Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
GENERAL DESCRIPTION
The ADT7463 dBCOOL controller is a complete systems
monitor and multiple PWM fan controller for noise-sensitive
applications requiring active system cooling. It can monitor
12 V, 5 V, and 2.5 V CPU supply voltages, plus its own supply
voltage. It can monitor the temperature of up to two remote
sensor diodes, plus its own internal temperature. It can measure
and control the speed of up to four fans so that they operate at the
lowest possible speed for minimum acoustic noise. The automatic
fan speed control loop optimizes fan speed for a given temperature.
A unique dynamic TMIN control mode enables the system
thermals/acoustics to be intelligently managed. The effectiveness
of the system’s thermal solution can be monitored using the
THERM input. The ADT7463 also provides critical thermal
protection to the system using the bidirectional THERM pin
as an output to prevent system or component overheating.
APPLICATIONS
Low Acoustic Noise PCs
Networking and Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
ADDR
SELECT ADDR EN SCL SDA SMBALERT
VID5
VID4
VID
REGISTER
VID3
VID2
VID1
SMBUS
ADDRESS
SELECTION
SERIAL BUS
INTERFACE
VID0
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
AUTOMATIC
FAN SPEED
CONTROL
ACOUSTIC
ENHANCEMENT
CONTROL
DYNAMIC
TMIN
CONTROL
TACH1
TACH2
FAN SPEED
COUNTER
TACH3
TACH4
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
PERFORMANCE
MONITORING
THERM
VCC
VCC TO ADT7463
THERMAL
PROTECTION
ADT7463
D1+
D1–
D2+
D2–
VCC
10-BIT
ADC
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
+5VIN
+12VIN
+2.5VIN
VCCP
BAND GAP
REFERENCE
BAND GAP
TEMP. SENSOR
INTERRUPT
STATUS
REGISTERS
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
GND
*Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result
from
use.reserved.
No license is granted by implication or otherwise
©2008
SCILLC.
Allits
rights
under any
patent
or patent rights of Analog Devices. Trademarks and
January
2008
-Rev. 4
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood,Publication
MA 02062-9106,
U.S.A.
Order Number:
Tel: 781/329-4700
www.analog.com
ADT7463/D
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
ADT7463–SPECIFICATIONS1, 2, 3, 4 (T = T
A
MIN
to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage
Supply Current, ICC
3.0
5.0
5.5
3
20
V
mA
µA
Interface Inactive, ADC Active
Standby Mode
± 1.5
±3
�C
�C
�C
�C
�C
�C
�C
µA
µA
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
± 0.5
Resolution
Remote Diode Sensor Accuracy
0.25
± 0.5
Resolution
Remote Sensor Source Current
0.25
180
11
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE
Differential Nonlinearity, DNL
Power Supply Sensitivity
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Total Monitoring Cycle Time
Input Resistance
100
± 0.1
11.38
12.09
25.59
120.17
13.51
140
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
Full-Scale Count
Nominal Input RPM
Internal Clock Frequency
82.8
OPEN-DRAIN DIGITAL OUTPUTS,
PWM1 to PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
0.1
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS
(VID0 to VID5)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Voltage, VIL
109
329
5,000
10,000
90.0
0.1
2.0
500
1.7
± 1.5
± 2.5
±3
± 1.5
±1
13
13.50
28
134.50
15
200
±7
± 11
± 13
65,535
0�C � TA � 70�C; 0�C � TD � 120�C
0�C � TA � 105�C; 0�C � TD � 120�C
0�C � TA � 120�C; 0�C � TD � 120�C
High Level
Low Level
Averaging Enabled
Averaging Enabled
Averaging Enabled
Averaging Enabled
Averaging Disabled
%
%
%
0�C � TA � 70�C
0�C � TA � 105�C
–40�C � TA � +120�C
Fan Count = 0xBFFF
Fan Count = 0x3FFF
Fan Count = 0x0438
Fan Count = 0x021C
97.2
RPM
RPM
RPM
RPM
kHz
8.0
0.4
1
mA
V
µA
IOUT = –8.0 mA, VCC = 3.3 V
VOUT = VCC
0.4
1
V
µA
IOUT = –4.0 mA, VCC = 3.3 V
VOUT = VCC
0.4
V
V
mV
0.8
0.8
%
LSB
%/V
ms
ms
ms
ms
ms
kΩ
0�C � TA � 70�C
–40�C � TA � +120�C
0.4
V
V
V
V
Bit 6 (THLD) Reg. 0x43 = 0
(VID Threshold = 1 V)
Bit 6 (THLD) Reg. 0x43 = 1
(VID Threshold = 0.6 V)
Rev. 4 | Page 2 of 52 | www.onsemi.com
–2–
REV. C
ADT7463
Parameter
Min
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Typ
0.5
0.75 � VCCP
0.4
V
V
–0.3
DIGITAL INPUT LOGIC LEVELS
(THERM) AGTL+
Input High Voltage, VIH
Input Low Voltage, VIL
Unit
V
V
V
V
V p-p
5.5
+0.8
Hysteresis
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
Max
–1
+1
5
Test Conditions/Comment
Maximum Input Voltage
Minimum Input Voltage
µA
µA
pF
VIN = VCC
VIN = 0
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
ms
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
Can Be Optionally Disabled
5
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Detect Clock Low Timeout, tTIMEOUT
400
50
1.3
0.6
0.6
1.3
0.6
50
1000
300
100
300
15
35
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T A = 25°C and represent the most likely parametric norm.
3
Logic inputs accept input high voltages up to V MAX even when the device is operating down to V MIN.
4
Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.0 V for a rising edge.
5
Guaranteed by design, not production tested.
Specifications subject to change without notice.
tR
tF
tHD;STA
tLOW
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;DAT
tSU;STO
SDA
tBUF
P
S
S
Figure 1. Diagram for Serial Bus Timing
Rev. 4 | Page 3 of 52 | www.onsemi.com
REV. C
–3–
P
ADT7463
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on +12VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
IR Reflow Peak Temperature for Pb-free . . . . . . . . . . 260°C
Lead Temperature (soldering 10 sec) . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
SDA 1
24 PWM1/XTO
SCL 2
23 VCCP
GND 3
22 +2.5V /SMBALERT
IN
VCC 4
21 +12VIN /VID5
VID0 5
VID1
6
VID2
7
VID3
ADT7463
20 +5V /THERM
IN
19 VID4
TOP VIEW
(Not to Scale) 18 D1+
8
17 D1–
TACH3 9
16 D2+
PWM2/SMBALERT 10
15 D2–
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TACH1 11
14 TACH4/ADDRESS SELECT/THERM
TACH2 12
13 PWM3/ADDRESS ENABLE
THERMAL CHARACTERISTICS
24-Lead QSOP Package:
θJA = 105°C/W, θJC = 39°C/W.
ORDERING GUIDE
Model
ADT7463ARQ
ADT7463ARQ-REEL
ADT7463ARQ-REEL7
ADT7463ARQZ*
ADT7463ARQZ-REEL*
ADT7463ARQZ-R7*
ADT7463ARQZ-REEL7*
EVAL-ADT7463EB
Temperature
Range
Package
Description
Package
Option
–40�C to +120�C
–40�C to +120�C
–40�C to +120�C
–40�C to +120�C
–40�C to +120�C
–40�C to +120�C
24-Lead QSOP
24-Lead QSOP
24-Lead QSOP
24-Lead QSOP
24-Lead QSOP
24-Lead QSOP
Evaluation Board
RQ-24
RQ-24
RQ-24
RQ-24
RQ-24
RQ-24
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADT7463 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Rev. 4 | Page 4 of 52 | www.onsemi.com
–4–
REV. C
ADT7463
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SDA
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus.
2
SCL
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
3
GND
Ground Pin for the ADT7463.
4
VCC
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. V CC is also
monitored through this pin. The ADT7463 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply.
5
VID0
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
6
VID1
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
7
VID2
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
8
VID3
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
9
TACH3
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog
input (AIN3) to measure the speed of 2-wire fans.
10
PWM2
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control FAN 2
speed.
SMBALERT
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
11
TACH1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog
input (AIN1) to measure the speed of 2-wire fans.
12
TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog
input (AIN2) to measure the speed of 2-wire fans.
13
PWM3
Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/Fan 4 speed. Requires 10 kΩ typical
pull-up.
ADDRESS ENABLE
If pulled low on power-up, this places the ADT7463 into address select mode, and the state of Pin 14 will determine
the ADT7463’s slave address.
TACH4
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog
input (AIN4) to measure the speed of 2-wire fans.
ADDRESS
SELECT
If in address select mode, this pin determines the SMBus device address.
THERM
Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
15
D2–
Cathode Connection to Second Thermal Diode.
16
D2+
Anode Connection to Second Thermal Diode.
17
D1–
Cathode Connection to First Thermal Diode.
18
D1+
Anode Connection to First Thermal Diode.
19
VID4
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
20
+5VIN
Analog Input. Monitors 5 V power supply.
THERM
Alternatively, this pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor
assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
+12VIN
VID5
Analog Input. Monitors 12 V power supply.
Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43).
Supports VRM10 solutions.
14
21
22
+2.5VIN
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
SMBALERT
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
23
VCCP
Analog Input. Monitors processor core voltage (0 V to 3 V).
24
PWM1/
Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical pull-up.
XTO
Also functions as the output from the XOR tree in XOR test mode.
Rev. 4 | Page 5 of 52 | www.onsemi.com
REV. C
–5–
ADT7463
FUNCTIONAL DESCRIPTION
General Description
INTERNAL REGISTERS OF THE ADT7463
A brief description of the ADT7463’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables IV to XLII.
The ADT7463 is a complete systems monitor and multiple fan
controller for any system requiring monitoring and cooling. The
device communicates with the system via a serial system
management bus. The serial bus controller has an optional
address line for device selection (Pin 14), a serial data line
for reading and writing addresses and data (Pin 1), and an input
line for the serial clock (Pin 2). All control and programming
functions of the ADT7463 are performed over the serial bus. In
addition, two of the pins can be reconfigured as an SMBALERT
output to indicate out-of-limit conditions.
Configuration Registers
The configuration registers provide control and configuration of
the ADT7463, including alternate pinout functionality.
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADT7463, the first byte
of data is always a register address, which is written to the
address pointer register.
Measurement Inputs
Status Registers
The device has six measurement inputs, four for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip temperature sensor.
These registers provide the status of each limit comparison and
are used to signal out-of-limit conditions on the temperature,
voltage, or fan speed channels. If Pin 10 or Pin 22 is configured as SMBALERT, then this pin asserts low whenever a
status bit gets set.
Pins 20 through 23 are analog inputs with on-chip attenuators,
configured to monitor 5 V, 12 V, 2.5 V, and the processor core
voltage (2.25 V input), respectively.
Interrupt Mask Registers
These registers allow each interrupt status event to be masked
when Pin 10 or Pin 22 is configured as an SMBALERT output.
Power is supplied to the chip via Pin 4, and the system also
monitors VCC through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
VID Register
The status of the VID0 to VID5 pins of the processor can read
from this register. VID code changes can also generate
SMBALERT interrupts.
Remote temperature sensing is provided by the D1� and D2�
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
Value and Limit Registers
The results of analog voltage inputs, temperature, and fan speed
measurements are stored in these registers, along with their
limit values.
The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature.
Offset Registers
Sequential Measurement
These registers allow each temperature channel reading to be
offset by a twos complement value written to these registers.
When the ADT7463 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are stored
in the status registers, which can be read over the serial bus to
flag out-of-limit conditions.
TMIN Registers
These registers program the starting temperature for each fan
under automatic fan speed control.
TRANGE Registers
These registers program the temperature-to-fan speed control
slope in automatic fan speed control mode for each PWM output.
Processor Voltage ID
Operating Point Registers
Five digital inputs (VID0 to VID5—Pins 5 to 8, 19, and 21) read
the processor voltage ID code and store it in the VID register,
from which it can be read out by the management system over
the serial bus. The VID code monitoring function is compatible
with both VRM9.x and future VRM10 solutions. Additionally,
an SMBALERT can be generated to flag a change in VID code.
These registers define the target operating temperatures for each
thermal zone when running under dynamic TMIN control. This
function allows the cooling solution to adjust dynamically in
response to measured temperature and system performance.
Enhance Acoustics Registers
These registers allow each PWM output controlling fan to be
tweaked to enhance the system’s acoustics.
ADT7463 Address Selection
Pin 13 is the dual-function PWM3/ADDRESS ENABLE pin.
If Pin 13 is pulled low on power-up, the ADT7463 reads the
state of Pin 14 (TACH4/ADDRESS SELECT/ THERM pin) to
determine the ADT7463’s slave address. If Pin 13 is high on
power-up, then the ADT7463 defaults to the SMBus slave
Address 0x2E. This function is described in more detail later.
Rev. 4 | Page 6 of 52 | www.onsemi.com
–6–
REV. C
Typical Performance Characteristics–ADT7463
3
10
5
DXP TO GND
0
–5
DXP TO VCC (3.3V)
–10
–15
–20
1.0
10.0
30.0
3.3
LEAKAGE RESISTANCE (M�)
100.0
TPC 1. Remote Temperature Error
vs. Leakage Resistance
–3
–6
–12
–15
–18
–21
–24
–27
–30
–33
–36
1.0
+3 SIGMA
1
0
–3 SIGMA
–1
–2
LOW LIMIT
10
60
TEMPERATURE ( C)
8
250mV
4
2
–2
100k
110
TPC 4. Local Temperature Error
vs. Actual Temperature
10
0
100mV
5M
550k
FREQUENCY (Hz)
50M
TPC 5. Remote Temperature Error
vs. Power Supply Noise Frequency
1.9
1.7
1.6
1.5
2.6
3.0
3.4
3.8
4.2
4.6
5.0
SUPPLY VOLTAGE (V)
TPC 7. Supply Voltage vs.
Supply Current
5.4
20mV
10
8
10mV
4
2
0
–2
60k 110k
1M
10M
FREQUENCY (Hz)
50M
TPC 8. Remote Temperature Error vs.
Differential Mode Noise Frequency
Rev. 4 | Page 7 of 52 | www.onsemi.com
REV. C
–2
LOW LIMIT
10
60
TEMPERATURE ( C)
110
250mV
5.0
2.5
0
100mV
–2.5
–5.0
100k
5M
550k
FREQUENCY (Hz)
50M
TPC 6. Local Temperature Error vs.
Power Supply Noise Frequency
40
12
6
–3 SIGMA
–1
7.5
REMOTE TEMPERATURE ERROR (�C)
REMOTE TEMPERATURE ERROR (�C)
1.8
0
10.0
16
14
+3 SIGMA
12.5
12
6
1
HIGH LIMIT
TPC 3. Remote Temperature Error
vs. Actual Temperature
LOCAL TEMPERATURE ERROR (�C)
HIGH LIMIT
2
2
–3
–40
47.0
TPC 2. Remote Temperature Error
vs. Capacitance between D+ and D–
REMOTE TEMPERATURE ERROR (�C)
LOCAL TEMPERATURE ERROR ( C)
10.0 22.0
2.2
3.3
4.7
DXP TO DXN CAPACITANCE (nF)
14
–3
–40
SUPPLY CURRENT (mA)
REMOTE TEMPERATURE
ERROR (�C)
–9
3
1.4
3
0
REMOTE TEMPERATURE ERROR ( C)
REMOTE TEMPERATURE ERROR (�C)
REMOTE TEMPERATURE ERROR (�C)
15
–7–
35
100mV
30
25
20
15
10
40mV
5
0
20mV
–5
–10
10k
100k
1M
FREQUENCY (Hz)
10M
TPC 9. Remote Temperature Error vs.
Common-Mode Noise Frequency
ADT7463
ADT7463
FRONT
CHASSIS
FAN
TACH2
PWM1
TACH1
PWM3
REAR
CHASSIS
FAN
TACH3
VID[0:4]/VID[0:5]
5(VRM9)/6(VRM10)
D2+
D2–
THERM
AMBIENT
TEMPERATURE
D1+
PROCHOT
D1–
3.3VSB
5V
SDA
12V/VID5
ADP316x
VRM
CONTROLLER
VCOMP
SCL
SMBALERT
CURRENT
VCORE
GND
Figure 2. Recommended Implementation
RECOMMENDED IMPLEMENTATION
Configuring the ADT7463 as in Figure 2 allows the systems
designer the following features:
•
Six VID inputs (VID0 to VID5) for VRM10 support.
•
Two PWM outputs for fan control of up to three fans
(the front and rear chassis fans are connected in parallel).
•
Three TACH fan speed measurement inputs.
•
VCC measured internally through Pin 4.
•
CPU core voltage measurement (VCORE).
•
2.5 V measurement input used to monitor CPU current
(connected to VCOMP output of ADP316x VRM controller).
This is used to determine CPU power consumption.
•
•
VRM temperature uses local temperature sensor.
•
CPU temperature measured using Remote 1 temperature
channel.
•
Ambient temperature measured through Remote 2 temperature
channel.
•
If not using VID5, this pin can be reconfigured as the 12 V
monitoring input.
•
Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT
monitoring and can function as an overtemperature THERM
output.
•
SMBALERT system interrupt output.
See the AN-612 ADT7463 Configuration application note for more
information and register settings for all possible configurations
(www.analog.com/UploadedFiles/Application_Notes/408599520AN612_0.pdf).
5 V measurement input.
Rev. 4 | Page 8 of 52 | www.onsemi.com
–8–
REV. C
ADT7463
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices sharing
the same serial bus, for example, if more than one ADT7463 is
used in a system.
SERIAL BUS INTERFACE
Control of the ADT7463 is carried out using the serial system
management bus (SMBus). The ADT7463 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7463 has a 7-bit serial bus address. When the device
is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high,
the ADT7463 has a default SMBus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address. If
more than one ADT7463 is used in a system, then each ADT7463
should be placed in address select mode by strapping Pin 13 low on
power-up. The logic state of Pin 14 then determines the device’s
SMBus address. The logic of these pins is sampled upon power-up.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely on the low-to-high transition
at the beginning of the 8th SCL pulse, when the serial bus address
byte matches the selected slave address. The selected slave address
is chosen using the address enable/address select pins. Any
attempted changes in the address will have no effect after this.
VCC
ADT7463
ADDR_SEL
Table I. Address Select Mode
Pin 13 State
Pin 14 State
Address
0
0
1
Low (10 kΩ to GND)
High (10 kΩ Pull-Up)
Don’t Care
0101100 (0x2C)
0101101 (0x2D)
0101110 (0x2E)
(Default)
PWM3/ADDR_EN
10k�
14
13
ADDRESS = 0x2D
Figure 5. SMBus Address = 0x2D (Pin 14 = 1)
VCC
ADT7463
VCC
ADT7463
ADDR_SEL
PWM3/ADDR_EN
14
ADDR_SEL
10k�
PWM3/ADDR_EN
ADT7463
PWM3/ADDR_EN
10k�
Figure 6. Unpredictable SMBus Address if Pin 13
Is Unconnected
13
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, then the master writes to the
slave device. If the R/W bit is a 1, the master reads from
the slave device.
ADDRESS = 0x2C
Figure 4. SMBus Address = 0x2C (Pin 14 = 0)
Rev. 4 | Page 9 of 52 | www.onsemi.com
REV. C
NC
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7463 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7463 IS PLACED INTO ADDRESS SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATE
FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME.
Figure 3. Default SMBus Address = 0x2E
14
13
DO NOT LEAVE ADDR_EN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
13
ADDRESS = 0x2E
ADDR_SEL
10k�
14
–9–
ADT7463
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7463, write operations contain either one
or two bytes, and read operations contain one byte and perform
the following functions.
To write data to one of the device data registers or read data from
it, the address pointer register must be set so that the correct data
register is addressed, then data can be written into that register
or read from it. The first byte of a write operation always contains
an address that is stored in the address pointer register. If data
is to be written to the device, then the write operation contains
a second data byte that is written to the register selected by the
address pointer register.
3. When all data bytes have been read or written, stop conditions
are established. In WRITE mode, the master pulls the data line
high during the tenth clock pulse to assert a STOP condition.
In READ mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse. This is known as No Acknowledge.
The master then takes the data line low during the low period before the 10th clock pulse, and then high during the
10th clock pulse to assert a STOP condition.
This is illustrated in Figure 7. The device address is sent over
the bus followed by R/W being set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
1
9
9
1
SCL
SDA
START BY
MASTER
0
1
0
1
1
A1
A0
FRAME 1
SERIAL BUS ADDRESS
BYTE
D7
R/W
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7463
ACK. BY
ADT7463
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
FRAME 3
DATA
BYTE
D2
D1
D0
ACK. BY
ADT7463
STOP BY
MASTER
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
Rev. 4 | Page 10 of 52 | www.onsemi.com
–10–
REV. C
ADT7463
1
9
9
1
SCL
SDA
0
1
START BY
MASTER
0
1
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7463
FRAME 1
SERIAL BUS ADDRESS
BYTE
ACK. BY
ADT7463
STOP BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 8. Writing to the Address Pointer Register Only
1
9
9
1
SCL
SDA
START BY
MASTER
0
1
0
1
1
A1
FRAME 1
SERIAL BUS ADDRESS
BYTE
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
ADT7463
D0
NO ACK. BY STOP BY
MASTER
MASTER
FRAME 2
DATA BYTE FROM ADT7463
Figure 9. Reading Data from a Previously Selected Register
When reading data from a register, there are two possibilities:
Notes
1. It is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.
1. If the ADT7463’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7463
as before, however, only the data byte is sent and this contains the register address. This is shown in Figure 8.
2. In Figures 7 to 9, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.
A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 9.
2. If the address pointer register is already at the desired address,
data can be read from the corresponding data register without
first writing to the address pointer register, so Figure 8 can
be omitted.
3. In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7463 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for
more information).
4. If it is required to perform several read or write operations in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
Rev. 4 | Page 11 of 52 | www.onsemi.com
REV. C
–11–
ADT7463
ADT7463 WRITE OPERATIONS
ADT7463 READ OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7463
are discussed below. The following abbreviations are used in the
diagrams:
S – START
P – STOP
R – READ
W – WRITE
A – ACKNOWLEDGE
A – NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols.
The ADT7463 uses the following SMBus read protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7463, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This is illustrated in Figure 10.
1
2
3
S SLAVE W A
ADDRESS
4
5
REGISTER
ADDRESS
6
A P
Figure 10. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after
setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single
byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated in Figure 11.
1
2
3
S SLAVE W A
ADDRESS
Receive Byte
This is useful when repeatedly reading a single register. The
register address needs to have been set up previously. In this
operation, the master device receives a single byte from a slave
device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and the transaction ends.
In the ADT7463, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation.
1
2
3
4
S SLAVE
R A DATA
ADDRESS
5
6
A P
Figure 12. Single Byte Read from a Register
ALERT RESPONSE ADDRESS
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address
that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and it can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the one
with the lowest device address will have priority in accordance
with normal SMBus arbitration.
5. Once the ADT7463 has responded to the alert response
address, the master must read the status registers and the
SMBALERT will only be cleared if the error condition has
gone away.
SMBUS TIMEOUT
4
REGISTER
ADDRESS
5
6
7 8
A DATA A P
Figure 11. Single Byte Write to a Register
The ADT7463 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
CONFIGURATION REGISTER 1 – Register 0x40
<6> TODIS = 0; SMBus Timeout ENABLED (Default)
<6> TODIS = 1; SMBus Timeout DISABLED
Rev. 4 | Page 12 of 52 | www.onsemi.com
–12–
REV. C
The ADT7463 includes an SMBus timeout feature. If there is
no SMBus activity for 35 ms, the ADT7463 assumes that the bus
is locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it
can be disabled.
CONFIGURATION
REGISTER
1 – Register 0x40
VOLTAGE
MEASUREMENT
INPUTS
<6> ADT7463
TODIS = has
0; SMBus
Timeout
ENABLED
(Default)
The
four external
voltage
measurement
channels.
= 1; SMBus
DISABLED
It<6>
canTODIS
also measure
its ownTimeout
supply voltage,
VCC
CC.
Pins 20 to 23 are dedicated to measuring 5 V, 12 V, and 2.5 V
VOLTAGE
INPUTS
–12–supplies
REV. C
and MEASUREMENT
the processor core voltage
VCCP
CCP (0 V to 3 V input).
The
ADT7463
has
four
external
voltage
measurement
channels.
The VCC
CC supply voltage measurement is carried out through
It can also measure its own supply voltage, VCC.
the VCC
CC pin (Pin 4). Setting Bit 7 of Configuration Register 1
Pins 20
to 23allows
are dedicated
to measuring
V,ADT7463
12 V, and and
2.5 V
(Reg.
0x40)
a 5 V supply
to power 5the
be
supplies and
the processor
corethe
voltage
VCCP (0 V to 3channel.
V input).
measured
without
overranging
VCC
CC measurement
voltage
measurement
through
The 2.5
VCCVsupply
The
input can
be used
to monitorisacarried
chipset out
supply
voltage
(Pin 4). Setting Bit 7 of Configuration Register 1
thecomputer
VCC pin systems.
in
(Reg. 0x40) allows a 5 V supply to power the ADT7463 and be
channel.
measured without overranging
the VCC measurement
ANALOG-TO-DIGITAL
CONVERTER
(ADC)
Theanalog
2.5 V inputs
input can
used to monitor
chipset supply
voltage
All
are be
multiplexed
into thea on-chip,
successive
in computer systems.
approximation,
ADC. This has a resolution of 10 bits. The basic
input range is 0 V to 2.25 V, but the inputs have built-in attenuANALOG-TO-DIGITAL
ators
to allow measurementCONVERTER
of 2.5 V, 3.3 V,(ADC)
5 V, 12 V, and the
All analogcore
inputs
are Vmultiplexed
into
the
on-chip,
successive
without
any
external
components.
To
processor
voltage
CCP
CCP
approximation,
ADC. This
has supply
a resolution
of 10the
bits.
Theprobasic
allow
for the tolerance
of these
voltages,
ADC
input an
range
is 0 V
but(decimal
the inputs
have
built-in
duces
output
of to
3/42.25
full V,
scale
768
or 300
hex)attenufor
ators
to allowinput
measurement
of so
2.5has
V, adequate
3.3 V, 5 V,
12 V, andtothe
the
nominal
voltage and
headroom
processor
voltage VCCP without any external components. To
cope
withcore
overvoltages.
allow for the tolerance of these supply voltages, the ADC produces anCIRCUITRY
output of 3/4 full scale (decimal 768 or 300 hex) for
INPUT
the nominal
input voltage
and
so has
adequate
headroom
to13.
The
internal structure
for the
analog
inputs
is shown
in Figure
cope with
Each
inputovervoltages.
circuit consists of an input protection diode, an
attenuator, plus a capacitor to form a first-order, low-pass filter
INPUT
that
givesCIRCUITRY
the input immunity to high frequency noise.
The internal structure for the analog inputs is shown in Figure 13.
Each input circuit
consists of anREGISTERS
input protection diode, an
VOLTAGE
MEASUREMENT
attenuator,
plus
capacitor= to
form
a first-order, low-pass filter
Reg.
0x20 2.5
V aReading
0x00
Default
that gives the input immunity to high frequency noise.
Reg. 0x21 VCCP
CCP Reading = 0x00 Default
Reading = 0x00REGISTERS
Default
Reg.
0x22
V
CC
VOLTAGE CC
MEASUREMENT
Reg. 0x23
0x20 52.5
Reading
= 0x00
Default
Reg.
VV
Reading
= 0x00
Default
ADT7463
VOLTAGE MEASUREMENT LIMIT REGISTERS
Associated with each voltage measurement channel are high and
low limit registers. Exceeding the programmed high or low limit
causes the appropriate status bit to be set. Exceeding either limit
VOLTAGE
MEASUREMENT
LIMIT REGISTERS
can
also generate
SMBALERT interrupts.
Associated
with
each
voltage
measurement
Reg. 0x44 2.5 V Low Limit = 0x00 Defaultchannel are high and
low limit registers. Exceeding the programmed high or low limit
Reg.
0x45
V High Limit
causes
the 2.5
appropriate
status =
bit0xFF
to beDefault
set. Exceeding either limit
can
also
generate
SMBALERT
interrupts.
Reg. 0x46 VCCP
CCP Low Limit = 0x00 Default
Reg. 0x47
0x44 V
2.5
V High
Low Limit
Limit =
= 0x00
0xFFDefault
Default
Reg.
CCP
CCP
ADT7463
Reg. 0x48
0x45 V
2.5
High
Limit
= 0xFF
Default
Low
Limit
= 0x00
Default
Reg.
CCV
CC
LowLimit
Limit==0xFF
0x00 Default
Default
Reg. 0x49
0x46 VVCC
CCP
High
Reg.
CC
High
Limit
= 0xFF
Default
Reg. 0x4A
0x47 5VCCP
Reg.
V Low
Limit
= 0x00
Default
Low Limit
Reg. 0x4B
0x48 V
Reg.
5 CC
V High
0xFFDefault
Default
Limit =
= 0x00
Limit =
= 0x00
0xFF Default
Default
Reg. 0x4C
0x49 V
Reg.
12CCVHigh
Low Limit
Reg. 0x4D
0x4A 12
5 VVLow
Default
Reg.
HighLimit
Limit= =0x00
0xFF
Default
Reg. 0x4B 5 V High Limit = 0xFF Default
120k�
120k�
12VIN
Reg. 0x4C 12V
12INV Low Limit = 0x00 Default
20k�
20k�
30pF
30pF
Reg. 0x4D 12 V High Limit = 0xFF Default
12V
5VIN
IN
IN
5V
5VIN
3.3V
IN
3.3V
IN
3.3VIN
2.5V
IN
2.5V
IN
120k�
93k�
93k�
20k�
47k�
47k�
93k�
68k�
68k�
47k�
71k�
71k�
2.5V
IN
VCCP
CCP
V
30pF
30pF
30pF
MUX
MUX
30pF
30pF
30pF
MUX
68k�
45k�
45k�
71k�
94k�
94k�
Reading==0x00
0x00Default
Default
Reg. 0x24
0x21 12
VCCP
Reg.
V Reading
Reg. 0x22 VCC Reading = 0x00 Default
30pF
30pF
30pF
45k�
17.5k�
17.5k�
94k�
52.5k�
52.5k�
30pF
35pF
35pF
Reg. 0x23 5 V Reading = 0x00 Default
Reg. 0x24 12 V Reading = 0x00 Default
V
17.5k�
CCP
Figure
13. Structure of Analog Inputs
35pF
52.5k�
Table II shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC
is running,
it samples
and converts
Figure
13. Structure
of Analog
Inputsa voltage
input in 711 µs and averages 16 conversions to reduce noise;
Table II shows the input ranges of the analog inputs and output
a measurement on each input takes nominally 11.38 ms.
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise;
a measurement on each input takes nominally 11.38 ms.
Rev. 4 | Page 13 of 52 | www.onsemi.com
REV. C
–13–
ADT7463
Table II. 10-Bit A/D Output Code vs. V IN
Input Voltage
A/D Output
+12VIN
+5VIN
VCC (3.3VIN)*
+2.5VIN
+VCCP
Decimal
Binary (10 Bits)
<0.0156
0.0156–0.0312
0.0312–0.0469
0.0469–0.0625
0.0625–0.0781
0.0781–0.0937
0.0937–0.1093
0.1093–0.1250
0.1250–0.14060
<0.0065
0.0065–0.0130
0.0130–0.0195
0.0195–0.0260
0.0260–0.0325
0.0325–0.0390
0.0390–0.0455
0.0455–0.0521
0.0521–0.0586
<0.0042
0.0042–0.0085
0.0085–0.0128
0.0128–0.0171
0.0171–0.0214
0.0214–0.0257
0.0257–0.0300
0.0300–0.0343
0.0343–0.0386
<0.00293
0.0293–0.0058
0.0058–0.0087
0.0087–0.0117
0.0117–0.0146
0.0146–0.0175
0.0175–0.0205
0.0205–0.0234
0.0234–0.0263
0
1
2
3
4
5
6
7
8
00000000 00
00000000 01
00000000 10
00000000 11
00000001 00
00000001 01
00000001 10
00000001 11
00000010 00
4.0000–4.0156
1.6675–1.6740
1.1000–1.1042
0.7500–0.7529
256 (1/4 scale)
01000000 00
8.0000–8.0156
3.3300–3.3415
2.2000–2.2042
1.5000–1.5029
512 (1/2 scale)
10000000 00
12.0000–12.0156
5.0025–5.0090
3.3000–3.3042
2.2500–2.2529
768 (3/4 scale)
11000000 00
15.8281–15.8437
15.8437–15.8593
15.8593–15.8750
15.8750–15.8906
15.8906–15.9062
15.9062–15.9218
15.9218–15.9375
15.9375–15.9531
15.9531–15.9687
15.9687–15.9843
>15.9843
6.5983–6.6048
6.6048–6.6113
6.6113–6.6178
6.6178–6.6244
6.6244–6.6309
6.6309–6.6374
6.6374–6.4390
6.6439–6.6504
6.6504–6.6569
6.6569–6.6634
>6.6634
4.3527–4.3570
4.3570–4.3613
4.3613–4.3656
4.3656–4.3699
4.3699–4.3742
4.3742–4.3785
4.3785–4.3828
4.3828–4.3871
4.3871–4.3914
4.3914–4.3957
>4.3957
<0.0032
0.0032–0.0065
0.0065–0.0097
0.0097–0.0130
0.0130–0.0162
0.0162–0.0195
0.0195–0.0227
0.0227–0.0260
0.0260–0.0292
•
•
•
0.8325–0.8357
•
•
•
1.6650–1.6682
•
•
•
2.4975–2.5007
•
•
•
3.2942–3.2974
3.2974–3.3007
3.3007–3.3039
3.3039–3.3072
3.3072–3.3104
3.3104–3.3137
3.3137–3.3169
3.3169–3.3202
3.3202–3.3234
3.3234–3.3267
>3.3267
2.9677–2.9707
2.9707–2.9736
2.9736–2.9765
2.9765–2.9794
2.9794–2.9824
2.9824–2.9853
2.9853–2.9882
2.9882–2.9912
2.9912–2.9941
2.9941–2.9970
>2.9970
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
11111101 01
11111101 10
11111101 11
11111110 00
11111110 01
11111110 10
11111110 11
11111111 00
11111111 01
11111111 10
11111111 11
*The VCC output codes listed assume that V CC is 3.3 V. If V CC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the VCC
output codes are the same as for the +5V IN column.
Rev. 4 | Page 14 of 52 | www.onsemi.com
–14–
REV. C
ADT7463
VID CODE MONITORING
The ADT7463 has five dedicated voltage ID (VID code) inputs.
These are digital inputs that can be read back through the
VID register (Reg. 0x43) to determine the processor voltage
required/being used in the system. Five VID code inputs support
VRM9.x solutions. In addition, Pin 21 (12 V input) can be reconfigured as a sixth VID input to satisfy future VRM requirements.
logic states on the VID inputs are different than they were 11 µs
previously. The change of VID code can be used to generate
an SMBALERT interrupt. If an SMBALERT interrupt is
not required, Bit 0 of Interrupt Mask Register 2 (Reg. 0x75),
when set, prevents SMBALERTs from occurring on VID code
changes.
STATUS REGISTER 2 – Register 0x42
VID CODE REGISTER – Register 0x43
<0> 12V/VC = 0; If Pin 21 is configured as VID5, then a
Logic 0 denotes no change in VID code within last 11 µs.
<1> = VID1 (reflects logic state of Pin 6)
<0> 12V/VC = 1; If Pin 21 is configured as VID5, then a Logic 1
means that a change has occurred on the VID code inputs within
the last 11 µs. An SMBALERT generates if this function is enabled.
<0> = VID0 (reflects logic state of Pin 5)
<2> = VID2 (reflects logic state of Pin 7)
<3> = VID3 (reflects logic state of Pin 8)
<4> = VID4 (reflects logic state of Pin 19)
<5> = VID5 (reconfigurable 12 V input). This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of VID register
(Reg. 0x43) controls the VID input threshold voltage.
VID CODE REGISTER – Register 0x43
<6> THLD = 0; VID Switching Threshold = 1 V,
VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V
RECONFIGURING PIN 21 (+12V/VID5) AS VID5 INPUT
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10-compatible systems. Since the pin is configured as
VID5, it is no longer possible to monitor a 12 V supply.
Bit 7 of the VID register (Reg. 0x43) determines the function of
Pin 21. System or BIOS software can read the state of Bit 7 to
determine whether the system is designed to monitor 12 V or is
monitoring a sixth VID input.
<7> VIDSEL = 0; Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (Reg. 0x42)
reflects 12 V out-of-limit measurements.
VIDSEL = 1; Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (Reg. 0x42)
reflects VID code changes.
VID CODE CHANGE DETECT FUNCTION
The ADT7463 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes can
be detected and reported back by the ADT7463. Bit 0 of Status
Register 2 (Reg. 0x42) is the 12V/VC bit and denotes a VID
change when set. The VID code change bit gets set when the
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility, including:
Turn-Off Averaging
For each voltage measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. There may
be an instance where you would like to speed up conversions.
Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This effectively gives a reading 16 times faster
(711 µs), but the reading may be noisier.
Bypass Voltage Input Attenuators
THLD = 1; VID Switching Threshold = 0.6 V,
VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V
VID CODE REGISTER – Register 0x43
ADDITIONAL ADC FUNCTIONS
Setting Bit 5 of Configuration Register 2 (Reg 0x73) removes
the attenuation circuitry from the 2.5 V, V CCP, VCC, 5 V, and
12 V inputs. This allows the user to directly connect external
sensors or rescale the analog voltage measurement inputs for
other applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this mode,
the ADT7463 can be made to read a single voltage channel
only. If the internal ADT7463 clock is used, the selected input
is read every 711 µs. The appropriate ADC channel is selected
by writing to Bits <7:5> of the TACH1 Minimum High Byte
Register (0x55).
Bits <7:5>
Reg 0x55
000
001
010
011
100
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<5> = 1 Bypass Input Attenuators
<6> = 1 Single-Channel Convert Mode
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
Rev. 4 | Page 15 of 52 | www.onsemi.com
REV. C
Channel
Selected
2.5 V
VCCP
VCC
5V
12 V
–15–
ADT7463
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7463 contains an on-chip band gap temperature sensor
whose output is digitized by the on-chip 10-bit ADC. The 8-bit
MSB temperature data is stored in the local temperature register
(Address 26h). As both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table III. Theoretically, the temperature sensor
and ADC can measure temperatures from –128�C to +127�C
with a resolution of 0.25�C. However, this exceeds the operating
temperature range of the device, so local temperature measurements outside this range are not possible.
Remote Temperature Measurement
The ADT7463 can measure the temperature of two remote diode
sensors or diode-connected transistors connected to Pins 15 and
16, or 17 and 18.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about –2 mV/�C. Unfortunately, the absolute
value of VBE varies from device to device and individual calibration is required to null this out, so the technique is unsuitable
for mass production. The technique used in the ADT7463 is to
measure the change in VBE when the device is operated at two
different currents.
This is given by
∆VBE = KT q × ln( N )
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 14 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor, provided for temperature
monitoring on some microprocessors. It could equally well be a
discrete transistor, such as a 2N3904.
VDD
I
N�I
IBIAS
CPU
REMOTE
SENSING
TRANSISTOR
THERMDA
D+
VOUT+
THERMDC
D–
VOUT–
TO ADC
BIAS
DIODE
LOW-PASS
FILTER
fC = 65kHz
Figure 14. Signal Conditioning for Remote Diode Temperature Sensors
Rev. 4 | Page 16 of 52 | www.onsemi.com
–16–
REV. C
ADT7463
If a discrete transistor is used, the collector will not be grounded
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input. Figures 15a and 15b
show how to connect the ADT7463 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal of
the sensor is not referenced to ground but is biased above ground
by an internal diode at the D– input.
ADT7463
2N3904
NPN
D–
Figure 15a. Measuring Temperature Using an
NPN Transistor
To measure ∆VBE, the sensor is switched between operating currents
of I and N � I. The resulting waveform is passed through a
65 kHz low-pass filter to remove noise and to a chopper-stabilized
amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to
∆VBE. This voltage is measured by the ADC to give a temperature output in 10-bit, twos complement format. To further reduce
the effects of noise, digital filtering is performed by averaging
the results of 16 measurement cycles. A remote temperature
measurement takes nominally 25.5 ms. The results of remote
temperature measurements are stored in 10-bit, twos complement
format, as illustrated in Table III. The extra resolution for the
temperature measurements is held in the Extended Resolution
Register 2 (Reg. 0x77). This gives temperature readings with a
resolution of 0.25�C.
Table III. Temperature Data Format
Temperature
Digital Output (10-Bit)*
–128�C
–125�C
–100�C
–75�C
–50�C
–25�C
–10�C
0�C
+10.25�C
+25.5�C
+50.75�C
+75�C
+100�C
+125�C
+127�C
1000 0000 00
1000 0011 00
1001 1100 00
1011 0101 00
1100 1110 00
1110 0111 00
1111 0110 00
0000 0000 00
0000 1010 01
0001 1001 10
0011 0010 11
0100 1011 00
0110 0100 00
0111 1101 00
0111 1111 00
ADT7463
D+
2N3906
PNP
D–
Figure 15b. Measuring Temperature Using a PNP
Transistor
Nulling Out Temperature Errors
As CPUs run faster, it is getting more difficult to avoid high
frequency clocks when routing the D+, D– traces around a
system board. Even when recommended layout guidelines are
followed, there may still be temperature errors attributed to
noise being coupled onto the D+/D– lines. High frequency noise
generally has the effect of giving temperature measurements that are
too high by a constant amount. The ADT7463 has temperature
offset registers at Addresses 0x70, 0x72 for the Remote 1 and
Remote 2 temperature channels. By doing a one-time calibration
of the system, one can determine the offset caused by system
board noise and null it out using the offset registers. The offset
registers automatically add a twos complement 8-bit reading to
every temperature measurement. The LSBs add 0.25°C offset to
the temperature reading so the 8-bit register effectively allows
temperature offsets of up to �32�C with a resolution of 0.25�C.
This ensures that the readings in the temperature measurement
registers are as accurate as possible.
Temperature Offset Registers
Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0°C Default)
Reg. 0x71 Local Temperature Offset = 0x00 (0°C Default)
Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0°C Default)
*Bold denotes 2 LSBs of measurement in Extended
Resolution Register 2 (Reg. 0x77) with 0.25�C resolution.
Rev. 4 | Page 17 of 52 | www.onsemi.com
REV. C
D+
–17–
ADT7463
Temperature Measurement Registers
Single-Channel ADC Conversions
Reg. 0x25 Remote 1 Temperature = 0x80 Default
Reg. 0x26 Local Temperature = 0x80 Default
Reg. 0x27 Remote 2 Temperature = 0x80 Default
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7463 into single-channel ADC conversion mode. In this
mode, the ADT7463 can be made to read a single temperature
channel only. If the internal ADT7463 clock is used, the
selected input is read every 1.4 ms. The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1 Minimum
High Byte Register (0x55).
Reg. 0x77 Extended Resolution 2 = 0x00 Default
<7:6> TDM2 = Remote 2 Temperature LSBs
<5:4> LTMP = Local Temperature LSBs
<3:2> TDM1 = Remote 1 Temperature LSBs
Bits <7:5> Reg 0x55
101
110
111
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Channel Selected
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
Configuration Register 2 (Reg. 0x73)
<4> = 1 Averaging Off
<6> = 1 Single-Channel Convert Mode
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
TACH1 Minimum High Byte (Reg. 0x55)
<7:5> Selects ADC Channel for Single-Channel Convert Mode
Overtemperature Events
Reading Temperature from the ADT7463
It is important to note that temperature can be read from the
ADT7463 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25°C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from
being updated while its 2 LSBs are being read and vice versa.
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Registers 0x6A to 0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all fans run at
100% duty cycle. The fans stay running at 100% until the
temperature drops below THERM – Hysteresis (this can be
disabled by setting the boost bit in Configuration Register 3,
Bit 2, Register 0x78). The hysteresis value for that THERM
limit is the value programmed into Registers 0x6D, 0x6E
(hysteresis registers). The default hysteresis value is 4°C.
THERM LIMIT
HYSTERESIS (�C)
TEMPERATURE
ADDITIONAL ADC FUNCTIONS
A number of other functions are available on the ADT7463 to
offer the systems designer increased flexibility.
FANS
100%
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it may be necessary to take a very fast measurement, e.g., of CPU
temperature. Setting Bit 4 of Configuration Register 2 (Reg. 0x73)
turns averaging off. This takes a reading every 13 ms. The measurement itself takes 4 ms.
Figure 16. THERM Limit Operation
Rev. 4 | Page 18 of 52 | www.onsemi.com
–18–
REV. C
ADT7463
LIMITS, STATUS REGISTERS, AND INTERRUPTS
Limit Values
Fan Limit Registers
Associated with each measurement channel on the ADT7463
are high and low limits. These can form the basis of system
status monitoring: a status bit can be set for any out-of-limit
condition and detected by polling the device. Alternatively,
SMBALERT interrupts can be generated to flag a processor or
microcontroller of out-of-limit conditions.
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
8-Bit Limits
The following is a list of 8-bit limits on the ADT7463.
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
Voltage Limit Registers
Reg. 0x44 2.5 V Low Limit = 0x00 Default
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Reg. 0x45 2.5 V High Limit = 0xFF Default
Once all limits are programmed, the ADT7463 can be enabled
for monitoring. The ADT7463 measures all parameters in
round-robin format and sets the appropriate status bit for outof-limit conditions. Comparisons are done differently depending
on whether the measured value is being compared to a high or
low limit.
Out-of-Limit Comparisons
Reg. 0x46 VCCP Low Limit = 0x00 Default
Reg. 0x47 VCCP High Limit = 0xFF Default
Reg. 0x48 VCC Low Limit = 0x00 Default
Reg. 0x49 VCC High Limit = 0xFF Default
Reg. 0x4A 5 V Low Limit = 0x00 Default
HIGH LIMIT: > COMPARISON PERFORMED
Reg. 0x4B 5 V High Limit = 0xFF Default
LOW LIMIT: < OR = COMPARISON PERFORMED
Reg. 0x4C 12 V Low Limit = 0x00 Default
Reg. 0x4D 12 V High Limit = 0xFF Default
Temperature Limit Registers
Reg. 0x4E Remote 1 Temp Low Limit = 0x81 Default
Reg. 0x4F Remote 1 Temp High Limit = 0x7F Default
Reg. 0x6A Remote 1 THERM Limit = 0x64 Default
NO INT
Reg. 0x50 Local Temp Low Limit = 0x81 Default
Reg. 0x51 Local Temp High Limit = 0x7F Default
Reg. 0x6B Local THERM Limit = 0x64 Default
Reg. 0x52 Remote 2 Temp Low Limit = 0x81 Default
Reg. 0x53 Remote 2 Temp High Limit = 0x7F Default
LOW LIMIT
Reg. 0x6C Remote 2 THERM Limit = 0x64 Default
THERM Limit Register
Reg. 0x7A THERM Limit = 0x00 Default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH
limits are also 16 bits, consisting of a high byte and low byte.
Since fans running under speed or stalled are normally the only
conditions of interest, only high limits exist for fan TACHs. Since
fan TACH period is actually being measured, exceeding the limit
indicates a slow or stalled fan.
TEMP >
LOW LIMIT
Figure 17. Temperature > Low Limit: No INT
Rev. 4 | Page 19 of 52 | www.onsemi.com
REV. C
–19–
ADT7463
Analog Monitoring Cycle Time
INT
LOW LIMIT
The analog monitoring cycle begins when a 1 is written to the
start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC
measures each analog input in turn and as each measurement is
completed, the result is automatically stored in the appropriate
value register. This round-robin monitoring cycle continues
unless disabled by writing a 0 to Bit 0 of Configuration Register 1.
Because the ADC is normally left to free-run in this manner, the
time taken to monitor all the analog inputs is normally not of
interest, since the most recently measured value of any input
can be read out at any time.
For applications where the monitoring cycle time is important,
it is easily calculated.
TEMP =
LOW LIMIT
The total number of channels measured is:
• Four dedicated supply voltage inputs
Figure 18. Temperature = Low Limit: INT Occurs
• 3.3 VSTBY or 5 V supply (VCC pin)
• Local temperature
• Two remote temperatures
NO INT
As mentioned previously, the ADC performs round-robin
conversions and takes 11.38 ms for each voltage measurement,
12 ms for a local temperature reading, and 25.5 ms for each remote
temperature reading.
The total monitoring cycle time for averaged voltage and temperature monitoring is therefore nominally
(5 × 11.38) + 12 + (2 × 25.5) = 120 ms
HIGH LIMIT
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Status Registers
TEMP =
HIGH LIMIT
21.00C
Figure 19. Temperature = High Limit: No INT
INT
HIGH LIMIT
TEMP >
HIGH LIMIT
Figure 20. Temperature > High Limit: INT Occurs
The results of limit comparisons are stored in Status Registers 1
and 2. The status register bit for each channel reflects the status
of the last measurement and limit comparison on that channel.
If a measurement is within limits, the corresponding status register
bit is cleared to 0. If the measurement is out-of-limits, the corresponding status register bit is set to 1.
The state of the various measurement channels may be polled
by reading the status registers over the serial bus. In Bit 7 (OOL)
of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit
event has been flagged in Status Register 2. This means that a
user need only read Status Register 2 when this bit is set. Alternatively, Pin 10 or Pin 22 can be configured as an SMBALERT
output. This automatically notifies the system supervisor of an
out-of-limit condition. Reading the status registers clears the
appropriate status bit as long as the error condition that caused
the interrupt has cleared. Status register bits are “sticky.” Whenever a status bit gets set, indicating an out-of-limit condition,
it remains set even if the event that caused it has gone away
(until read). The only way to clear the status bit is to read the
status register after the event has gone away. Interrupt status
mask registers (Reg. 0x74, 0x75) allow individual interrupt
sources to be masked from causing an SMBALERT. However,
if one of these masked interrupt sources goes out-of-limit, its
associated status bit gets set in the interrupt status registers.
Rev. 4 | Page 20 of 52 | www.onsemi.com
–20–
REV. C
ADT7463
Read/Write
HIGH LIMIT
(Click
Digits)
10000000
2.5V
OOL
R2T
VCCP
LT
R1T
5V
VCC
TEMPERATURE
OOL = 1 DENOTES A PARAMETER
MONITORED THROUGH STATUS REG 2
IS OUT-OF-LIMIT
“STICKY”
STATUS
BIT
Figure 21. Status Register 1
Status Register 1 (Reg. 0x41)
SMBALERT
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 Temperature High or Low Limit
has been exceeded.
Bit 5 (LT) = 1, Local Temperature High or Low Limit has
been exceeded.
Bit 4 (R1T) = 1, Remote 1 Temperature High or Low Limit
has been exceeded.
Bit 3 (5V) = 1, 5 V High or Low Limit has been exceeded.
Bit 2 (VCC) = 1, VCC High or Low Limit has been exceeded.
Bit 1 (VCCP) = 1, VCCP High or Low Limit has been exceeded.
Bit 0 (2.5V) = 1, 2.5 V High or Low Limit has been exceeded.
D2
D1
F4P
FAN3
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 23. SMBALERT and Status Bit Behavior
Figure 23 shows how the SMBALERT output and “sticky” status
bits behave. Once a limit is exceeded, the corresponding status
bit gets set to 1. The status bit remains set until the error condition subsides and the status register gets read. The status bits are
referred to as sticky since they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if software
is polling the device periodically. Note that the SMBALERT
output remains low for the entire duration that a reading is
out-of-limit and until the status register has been read. This
has implications on how software handles the interrupt.
HANDLING SMBALERT INTERRUPTS
To prevent the system from being tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
Read/Write
(Click
Digits)
00100000
CLEARED ON READ
(TEMP BELOW LIMIT)
1. Detect the SMBALERT assertion.
12V/VC
OVT
FAN1
FAN2
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
F4P = 1, FAN4 OR THERM
TIMER IS OUT-OF-LIMIT
4. Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, 0x75).
Figure 22. Status Register 2
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1, indicates an open or short on D2+/D2– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates that THERM limit has been
exceeded if the THERM function is used.
5. Take the appropriate action for a given interrupt source.
6. Exit the Interrupt Handler.
7. Periodically poll the status registers. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This causes the SMBALERT output and status bits to behave as shown in Figure 24.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum speed.
HIGH LIMIT
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum speed.
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
“STICKY”
STATUS
BIT
Bit 0 (12V/VC) = 1, 12 V High or Low Limit has been
exceeded. If the VID code change function is used, this bit
indicates a change in VID code on the VID0 to VID5 inputs.
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
SMBALERT Interrupt Behavior
The ADT7463 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing Interrupt Handler software.
Figure 24. How Masking the Interrupt Source Affects
SMBALERT Output
Rev. 4 | Page 21 of 52 | www.onsemi.com
REV. C
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
–21–
ADT7463
Masking Interrupt Sources
To Assign THERM Functionality to a Pin
Interrupt Mask Registers 1 and 2 are located at Addresses
0x74 and 0x75. These allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source only prevents the SMBALERT
output from being asserted; the appropriate status bit gets set
as normal.
Pin 14 or Pin 20 can be configured as the THERM pin on the
ADT7463.
Interrupt Mask Register 1 (Reg. 0x74)
To configure Pin 20 as the THERM pin:
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 Temperature.
Bit 5 (LT) = 1, masks SMBALERT for Local Temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 Temperature.
Bit 3 (5V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.
Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel.
To enable the THERM functionality, users must first set the
THERM enable bit. The TH5V bit then determines which pin
the THERM functionality is enabled on (i.e., users cannot enable
THERM on two pins at once).
1. Set the TH5V bit (Bit 1) in the Configuration Register 4
(Address = 0x7D) = 1.
2. Set the THERM Enable Bit (Bit 1) in Configuration
Register 3 (Address = 0x78) = 1.
To configure Pin 14 as the THERM pin:
1. Set the TH5V bit (Bit 1) in the Configuration Register 4
(Address = 0x7D) = 0.
Bit 0 (2.5V) = 1, masks SMBALERT for 2.5 V channel.
2. Set the THERM Enable Bit (Bit 1) in Configuration
Register 3 (Address = 0x78) = 1.
Interrupt Mask Register 2 (Reg. 0x75)
THERM as an Input
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure. If the
TACH4 pin is being used as the THERM input, this bit masks
SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or
for a VID code change, depending on the function used.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default.
Pin 10 or Pin 22 can be reconfigured as an SMBALERT output
to signal out-of-limit conditions.
CONFIGURING PIN 22 AS SMBALERT OUTPUT
REGISTER
BIT SETTING
Config Reg 3 (Reg. 0x78)
<0> ALERT = 1
CONFIGURING PIN 22 AS SMBALERT OUTPUT
REGISTER
BIT SETTING
Config Reg 4 (Reg. 0x7D)
<0> AL2.5V = 1
When configured as an input, the user can time assertions on
the THERM pin. This can be useful for connecting to the
PROCHOT output of a CPU to gauge system performance.
See this data sheet for more information on timing THERM
assertions and generating ALERTs based on THERM.
The user can also setup the ADT7463 so when the THERM pin
is driven low externally the fans run at 100%. The fans run at
100% for the duration of the THERM pin being pulled low.
This is done by setting the BOOST bit (Bit 2) in Configuration
Register 3 (Address = 0x78) to 1. This only works if the fan is
already running, for example, in manual mode when the
current duty cycle is above 0x00 or in automatic mode when
the temperature is above TMIN. If the temperature is below
TMIN or if the duty cycle in manual mode is set to 0x00, then
pulling the THERM low externally has no effect. See Figure 25
for more information.
TMIN
THERM
THERM ASSERTED LOW AS AN INPUT
FANS DO NOT GO TO 100% SINCE
TEMPERATURE IS BELOW T MIN
THERM ASSERTED LOW AS AN INPUT
FANS GO TO 100% SINCE TEMPERATURE
IS ABOVE T MIN AND FANS ARE ALREADY
RUNNING
Figure 25. Asserting THERM Low as an Input in
Automatic Fan Speed Control Mode
Rev. 4 | Page 22 of 52 | www.onsemi.com
–22–
REV. C
ADT7463
THERM TIMER
The ADT7463 has an internal timer to measure THERM assertion time. For example, the THERM input may be connected
to the PROCHOT output of a Pentium 4 CPU and measure
system performance. The THERM input may also be connected
to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7463’s
THERM input and stopped on the negation of the pin. The
timer counts THERM times cumulatively, i.e., the timer
resumes counting on the next THERM assertion. The THERM
timer continues to accumulate THERM assertion times until
the timer is read (it is cleared on read) or until it reaches full
scale. If the counter reaches full scale, it stops at that reading
until cleared.
When using the THERM timer, be aware of the following:
After a THERM timer read (Reg. 0x79):
a) The contents of the timer get cleared on read.
b) The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming the THERM limit has been exceeded).
The 8-bit THERM timer register (Reg. 0x79) is designed such
that Bit 0 gets set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit
1 of the THERM timer gets set and Bit 0 now becomes the LSB
of the timer with a resolution of 22.76 ms.
7 6 5 4 3 2 1 0
THERM ASSERTED
22.76ms
ACCUMULATE THERM LOW
ASSERTION TIMES
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
45.52ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
a) The contents of the timer are cleared.
b) Bit 0 of the THERM timer is set to 1 (since a THERM
assertion is occurring).
c) The THERM timer increments from zero.
Generating SMBALERT Interrupts from THERM Events
0 0 0 0 0 0 0 1
THERM
THERM
TIMER
(REG. 0x79)
If the THERM timer is read during a THERM assertion, then
the following will happen:
d) If the THERM limit (Reg. 0x7A) = 0x00, then the F4P bit
gets set.
THERM
THERM
TIMER
(REG. 0x79)
Figure 26 illustrates how the THERM timer behaves as the
THERM input is asserted and negated. Bit 0 gets set on the first
THERM assertion detected. This bit remains set until such time
as the cumulative THERM assertions exceed 45.52 ms. At this
time, Bit 1 of the THERM timer gets set, and Bit 0 is cleared.
Bit 0 now reflects timer readings with a resolution of 22.76 ms.
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED 113.8ms
(91.04ms + 22.76ms)
Figure 26. Understanding the THERM Timer
The ADT7463 can generate SMBALERTs when a programmable
THERM limit has been exceeded. This allows the systems
designer to ignore brief, infrequent THERM assertions, while
capturing longer THERM events. Register 0x7A is the THERM
Limit Register. This 8-bit register allows a limit from 0 seconds
(first THERM assertion) to 5.825 seconds to be set before an
SMBALERT is generated. The THERM timer value is compared
with the contents of the THERM limit register. If the THERM
timer value exceeds the THERM limit value, then the F4P bit
(Bit 5) of Status Register 2 gets set, and an SMBALERT is
generated. Note that the F4P bit (Bit 5) of Mask Register 2
(Reg. 0x75) masks out SMBALERTs if this bit is set to 1, although the F4P bit of Interrupt Status Register 2 still gets set if
the THERM limit is exceeded.
Figure 27 is a Functional Block Diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM limit
value of 0x01 generates an SMBALERT once cumulative THERM
assertions exceed 45.52 ms.
Rev. 4 | Page 23 of 52 | www.onsemi.com
REV. C
–23–
ADT7463
THERM LIMIT
(REG. 0x7A)
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
THERM
TIMER
(REG. 0x79)
7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
LATCH
F4P BIT (BIT 5)
STATUS REGISTER 2
SMBALERT
RESET
CLEARED
ON READ
1 = MASK
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Figure 27. Functional Diagram of ADT7463’s THERM Monitoring Circuitry
Configuring the Desired THERM Behavior
1. Configure the desired pin as the THERM input.
Setting Bit 1 (THERM Enable) of Configuration Register 3
(Reg. 0x78) enables the THERM monitoring functionality.
This is enabled on Pin 14 by default.
Setting Bit 1 (TH5V) of Configuration Register 4
(Reg. 0x7D) enables THERM monitoring on Pin 20
(Bit 1 of Configuration Register 3 must also be set). Pin 14
can be used as TACH4.
2. Select the desired fan behavior for THERM events.
Setting Bit 2 (BOOST bit) of Configuration Register 3
(Reg. 0x78) causes all fans to run at 100% duty cycle
whenever THERM gets asserted. This allows fail-safe system
cooling. If this bit = 0, the fans run at their current settings
and are not affected by THERM events.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is generated
on the first THERM assertion, or only if a cumulative THERM
assertion time limit is exceeded. A value of 0x00 causes an
SMBALERT to be generated on the first THERM assertion.
5. Select a THERM monitoring time.
This is how often OS or BIOS level software checks the
THERM timer. For example, BIOS could read the THERM
timer once an hour to determine the cumulative THERM
assertion time. If, for example, the total THERM assertion
time is <22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system performance
is degrading significantly since THERM is asserting more
frequently on an hourly basis.
Alternatively, OS or BIOS level software can time-stamp
when the system is powered on. If an SMBALERT is generated due to the THERM limit being exceeded, another
time-stamp can be taken. The difference in time can be
calculated for a fixed THERM limit time. For example, if it
takes one week for a THERM limit of 2.914 s to be exceeded
and the next time it takes only 1 hour, then this is an
indication of a serious degradation in system performance.
3. Select whether THERM events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks
out SMBALERTs when the THERM limit value gets
exceeded. This bit should be cleared if SMBALERTs based
on THERM events are required.
Rev. 4 | Page 24 of 52 | www.onsemi.com
–24–
REV. C
ADT7463
pull-up on the gate is tied to 5 V. The MOSFET should also have
a low on resistance to ensure that there is not significant voltage
drop across the FET. This reduces the voltage applied across
the fan and therefore the maximum operating speed of the fan.
Configuring the ADT7463 THERM Pin as an Output
In addition to the ADT7463 being able to monitor THERM as
an input, the ADT7463 can optionally drive THERM low as an
output. The user can preprogram system critical thermal limits.
If the temperature exceeds a thermal limit by 0.25°C, THERM
asserts low. If the temperature is still above the thermal limit on
the next monitoring cycle, THERM stays low. THERM remains
asserted low until the temperature is equal to or below the
thermal limit. Since the temperature for that channel is measured only every monitoring cycle, once THERM asserts it is
guaranteed to remain low for at least one monitoring cycle.
Figure 29 shows how a 3-wire fan may be driven using PWM
control.
12V
10k�
TACH/AIN
The THERM pin can be configured to assert low if the
Remote 1, Local, or Remote 2 Temperature THERM limits get
exceeded by 0.25°C. The THERM limit registers are at locations 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of
Registers 0x5F, 0x60, and 0x61 enables the THERM output
feature for the Remote 1, Local, and Remote 2 Temperature
channels, respectively. Figure 28 shows how the THERM pin
asserts low as an output in the event of a critical overtemperature.
THERM LIMIT
+0.25�C
THERM LIMIT
10k�
4.7k�
ADT7463
12V
FAN
TACH
1N4148
3.3V
10k�
Q1
NDT3055L
PWM
Figure 29. Driving a 3-Wire Fan Using an
N-Channel MOSFET
Figure 29 uses a 10 kΩ pull-up resistor for the TACH signal. This
assumes that the TACH signal is open-collector from the fan. In
all cases, the TACH signal from the fan must be kept below 5 V
maximum to prevent damaging the ADT7463. If in doubt as to
whether the fan used has an open-collector or totem pole TACH
output, use one of the input signal conditioning circuits shown
in the Fan Speed Measurement section of the data sheet.
TEMP
THERM
Figure 30 shows a fan drive circuit using an NPN transistor
such as a general-purpose MMBT2222. While these devices are
inexpensive, they tend to have much lower current handling
capabilities and higher on resistance than MOSFETs. When
choosing a transistor, care should be taken to ensure that it
meets the fan’s current requirements.
ADT7463
MONITORING
CYCLE
Figure 28. Asserting THERM as an Output, Based
on Tripping THERM Limits
Ensure that the base resistor is chosen such that the transistor is
saturated when the fan is powered on.
FAN DRIVE USING PWM CONTROL
The ADT7463 uses pulse-width modulation (PWM) to control
fan speed. This relies on varying the duty cycle (or on/off ratio)
of a square wave applied to the fan to vary the fan speed. The
external circuitry required to drive a fan using PWM control is
extremely simple. A single NMOSFET is the only drive device
required. The specifications of the MOSFET depend on the
maximum current required by the fan being driven. Typical
notebook fans draw a nominal 170 mA, and so SOT devices can
be used where board space is a concern. In desktops, fans can
typically draw 250 mA to 300 mA each. If you drive several fans
in parallel from a single PWM output or drive larger server fans,
the MOSFET needs to handle the higher current requirements.
The only other stipulation is that the MOSFET should have a
gate voltage drive, VGS < 3.3 V for direct interfacing to the
PWM_OUT pin. VGS can be greater than 3.3 V as long as the
12V
–25–
12V
10k�
TACH/AIN
10k�
4.7k�
ADT7463
TACH
12V
FAN
1N4148
3.3V
470�
PWM
Q1
MMBT2222
Figure 30. Driving a 3-Wire Fan Using an NPN Transistor
Rev. 4 | Page 25 of 52 | www.onsemi.com
REV. C
12V
ADT7463
Driving Two Fans from PWM3
Driving up to Three Fans from PWM2
Note that the ADT7463 has four TACH inputs available for fan
speed measurement, but only three PWM drive outputs. If a
fourth fan is being used in the system, it should be driven from
the PWM3 output in parallel with the third fan. Figure 31 shows
how to drive two fans in parallel using low cost NPN transistors.
Figure 32 is the equivalent circuit using the NDT3055L MOSFET.
Note that since the MOSFET can handle up to 3.5 A, it is
simply a matter of connecting another fan directly in parallel
with the first.
TACH measurements for fans are synchronized to particular
PWM channels, e.g., TACH1 is synchronized to PWM1. TACH3
and TACH4 are both synchronized to PWM3 so PWM3 can
drive 2 fans. Alternatively, PWM2 can be programmed to
synchronize TACH2, TACH3, and TACH4 to the PWM2 output. This allows PWM2 to drive two or three fans. In this case,
the drive circuitry looks the same as shown in Figures 31 and 32.
The SYNC bit in Register 0x62 enables this function.
<4> (SYNC) ENHANCE ACOUSTICS REG 1 (0X62)
SYNC = 1 Synchronizes TACH2, TACH3, and TACH4
to PWM2.
Care should be taken in designing drive circuits with transistors
and FETs to ensure that the PWM pins are not required to
source current and that they sink less than the 8 mA maximum
current specified on the data sheet.
12V
3.3V
1N4148
3.3V
ADT7463
TACH3
1k�
TACH4
Q1
MMBT3904
PWM3
2.2k�
Q2
MMBT2222
10�
Q3
MMBT2222
10�
Figure 31. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
3.3V
10k�
TYPICAL
TACH4
3.3V
ADT7463
10k�
TYPICAL
TACH3
+V
+V
5V OR
12V FAN
1N4148
TACH
TACH
3.3V
10k�
TYPICAL
PWM3
5V OR 12V
FAN
Q1
NDT3055L
Figure 32. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Rev. 4 | Page 26 of 52 | www.onsemi.com
–26–
REV. C
ADT7463
Driving 2-Wire Fans
LAYING OUT 2-WIRE AND 3-WIRE FANS
Figure 33 shows how a 2-wire fan may be connected to the
ADT7463. This circuit allows the speed of a 2-wire fan to be
measured, even though the fan has no dedicated TACH signal.
A series resistor, RSENSE, in the fan circuit converts the fan
commutation pulses into a voltage. This is ac-coupled into the
ADT7463 through the 0.01 µF capacitor. On-chip signal
conditioning allows accurate monitoring of fan speed. The
value of RSENSE chosen depends upon the programmed input
threshold and the current drawn by the fan. For fans drawing
approximately 200 mA, a 2 Ω RSENSE value is suitable when the
threshold is programmed as 40 mV. For fans that draw more
current, such as larger desktop or server fans, RSENSE may be
reduced for the same programmed threshold. The smaller the
threshold programmed the better, since more voltage is developed
across the fan and the fan spins faster. Figure 34 shows a typical
plot of the sensing waveform at the TACH/AIN pin. The most
important thing is that the voltage spikes (either negative going
or positive going) are more than 40 mV in amplitude. This
allows fan speed to be reliably determined.
Figure 35 shows how to lay out a common circuit arrangement
for 2-wire and 3-wire fans. Some components are not populated,
depending on whether a 2-wire or 3-wire fan is being used.
+V
3.3V
PWM
1N4148
3.3V OR 5V
R2
R5
R3
PWM
Q1
MMBT2222
C1
TACH/AIN
R4
FOR 3-WIRE FANS:
POPULATE R1, R2, R3
R4 = 0�
C1 = UNPOPULATED
FOR 2-WIRE FANS:
POPULATE R4, C1
R1, R2, R3 UNPOPULATED
Figure 35. Planning for 2-Wire or 3-Wire Fans on a PCB
Pins 9, 11, 12, and 14 are open-drain TACH inputs intended
for fan speed measurement.
1N4148
10k�
TYPICAL
R1
TACH Inputs
5V OR
12V FAN
ADT7463
12V OR 5V
Signal conditioning in the ADT7463 accommodates the slow rise
and fall times typical of fan tachometer outputs. The maximum
input signal range is 0 V to 5 V, even where VCC is less than 5 V.
In the event that these inputs are supplied from fan outputs that
exceed 0 V to 5 V, either resistive attenuation of the fan signal
or diode clamping must be included to keep inputs within an
acceptable range.
Q1
NDT3055L
0.01�F
TACH/AIN
RSENSE
2�
TYPICAL
Figures 36a to 36d show circuits for most common fan
TACH outputs.
Figure 33. Driving a 2-Wire Fan
If the fan TACH output has a resistive pull-up to VCC, it can
be connected directly to the fan input, as shown in Figure 36a.
VCC
12V
PULL-UP
4.7k�
TYP
ADT7463
TACH
OUTPUT
TACH
FAN SPEED
COUNTER
Figure 36a. Fan with TACH Pull-Up to VCC
If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 5 V) then the fan output can be clamped with a
Zener diode, as shown in Figure 36b. The Zener diode voltage
should be chosen so that it is greater than VIH of the TACH
input but less than 5 V, allowing for the voltage tolerance of the
Zener. A value of between 3 V and 5 V is suitable.
Figure 34. Fan Speed Sensing Waveform at TACH/AIN Pin
Rev. 4 | Page 27 of 52 | www.onsemi.com
REV. C
–27–
ADT7463
12V
measured by gating an on-chip 90 kHz oscillator into the input
of a 16-bit counter for N periods of the fan TACH output
(Figure 37), so the accumulated count is actually proportional
to the fan tachometer period and inversely proportional to the
fan speed.
VCC
PULL-UP
4.7k�
TYP
ADT7463
TACH
OUTPUT
TACH
FAN SPEED
COUNTER
CLOCK
ZD1*
*CHOOSE ZD1 VOLTAGE APPROX 0.8 � VCC
PWM
Figure 36b. Fan with TACH Pull-Up to Voltage
> 5 V, e.g., 12 V, Clamped with Zener Diode
TACH
If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a totempole output, then a series resistor can be added to limit the Zener
current, as shown in Figure 36c. Alternatively, a resistive
attenuator may be used, as shown in Figure 36d.
1
2
3
4
R1 and R2 should be chosen such that
Figure 37. Fan Speed Measurement
2 V < VPULLUP × R2 / ( RPULLUP + R1 + R2) < 5 V
N, the number of pulses counted, is determined by the settings
of Register 0x7B (fan pulses per revolution register). This
register contains two bits for each fan, allowing one, two
(default), three, or four TACH pulses to be counted.
The fan inputs have an input resistance of nominally 160 kΩ
to ground, so this should be taken into account when calculating
resistor values.
With a pull-up voltage of 12 V and pull-up resistor less than 1 kΩ,
suitable values for R1 and R2 would be 100 kΩ and 47 kΩ. This
gives a high input voltage of 3.83 V.
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7463.
Reg. 0x28 TACH1 Low Byte = 0x00 Default
5V OR 12V
VCC
FAN
Reg. 0x29 TACH1 High Byte = 0x00 Default
Reg. 0x2A TACH2 Low Byte = 0x00 Default
ADT7463
PULL-UP TYP
<1k�
OR
TOTEM POLE
R1
10k�
TACH
OUTPUT
TACH
FAN SPEED
COUNTER
ZD1
ZENER*
VCC
ADT7463
<1k�
R1*
TACH
Reg. 0x2D TACH3 High Byte = 0x00 Default
Reg. 0x2F TACH4 High Byte = 0x00 Default
Figure 36c. Fan with Strong TACH Pull-Up to
> VCC or Totem-Pole Output, Clamped with Zener
and Resistor
TACH
OUTPUT
Reg. 0x2C TACH3 Low Byte = 0x00 Default
Reg. 0x2E TACH4 Low Byte = 0x00 Default
*CHOOSE ZD1 VOLTAGE APPROX 0.8 � VCC
12V
Reg. 0x2B TACH2 High Byte = 0x00 Default
FAN SPEED
COUNTER
R2*
*SEE TEXT
Figure 36d. Fan with Strong TACH Pull-Up to
> VCC or Totem-Pole Output, Attenuated with R1/R2
Reading Fan Speed from the ADT7463
If fan speeds are being measured, this involves a 2-register read
for each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers have been read from. This prevents erroneous TACH
readings.
The fan tachometer reading registers report back the number of
11.11 µs period clocks (90 kHz oscillator) gated to the fan
speed counter, from the rising edge of the first fan TACH pulse
to the rising edge of the third fan TACH pulse (assuming two
pulses per revolution are being counted). Since the device is
essentially measuring the fan TACH period, the higher the
count value the slower the fan is actually running. A 16-bit fan
tachometer reading of 0xFFFF indicates either that the fan has
stalled or is running very slowly (< 100 RPM).
HIGH LIMIT: > COMPARISON PERFORMED
Fan Speed Measurement
The fan counter does not count the fan TACH output pulses
directly because the fan speed may be less than 1,000 RPM and
it would take several seconds to accumulate a reasonably large
and accurate count. Instead, the period of the fan revolution is
Since the actual fan TACH period is being measured, exceeding
a fan TACH limit by 1 sets the appropriate status bit and can be
used to generate an SMBALERT.
Rev. 4 | Page 28 of 52 | www.onsemi.com
–28–
REV. C
ADT7463
00 = 1 Pulse per Revolution.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of
two bytes.
01 = 2 Pulses per Revolution.
10 = 3 Pulses per Revolution.
Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default
11 = 4 Pulses per Revolution.
Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default
2-Wire Fan Speed Measurements
Reg. 0x56 TACH2 Minimum Low Byte = 0xFF Default
The ADT7463 is capable of measuring the speed of 2-wire fans,
i.e., fans without TACH outputs. To do this, the fan must be
interfaced as shown in the Fan Drive Circuitry section of the
data sheet. In this case, the TACH inputs need to be reprogrammed as analog inputs, AIN.
Reg. 0x57 TACH2 Minimum High Byte = 0xFF Default
Reg. 0x58 TACH3 Minimum Low Byte = 0xFF Default
Reg. 0x59 TACH3 Minimum High Byte = 0xFF Default
Reg. 0x5A TACH4 Minimum Low Byte = 0xFF Default
CONFIGURATION REGISTER 2 (REG. 0x73)
Reg. 0x5B TACH4 Minimum High Byte = 0xFF Default
Bit 3 (AIN4) = 1, Pin 14 is reconfigured to measure the speed
of a 2-wire fan using an external sensing resistor and coupling
capacitor.
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every second.
The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78),
when set, updates the fan TACH readings every 250 ms.
Bit 2 (AIN3) = 1, Pin 9 is reconfigured to measure the speed of
a 2-wire fan using an external sensing resistor and coupling
capacitor.
If any of the fans are not being driven by a PWM channel but
are powered directly from 5 V or 12 V, its associated dc bit in
Configuration Register 3 should be set. This allows TACH
readings to be taken on a continuous basis for fans connected
directly to a dc source.
Bit 1 (AIN2) = 1, Pin 12 is reconfigured to measure the speed
of a 2-wire fan using an external sensing resistor and coupling
capacitor.
Bit 0 (AIN1) = 1, Pin 11 is reconfigured to measure the speed
of a 2-wire fan using an external sensing resistor and coupling
capacitor.
Calculating Fan Speed
Assuming a fan with a two pulses/revolution (and two pulses/
revolution being measured), fan speed is calculated by
AIN Switching Threshold
Fan Speed (RPM) = (90,000 � 60)/Fan TACH Reading
Having configured the TACH inputs as AIN inputs for 2-wire
measurements, users can select the sensing threshold for the
AIN signal.
where
Fan TACH Reading = 16-Bit Fan Tachometer Reading
CONFIGURATION REGISTER 4 (REG. 0X7D)
Example:
<3:2> AINL These two bits define the input threshold for
2-wire fan speed measurements.
00 = �20 mV
01 = �40 mV
10 = �80 mV
11 = �130 mV
TACH1 High Byte (Reg 0x29) = 0x17
TACH1 Low Byte (Reg 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143 Decimal
RPM = (f � 60)/Fan 1 TACH Reading
RPM = (90000 � 60)/6143
Fan Speed = 879 RPM
Fan Spin-Up
Fan Pulses per Revolution
Different fan models can output either 1, 2, 3, or 4 Tach pulses
per revolution. Once the number of fan Tach pulses has been
determined, it is programmed into the fan pulses per revolution
register (Reg. 0x7B) for each fan. Alternatively, this register can
be used to determine the number or pulses/revolution output by
a given fan. By plotting fan speed measurements at 100% speed
with different pulses/revolution setting, the smoothest graph with
the lowest ripple determines the correct pulses/revolution value.
Fan Pulses per Revolution Register
<1:0> FAN 1 Default = 2 Pulses per Revolution.
<3:2> FAN 2 Default = 2 Pulses per Revolution.
<5:4> FAN 3 Default = 2 Pulses per Revolution.
<7:6> FAN 4 Default = 2 Pulses per Revolution.
The ADT7463 has a unique fan spin-up function. It spins the
fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two pulses are detected, the
PWM duty cycle goes to the expected running value, e.g.,
33%. The advantage of this is that fans have different spin-up
characteristics and takes different times to overcome inertia. The
ADT7463 just runs the fans fast enough to overcome inertia and
are quieter on spin-up than fans programmed to spin-up for a
given spin-up time.
Fan Start-Up Timeout
To prevent false interrupts being generated as a fan spins up
(since it is below running speed), the ADT7463 includes a fan
start-up timeout function. This is the time limit allowed for two
TACH pulses to be detected on spin-up. For example, if 2-second
fan start-up timeout is chosen and no TACH pulses occur within
2 seconds of the start of spin-up, a fan fault is detected and flagged
in the interrupt status registers.
Rev. 4 | Page 29 of 52 | www.onsemi.com
REV. C
–29–
ADT7463
PWM1 CONFIGURATION (REG. 0x5C)
<2:0> SPIN
PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61)
These bits control the start-up timeout for PWM1.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
These bits control the start-up timeout for PWM2.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
PWM3 CONFIGURATION (REG. 0x5E)
<2:0> SPIN
These bits control the start-up timeout for PWM3.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
Manual Fan Speed Control
The ADT7463 allows the duty cycle of any PWM output
to be manually adjusted. This can be useful if users wish to
change fan speed in software or want to adjust PWM duty cycle
output for test purposes. Bits <7:5> of Registers 0x5C to 0x5E
(PWM Configuration) control the behavior of each PWM output.
PWM CONFIGURATION (REG. 0x5C to 0x5E)
Disabling Fan Start-Up Timeout
Although fan start-up makes fan spin-ups much quieter than
fixed-time spin-ups, the option exists to use fixed spin-up times.
Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40)
disables the spin-up for two TACH pulses. Instead, the fan spins
up for the fixed time as selected in Registers 0x5C to 0x5E.
PWM Logic State
The PWM outputs can be programmed high for 100% duty
cycle (noninverted) or low for 100% duty cycle (inverted).
PWM1 Configuration (Reg. 0x5C)
<4> INV
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM2 Configuration (Reg. 0x5D)
<4> INV
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM3 Configuration (Reg. 0x5E)
<4> INV
Fan Speed Control
The ADT7463 can control fan speed using two different modes.
The first is automatic fan speed control mode. In this mode, fan
speed is automatically varied with temperature and without CPU
intervention, once initial parameters are set up. The advantage of
this is in the case of the system hanging, the user is guaranteed
that the system is protected from overheating. The automatic fan
speed control incorporates a feature called dynamic TMIN calibration. This feature reduces the design effort required to program
the automatic fan speed control loop. For more information and
how to program the automatic fan speed control loop and dynamic
TMIN calibration, see the AN-613 Programming the Automatic
Fan Speed Control Loop application note (www.analog.com/
UploadedFiles/Application_Notes/331085006AN613_0.pdf).
The second fan speed control method is manual fan speed control
which is described in the next paragraph.
PWM2 CONFIGURATION (REG. 0x5D)
<2:0> SPIN
<2:0> FREQ 000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
0 = Logic High for 100% PWM Duty Cycle
1 = Logic Low for 100% PWM Duty Cycle
PWM Drive Frequency
The PWM drive frequency can be adjusted for the application.
Registers 0x5F to 0x61 configure the PWM frequency for
PWM1 to PWM3, respectively.
<7:5> BHVR 111 = Manual Mode
Once under manual control, each PWM output may be manually
updated by writing to Registers 0x30 to 0x32 (PWMx current
duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWMMIN register is
given by
Value (Decimal ) = PWM MIN 0.39
Example 1: For a PWM duty cycle of 50%,
Value (Decimal) = 50/0.39 = 128 Decimal
Value = 128 decimal or 0x80.
Example 2: For a PWM duty cycle of 33%,
Value (Decimal) = 33/0.39 = 85 Decimal
Value = 85 Decimal or 0x54.
PWM DUTY CYCLE REGISTERS
Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% Default)
Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% Default)
Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% Default)
Rev. 4 | Page 30 of 52 | www.onsemi.com
–30–
REV. C
ADT7463
By reading the PWMx current duty cycle registers, users can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.
Note that since other voltages can drop or be turned off during
a low power state, these voltage channels set status bits or
generate SMBALERTs. It is still necessary to mask out these
channels prior to entering a low power state using the interrupt
mask registers. When exiting the low power state, the mask bits
can be cleared. This prevents the device from generating
unwanted SMBALERTs during the low power state.
XOR TREE TEST MODE
The ADT7463 includes an XOR Tree Test Mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XOR Tree, it is
possible to detect opens or shorts on the system board. Figure 39
shows the signals that are exercised in the XOR Tree Test Mode.
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
VID0
VID1
Figure 38. Control PWM Duty Cycle Manually with
a Resolution of 0.39%
VID2
VID3
OPERATING FROM 3.3 V STANDBY
The ADT7463 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5
states, the core voltage of the processor is lowered in these states.
If using the dynamic TMIN mode, lowering the core voltage of
the processor would change the CPU temperature and change
the dynamics of the system under dynamic TMIN control. Likewise, when monitoring THERM, the THERM timer should
be disabled during these states.
VID4
TACH1
TACH2
TACH3
DYNAMIC TMIN CONTROL REGISTER 1 (REG. 0x36)
<1> VCCPLO = 1
When the power is supplied from 3.3 V STBY and the VCCP
voltage drops below the VCCP low limit, the following occurs:
TACH4
PWM2
• Status Bit 1 (VCCP) in Status Register 1 gets set.
• SMBALERT gets generated if enabled.
PWM3
• THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
• Dynamic TMIN control is disabled. This prevents TMIN
from being adjusted due to an S3 or S5 state.
• The ADT7463 is prevented from entering the shutdown
state.
Once the core voltage, VCCP, goes above the VCCP low limit, everything gets re-enabled and the system resumes normal operation.
Figure 39. XOR Tree Test
The XOR Tree Test is invoked by setting Bit 0 (XEN) of the
XOR Tree Test Enable Register (Reg. 0x6F).
POWER-ON DEFAULT
The ADT7463 does not monitor temperature and fan speed by
default on power-up. Monitoring of temperature and fan speed
is enabled by setting the Start Bit in Configuration Register 1
(Bit 0, Address 0×40) to 1. The fans run at full speed on powerup. This is because the BHVR bits (Bits 7:5) in the PWMx
configuration registers are set to 100 (fans run full speed) by default.
Rev. 4 | Page 31 of 52 | www.onsemi.com
REV. C
PWM1/XTO
–31–
ADT7463
Table IV. ADT7463 Registers
Address
R/W
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x3D
0x3E
0x3F
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
2.5 V Reading
VCCP Reading
VCC Reading
5 V Reading
12 V Reading
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
TACH1 Low Byte
TACH1 High Byte
TACH2 Low Byte
TACH2 High Byte
TACH3 Low Byte
TACH3 High Byte
TACH4 Low Byte
TACH4 High Byte
PWM1 Current Duty Cycle
PWM2 Current Duty Cycle
PWM3 Current Duty Cycle
Remote 1 Operating Point
Local Temp Operating Point
Remote 2 Operating Point
Dynamic TMIN Control Reg 1
Dynamic TMIN Control Reg 2
Device ID Register
Company ID Number
Revision Number
9
9
9
9
9
9
9
9
7
15
7
15
7
15
7
15
7
7
7
7
7
7
R2T
CYR2
7
7
VER
8
8
8
8
8
8
8
8
6
14
6
14
6
14
6
14
6
6
6
6
6
6
LT
CYR2
6
6
VER
7
7
7
7
7
7
7
7
5
13
5
13
5
13
5
13
5
5
5
5
5
5
R1T
CYL
5
5
VER
6
6
6
6
6
6
6
6
4
12
4
12
4
12
4
12
4
4
4
4
4
4
PHTR2
CYL
4
4
VER
5
5
5
5
5
5
5
5
3
11
3
11
3
11
3
11
3
3
3
3
3
3
PHTL
CYL
3
3
STP
4
4
4
4
4
4
4
4
2
10
2
10
2
10
2
10
2
2
2
2
2
2
PHTR1
CYR1
2
2
STP
3
3
3
3
3
3
3
3
1
9
1
9
1
9
1
9
1
1
1
1
1
1
VCCPLO
CYR1
1
1
STP
2
2
2
2
2
2
2
2
0
8
0
8
0
8
0
8
0
0
0
0
0
0
CYR2
CYR1
0
0
STP
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration Register 1
Interrupt Status Register 1
Interrupt Status Register 2
VID Register
2.5 V Low Limit
2.5 V High Limit
VCCP Low Limit
VCCP High Limit
VCC Low Limit
VCC High Limit
5 V Low Limit
5 V High Limit
12 V Low Limit
12 V High Limit
Remote 1 Temp Low Limit
Remote 1 Temp High Limit
Local Temp Low Limit
Local Temp High Limit
Remote 2 Temp Low Limit
Remote 2 Temp High Limit
TACH1 Minimum Low Byte
TACH1 Minimum High Byte
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
VCC
OOL
D2
VIDSEL
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
15
7
15
7
15
7
15
TODIS
R2T
D1
THLD
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
14
6
14
6
14
6
14
FSPDIS
LT
F4P
VID5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
13
5
13
5
13
5
13
V�I
R1T
FAN3
VID4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
12
4
12
4
12
4
12
FSPD
5V
FAN2
VID3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
11
3
11
3
11
3
11
RDY
VCC
FAN1
VID2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
10
2
10
2
10
2
10
LOCK
VCCP
OVT
VID1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
9
1
9
1
9
STRT
2.5V
12V/VC
VID0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
8
0
8
0
8
0x00
0x00
0x00
0x00
0x00
0x80
0x80
0x80
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0x64
0x64
0x64
0x00
0x00
0x27
0x41
0x62 or
0x6A
0x00
0x00
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x81
0x7F
0x81
0x7F
0x81
0x7F
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Lockable?
YES
YES
YES
YES
YES
YES
Rev. 4 | Page 32 of 52 | www.onsemi.com
–32–
REV. C
ADT7463
Table IV. ADT7463 Registers (continued)
Address
R/W Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable?
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM1 Configuration Register
PWM2 Configuration Register
PWM3 Configuration Register
Remote 1 TRANGE/PWM 1 Freq
Local Temp TRANGE/PWM 2 Freq
Remote 2 TRANGE/PWM 3 Freq
Enhance Acoustics Reg 1
Enhance Acoustics Reg 2
PWM1 Min Duty Cycle
PWM2 Min Duty Cycle
PWM3 Min Duty Cycle
Remote 1 Temp TMIN
Local Temp TMIN
Remote 2 Temp TMIN
Remote 1 THERM Limit
Local THERM Limit
Remote 2 THERM Limit
Remote 1 Local Temp Hysteresis
Remote 2 Temp Hysteresis
XOR Tree Test Enable
Remote 1 Temperature Offset
Local Temperature Offset
Remote 2 Temperature Offset
Configuration Register 2
Interrupt Mask 1 Register
Interrupt Mask 2 Register
Extended Resolution Register 1
Extended Resolution Register 2
Configuration Register 3
BHVR
BHVR
BHVR
RANGE
RANGE
RANGE
MIN3
EN2
7
7
7
7
7
7
7
7
7
HYSR1
HYSR2
RES
7
7
7
SHDN
OOL
D2
5V
TDM2
DC4
BHVR
BHVR
BHVR
RANGE
RANGE
RANGE
MIN2
ACOU2
6
6
6
6
6
6
6
6
6
HYSR1
HYSR2
RES
6
6
6
CONV
R2T
D1
5V
TDM2
DC3
BHVR
BHVR
BHVR
RANGE
RANGE
RANGE
MIN1
ACOU2
5
5
5
5
5
5
5
5
5
HYSR1
HYSR2
RES
5
5
5
ATTN
LT
F4P
VCC
LTMP
DC2
INV
INV
INV
RANGE
RANGE
RANGE
SYNC
ACOU2
4
4
4
4
4
4
4
4
4
HYSR1
HYSR2
RES
4
4
4
AVG
R1T
FAN3
VCC
LTMP
DC1
SLOW
SLOW
SLOW
THRM
THRM
THRM
EN1
EN3
3
3
3
3
3
3
3
3
3
HYSL
RES
RES
3
3
3
AIN4
5V
FAN2
VCCP
TDM1
FAST
SPIN
SPIN
SPIN
FREQ
FREQ
FREQ
ACOU
ACOU3
2
2
2
2
2
2
2
2
2
HYSL
RES
RES
2
2
2
AIN3
VCC
FAN1
VCCP
TDM1
BOOST
SPIN
SPIN
SPIN
FREQ
FREQ
FREQ
ACOU
ACOU3
0
0
0
0
0
0
0
0
0
HYSL
RES
XEN
0
0
0
AIN1
2.5V
12V/VC
2.5V
12V
ALERT
0x62
0x62
0x62
0xC4
0xC4
0xC4
0x00
0x00
0x80
0x80
0x80
0x5A
0x5A
0x5A
0x64
0x64
0x64
0x44
0x40
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
0x79
R
THERM Status Register
TMR
TMR
TMR
TMR
TMR
TMR
SPIN
SPIN
SPIN
FREQ
FREQ
FREQ
ACOU
ACOU3
1
1
1
1
1
1
1
1
1
HYSL
RES
RES
1
1
1
AIN2
VCCP
OVT
2.5V
12V
THERM
Enable
TMR
0x00
0x7A
0x7B
0x7D
0x7E
0x7F
R/W
R/W
R/W
R
R
THERM Limit Register
Fan Pulses per Revolution
Configuration Register 4
Test Register 1
Test Register 2
LIMT
FAN4
RES
LIMT
FAN4
RES
LIMT
LIMT LIMT LIMT
LIMT
FAN3
FAN3 FAN2 FAN2
FAN1
RES
RES
AINL
AINL
TH5V
DO NOT WRITE TO THESE REGISTERS
DO NOT WRITE TO THESE REGISTERS
ASRT\
TMR0
LIMT
FAN1
AL2.5V
Rev. 4 | Page 33 of 52 | www.onsemi.com
REV. C
–33–
0x00
0x55
0x00
0x00
0x00
YES
YES
YES
YES
ADT7463
Table V. Voltage Reading Registers (Power-On Default = 0x00)
Register Address
R/W
Description
0x20
0x21
0x22
0x23
0x24
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
2.5 V Reading (8 MSBs of reading)
VCCP Reading: holds processor core voltage measurement (8 MSBs of reading)
VCC Reading: measures VCC through the VCC pin (8 MSBs of reading)
5 V Reading (8 MSBs of reading)
12 V Reading (8 MSBs of reading)
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended
resolution registers get read, the associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers get frozen.
Table VI. Temperature Reading Registers (Power-On Default = 0x80)
Register Address
R/W
Description
0x25
0x26
0x27
Read-Only
Read-Only
Read-Only
Remote 1 Temperature Reading* (8 MSBs of reading)
Local Temperature Reading (8 MSBs of reading)
Remote 2 Temperature Reading* (8 MSBs of reading)
These temperature readings are in twos complement format.
*Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution bits of these readings
are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers get read, all associated MSB reading registers get frozen until read. Both the extended resolution registers and the MSB registers get frozen.
Table VII. Fan Tachometer Reading Registers (Power-On Default = 0x00)
Register Address
R/W
Description
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
Read-Only
TACH1 Low Byte
TACH1 High Byte
TACH2 Low Byte
TACH2 High Byte
TACH3 Low Byte
TACH3 High Byte
TACH4 Low Byte
TACH4 High Byte
These registers count the number of 11.11 µs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately measured. Since a valid fan tachometer reading requires that two bytes are read, the low byte MUST be read first. Both the low and high bytes are then frozen until read.
At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read in to these registers. This prevents false interrupts from
occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is:
1. Stalled or blocked (object jamming the fan).
2. Failed (internal circuitry destroyed).
3. Not populated (the ADT7463 expects to see a fan connected to
each TACH. If a fan is not connected to that TACH, its TACH
minimum high and low byte should be set to 0xFFFF).
4. Alternate function, e.g., TACH4 reconfigured as THERM pin.
5. 2-Wire Instead of 3-Wire Fan.
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ADT7463
Table VIII. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)
Register Address
R/W
Description
0x30
0x31
0x32
Read/Write
Read/Write
Read/Write
PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7463 reports the PWM
duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup,
these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table IX. Operating Point Registers (Power-On Default = 0x64)
Register Address
R/W*
Description
0x33
0x34
0x35
Read/Write
Read/Write
Read/Write
Remote 1 Operating Point Register (Default = 100�C)
Local Temp Operating Point Register (Default = 100�C)
Remote 2 Operating Point Register (Default = 100�C)
These registers set the target operating point for each temperature channel when the dynamic T MIN control feature is enabled.
The fans being controlled adjust to maintain temperature about an operating point.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7463
Table X. Register 0x36 – Dynamic TMIN Control Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<0>
CYR2
Read/Write
MSB of 3-Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic TMIN
Control Register 2 (Reg. 0x37). These three bits define the delay time between making subsequent TMIN adjustments in the control loop, in terms of number of monitoring cycles.
The system has associated thermal time constants that need to be found to optimize
the response of fans and the control loop.
<1>
VCCPLO
Read/Write
VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage
(VCCP) drops below its VCCP low limit value (Reg. 0x46), the following occurs:
• Status Bit 1 in Status Register 1 gets set.
• SMBALERT gets generated if enabled.
• PROCHOT monitoring is disabled.
• Dynamic TMIN control is disabled.
• The device is prevented from entering shutdown.
• Everything re-enabled once VCCP increases above VCCP low limit.
<2>
PHTR1
Read/Write
PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 Operating Point
Register if THERM gets asserted. The operating point contains the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTR1 = 0 ignores any THERM assertions on the
THERM pin. The Remote 1 Operating Point Register reflects its programmed value.
<3>
PHTL
Read/Write
PHTL = 1 copies the local channel’s current temperature to the Local Operating Point
Register if THERM gets asserted. The operating point contains the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTL = 0 ignores any THERM assertions on the
THERM pin. The Local Temp Operating Point Register reflects its programmed value.
<4>
PHTR2
Read/Write
PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 Operating Point
Register if THERM gets asserted. The operating point contains the temperature at
which THERM is asserted. This allows the system to run as quietly as possible without
system performance being affected. PHTR2 = 0 ignores any THERM assertions on the
THERM pin. The Remote 2 Operating Point Register reflects its programmed value.
<5>
R1T
Read/Write
R1T = 1 enables dynamic TMIN control on the Remote 1 Temperature channel. The
chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described
in the Automatic Fan Control section.
<6>
LT
Read/Write
LT = 1 enables dynamic TMIN control on the Local Temperature channel. The chosen
TMIN value is dynamically adjusted based on the current temperature, operating
point, and high and low limits for this zone. LT = 0 disables dynamic TMIN control. The
TMIN value chosen is not adjusted and the channel behaves as described in the
Automatic Fan Control section.
<7>
R2T
Read/Write
R2T = 1 enables dynamic TMIN control on the Remote 2 Temperature channel. The
chosen TMIN value is dynamically adjusted based on the current temperature,
operating point, and high and low limits for this zone. R2T = 0 disables dynamic TMIN
control. The TMIN value chosen is not adjusted and the channel behaves as
described in the Automatic Fan Control section.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7463
Table XI. Register 0x37 – Dynamic TMIN Control Register 2 (Power-On Default = 0x00)
Bit
Name
R/W*
Description
<2:0>
CYR1
Read/Write
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making
subsequent TMIN adjustments in the control loop for the Remote 1 channel, in terms of
number of monitoring cycles. The system has associated thermal time constants that
need to be found to optimize the response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
<5:3>
CYL
Read/Write
CYR2
Read/Write
Increase Cycle
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
3-Bit Local Temp Cycle Value. These three bits define the delay time between making
subsequent TMIN adjustments in the control loop for the local temperature channel, in
terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
<7:6>
Decrease Cycle
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
Decrease Cycle
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
Increase Cycle
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic
TMIN Control Register 1 (Reg. 0x36). These three bits define the delay time between
making subsequent TMIN adjustments in the control loop for the Remote 2 channel, in
terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
Decrease Cycle
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
Increase Cycle
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.
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Table XII. Register 0x40 – Configuration Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<0>
STRT
Read/Write
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up
limit settings. Note that the limit values programmed are preserved even if a Logic 0 is
written to this bit and the default settings are enabled. This bit becomes read-only and
cannot be changed once Bit 1 (LOCK bit) has been written. All limit registers should be
programmed by BIOS before setting this bit to 1. (Lockable.)
<1>
LOCK
Write Once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable
registers become read-only and cannot be modified until the ADT7463 is powered down
and powered up again. This prevents rogue programs such as viruses from modifying
critical system limit settings. (Lockable.)
<2>
RDY
Read-Only
This bit gets set to 1 by the ADT7463 to indicate that the device is fully powered-up
and ready to begin systems monitoring.
<3>
FSPD
Read/Write
When set to 1, this runs all fans at full speed. Power-on default = 0. This bit does not get
locked at any time.
<4>
V�I
Read/Write
BIOS should set this bit to a 1 when the ADT7463 is configured to measure current
from an ADI ADOPTTM VRM controller and measure the CPU’s core voltage. This
allows monitoring software to display CPU watts usage. (Lockable.)
<5>
FSPDIS
Read/Write
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high
for the entire fan spin-up timeout selected.
<6>
TODIS
Read/Write
When this bit is set to 1, the SMBus timeout feature is disabled. This allows the
ADT7463 to be used with SMBus controllers that cannot handle SMBus
timeouts. (Lockable.)
<7>
VCC
Read/Write
When this bit is set to 1, the ADT7463 rescales its VCC pin to measure a 5 V supply. If
this bit is 0, the ADT7463 measures VCC as a 3.3 V supply. (Lockable.)
Table XIII. Register 0x41 – Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<0>
2.5V
Read-Only
A one indicates the 2.5 V high or low limit has been exceeded. This bit gets cleared on
a read of the status register only if the error condition has subsided.
<1>
VCCP
Read-Only
A one indicates the VCCP high or low limit has been exceeded. This bit gets cleared on
a read of the status register only if the error condition has subsided.
<2>
VCC
Read-Only
A one indicates the VCC high or low limit has been exceeded. This bit gets cleared on a
read of the status register only if the error condition has subsided.
<3>
5V
Read-Only
A one indicates the 5 V high or low limit has been exceeded. This bit gets cleared on a
read of the status register only if the error condition has subsided.
<4>
R1T
Read-Only
A one indicates the Remote 1 Low or High temp limit has been exceeded. This bit gets
cleared on a read of the status register only if the error condition has subsided.
<5>
LT
Read-Only
A one indicates the Local Low or High temp limit has been exceeded. This bit gets
cleared on a read of the status register only if the error condition has subsided.
<6>
R2T
Read-Only
A one indicates the Remote 2 Low or High temp limit has been exceeded. This bit gets
cleared on a read of the status register only if the error condition has subsided.
<7>
OOL
Read-Only
A one indicates that an out-of-limit event has been latched in Status Register 2. This
bit is a logical OR of all status bits in Status Register 2. Software can test this bit in
isolation to determine whether any of the voltage, temperature, or fan speed readings
represented by Status Register 2 are out-of-limit. This saves the need to read Status
Register 2 every interrupt or polling cycle.
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ADT7463
Table XIV. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<0>
12V/VC
Read-Only
A one indicates the 12 V high or low limit has been exceeded. This bit gets cleared on a read
of the status register only if the error condition has subsided. If Pin 21 is configured as VID5,
this bit is the VID change bit. This bit gets set when the levels on VID0 to VID5 are different
than they were 11 µs previously. This can be used to generate an SMBALERT whenever
the VID code changes.
<1>
OVT
Read-Only
A one indicates that one of the THERM overtemperature limits has been exceeded. This
bit gets cleared on a read of the status register when the temperature drops below
THERM – THYST.
<2>
FAN1
Read-Only
A one indicates that Fan 1 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 1 output is off.
<3>
FAN2
Read-Only
A one indicates that Fan 2 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 2 output is off.
<4>
FAN3
Read-Only
A one indicates that Fan 3 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 3 output is off.
<5>
F4P
Read-Only
Read-Only
A one indicates that Fan 4 has dropped below minimum speed or has stalled.
This bit does NOT get set when the PWM 3 output is off.
If Pin 14 or Pin 20 is configured as the THERM timer input for THERM
monitoring, then this bit gets set when the THERM assertion time exceeds the
limit programmed in the THERM Limit Register (Reg. 0x7A).
<6>
D1
Read-Only
A one indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7>
D2
Read-Only
A one indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table XV. Register 0x43 – VID Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
<4:0>
VID[4:0]
Read-Only
The VID[4:0] inputs from the CPU to indicate the expected processor core voltage. On
power-up, these bits reflect the state of the VID pins even if monitoring is not enabled.
<5>
VID5
Read-Only
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, then the VID5 bit always
reads back 0 (power-on default).
<6>
THLD
Read/Write
This selects the input switching threshold for the VID inputs. THLD = 0 selects a
threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V). THLD = 1 lowers the switching threshold
to 0.6 V (VOL < 0.4 V, VIH > 0.8 V).
<7>
VIDSEL
Read/Write
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).
VIDSEL = 1 configures Pin 21 as the VID5 input. This also allows VID code
changes to be detected.
Table XVI. Voltage Limit Registers
Register Address
R/W
Description
Power-On Default
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
2.5 V Low Limit
2.5 V High Limit
VCCP Low Limit
VCCP High Limit
VCC Low Limit
VCC High Limit
5 V Low Limit
5 V High Limit
12 V Low Limit
12 V High Limit
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Setting the Configuration Register 1 Lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit ( ≤ comparison).
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ADT7463
Table XVII. Temperature Limit Registers
Register Address
R/W
Description
Power-On Default
0x4E
0x4F
0x50
0x51
0x52
0x53
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Remote 1 Temp Low Limit
Remote 1 Temp High Limit
Local Temp Low Limit
Local Temp High Limit
Remote 2 Temp Low Limit
Remote 2 Temp High Limit
0x81
0x7F
0x81
0x7F
0x81
0x7F
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the Interrupt Status Register. Setting the Configuration Register 1 Lock
bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit ( ≤ comparison).
Table XVIII. Fan Tachometer Limit Registers
Register Address
R/W
Description
Power-On Default
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
TACH1 Minimum Low Byte
TACH1 Minimum High Byte
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register
2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
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ADT7463
Table XIX. PWM Configuration Registers
Register Address
R/W*
Description
Power-On Default
0x5C
0x5D
0x5E
Read/Write
Read/Write
Read/Write
PWM1 Configuration
PWM2 Configuration
PWM3 Configuration
0x62
0x62
0x62
Bit
Name
R/W
Description
<2:0>
SPIN
Read/Write
These bits control the startup timeout for PWMx. The PWM output stays high until two
valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the
fan TACH measurement directly after the fan startup timeout period, then the TACH
measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH
Minimum High and Low Byte contains 0xFFFF or 0x0000, then the Status Register 2
Bit is not set, even if the fan has not started.
000 = No Startup Timeout.
001 = 100 ms.
010 = 250 ms (Default).
011 = 400 ms.
100 = 667 ms.
101 = 1 s.
110 = 2 s.
111 = 4 s.
<3>
SLOW
Read/Write
Slow = 1 makes the ramp rates for acoustic enhancement four times longer.
<4>
INV
Read/Write
This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty
cycle corresponds to a logic low output.
<7:5>
BHVR
Read/Write
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 Temp Controls PWMx (Automatic Fan Control Mode).
001 = Local Temp Controls PWMx (Automatic Fan Control Mode).
010 = Remote 2 Temp Controls PWMx (Automatic Fan Control Mode).
011 = PWMx Runs Full Speed (Default).
100 = PWMx Disabled.
101 = Fastest Speed Calculated by Local and Remote 2 Temp Controls PWMx.
110 = Fastest Speed Calculated by All 3 Temperature Channels Controls PWMx.
111 = Manual Mode. PWM Duty Cycle Registers (Reg 0x30 to 0x32) Become Writable.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7463
Table XX. TEMP TRANGE/PWM Frequency Registers
Register Address
R/W*
Description
Power-On Default
0x5F
0x60
0x61
Read/Write
Read/Write
Read/Write
Remote 1 TRANGE/PWM 1 Frequency
Local Temp TRANGE/PWM 2 Frequency
Remote 2 TRANGE/PWM 3 Frequency
0xC4
0xC4
0xC4
Bit
Name
Read/Write
Description
<2:0>
FREQ
Read/Write
These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
<3>
THRM
Read/Write
THRM = 1 causes the THERM pin (Pin 14 or 20) to assert low as an output when this
temperature channel’s THERM limit has been exceeded by 0.25�C. The THERM pin
remains asserted until the temperature is equal to or below the THERM limit. The
minimum time that THERM asserts for is one monitoring cycle. This allows clock modulation of devices that incorporate this feature.
THRM = 0 makes the THERM pin act as an input only, e.g., for Pentium 4 PROCHOT
monitoring, when Pin 14 or 20 is configured as THERM.
<7:4>
RANGE
Read/Write
These bits determine the PWM duty cycle versus the temperature slope for
automatic fan control.
0000 = 2�C
0001 = 2.5�C
0010 = 3.33�C
0011 = 4�C
0100 = 5�C
0101 = 6.67�C
0110 = 8�C
0111 = 10�C
1000 = 13.33�C
1001 = 16�C
1010 = 20�C
1011 = 26.67�C
1100 = 32�C (Default)
1101 = 40�C
1110 = 53.33�C
1111 = 80�C
*These registers become read-only when the Configuration Register 1 Lock bit is set. Any further attempts to write to these registers shall have no effect.
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ADT7463
Table XXI. Register 0x62 – Enhance Acoustics Reg 1 (Power-On Default = 0x00)
Bit
Name
R/W*
Description
<2:0>
ACOU
Read/Write
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate
determined by these bits. This feature enhances the acoustics of the fan being driven by
the PWM1 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
18 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
<3>
EN1
Read/Write
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
<4>
SYNC
Read/Write
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and
TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and
their speeds to be measured.
SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output.
<5>
MIN1
Read/Write
When the ADT7463 is in automatic fan control mode, this bit defines whether PWM 1
is off (0% duty cycle) or at PWM 1 Minimum Duty Cycle when the controlling temperature is below its TMIN – Hysteresis value.
0 = 0% duty cycle below TMIN – Hysteresis.
1 = PWM 1 Minimum Duty Cycle below TMIN – Hysteresis.
<6>
MIN2
Read/Write
When the ADT7463 is in automatic fan speed control mode, this bit defines whether
PWM 2 is off (0% duty cycle) or at PWM 2 Minimum Duty Cycle when the controlling
temperature is below its TMIN – Hysteresis value.
0 = 0% duty cycle below TMIN – Hysteresis.
1 = PWM 2 Minimum Duty Cycle below TMIN – Hysteresis.
<7>
MIN3
Read/Write
When the ADT7463 is in automatic fan speed control mode, this bit defines whether
PWM 3 is off (0% duty cycle) or at PWM 3 Minimum Duty Cycle when the controlling
temperature is below its TMIN – Hysteresis value.
0 = 0% duty cycle below TMIN – Hysteresis.
1 = PWM 3 Minimum Duty Cycle below TMIN – Hysteresis.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
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Table XXII. Register 0x63 – Enhance Acoustics Reg 2 (Power-On Default = 0x00)
Bit
Name
R/W*
Description
<2:0>
ACOU3
Read/Write
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate
determined by these bits. This effect enhances the acoustics of the fan being driven by the
PWM3 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
<3>
EN3
Read/Write
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
<6:4>
ACOU2
Read/Write
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2
jumping instantaneously to its newly calculated speed, PWM2 ramps gracefully at the
rate determined by these bits. This effect enhances the acoustics of the fans being driven
by the PWM2 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 s
001 = 2
17.6 s
010 = 3
11.8 s
011 = 5
7s
100 = 8
4.4 s
101 = 12
3s
110 = 24
1.6 s
111 = 48
0.8 s
<7>
EN2
Read/Write
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
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ADT7463
Table XXIII. PWM Min Duty Cycle Registers
Register Address
R/W*
Description
0x64
0x65
0x66
Bit
<7:0>
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
PWM1 Min Duty Cycle
0x80 (50% duty cycle)
PWM2 Min Duty Cycle
0x80 (50% duty cycle)
PWM3 Min Duty Cycle
0x80 (50% duty cycle)
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% duty cycle (Fan off).
0x40 = 25% duty cycle.
0x80 = 50% duty cycle.
0xFF = 100% duty cycle (Fan full speed).
Name
PWM Duty
Cycle
Power-On Default
*These registers become read-only when the ADT7463 is in automatic fan control mode.
Table XXIV. TMIN Registers
Register Address
R/W*
Description
Power-On Default
0x67
0x68
0x69
Read/Write
Read/Write
Read/Write
Remote 1 Temp TMIN
Local Temp TMIN
Remote 2 Temp TMIN
0x5A (90�C)
0x5A (90�C)
0x5A (90�C)
These are the T MIN registers for each temperature channel. When the temperature measured exceeds T MIN, the appropriate fan runs at minimum speed and
increases with temperature according to T RANGE.
*These registers become read-only when the Configuration Register 1 Lock bit is set. Any further attempts to write to these registers shall have no effect.
Table XXV. THERM Limit Registers
Register Address
R/W*
Description
Power-On Default
0x6A
0x6B
0x6C
Read/Write
Read/Write
Read/Write
Remote 1 THERM Limit
Local THERM Limit
Remote 2 THERM Limit
0x64 (100�C)
0x64 (100�C)
0x64 (100�C)
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the
system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is
disabled. The PWM output remains at 100% until the temperature drops below THERM Limit – Hysteresis. If the THERM pin is programmed as an output, then
exceeding these limits by 0.25�C can cause the THERM pin to assert low as an output.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to these registers will have no effect.
Table XXVI. Temperature Hysteresis Registers
Register Address
R/W*
Description
Power-On Default
0x6D
0x6E
Read/Write
Read/Write
Remote 1 Local Temp Hysteresis
Remote 2 Temp Hysteresis
0x44
0x40
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its
TMIN value, the fan remains running at PWM MIN duty cycle until the temperature = T MIN – Hysteresis. Up to 15°C of hysteresis may be assigned to any temperature
channel. The hysteresis value chosen also applies to that temperature channel if its THERM limit is exceeded. The PWM output being controlled goes to 100%
if the THERM limit is exceeded and remains at 100% until the temperature drops below THERM – Hysteresis. For acoustic reasons, it is recommended that
the hysteresis value not be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the
temperature is close to T MIN.
*These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to these registers will have no effect.
Rev. 4 | Page 45 of 52 | www.onsemi.com
REV. C
–45–
ADT7463
Table XXVII. XOR Tree Test Enable
Register Address
R/W*
Description
Power-On Default
0x00
0x6F
Read/Write
XOR Tree Test Enable Register
<0>
XEN
If the XEN bit is set to 1, the device enters the XOR Tree Test Mode. Clearing the bit
removes the device from the XOR Test Mode.
<7:1>
Reserved
Unused. Do not write to these bits.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXVIII. Remote 1 Temperature Offset
Register Address
R/W*
Description
Power-On Default
0x00
0x70
Read/Write
Remote 1 Temperature Offset
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 1 Temperature reading. This is to compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 0.25°C.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXIX. Local Temperature Offset
Register Address
R/W*
Description
Power-On Default
0x71
Read/Write
Local Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the local temperature reading. LSB value = 0.25°C.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXX. Remote 2 Temperature Offset
Register Address
R/W*
Description
Power-On Default
0x00
0x72
Read/Write
Remote 2 Temperature Offset
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 2 Temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.25°C.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Rev. 4 | Page 46 of 52 | www.onsemi.com
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REV. C
ADT7463
Table XXXI. Register 0x73 – Configuration Register 2 (Power-On Default = 0x00)
Bit
Name
R/W*
Description
0
AIN1
Read/Write
1
AIN2
Read/Write
2
AIN3
Read/Write
3
AIN4
Read/Write
4
AVG
Read/Write
5
ATTN
Read/Write
6
CONV
Read/Write
7
SHDN
Read/Write
AIN1 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN1 = 1, Pin 11 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration
Register 4 (Reg. 0x7D).
AIN2 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN2 = 1, Pin 12 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration
Register 4 (Reg. 0x7D).
AIN3 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN3 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration
Register 4 (Reg. 0x7D).
AIN4 = 0, Speed of 3-wire fans measured using the TACH output from the fan.
AIN4 = 1, Pin 14 is reconfigured to measure the speed of 2-wire fans using an external
sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration
Register 4 (Reg. 0x7D).
AVG = 1, Averaging on the temperature and voltage measurements is turned off. This
allows measurements on each channel to be made much faster.
ATTN = 1, the ADT7463 removes the attenuators from the 2.5 V, VCCP, 5 V, and
12 V inputs. The inputs can be used for other functions such as connecting up external
sensors.
CONV = 1, the ADT7463 is put into a single-channel ADC conversion mode. In this
mode, the ADT7463 can be made to read continuously from one input only, e.g.,
Remote 1 Temperature. It is also possible to start ADC conversions using an external
clock on Pin 11 by setting Bit 2 of Test Register 2 (Reg. 0x7F). This mode could be
useful if, for example, users wanted to characterize/profile CPU temperature quickly.
The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1 Min High
Byte Register (0x55).
Bits <7:5> Reg 0x55
Channel Selected
000
2.5 V
001
VCCP
010
VCC (3.3 V)
011
5V
100
12 V
101
Remote 1 Temperature
110
Local Temperature
111
Remote 2 Temperature
SHDN = 1, ADT7463 goes into shutdown mode. All PWM outputs assert low (or high
depending on state of INV bit) to switch off all fans. The PWM current duty cycle
registers read 0x00 to indicate that the fans are not being driven.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Rev. 4 | Page 47 of 52 | www.onsemi.com
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–47–
ADT7463
Table XXXII. Register 0x74 – Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)
Bit
Name
R/W
Description
0
1
2
3
4
2.5V
VCCP
VCC
5V
R1T
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
5
LT
Read/Write
6
R2T
Read/Write
7
OOL
Read/Write
A one masks SMBALERT for out-of-limit conditions on the 2.5 V channel.
A one masks SMBALERT for out-of-limit conditions on the VCCP channel.
A one masks SMBALERT for out-of-limit conditions on the VCC channel.
A one masks SMBALERT for out-of-limit conditions on the 5 V channel.
A one masks SMBALERT for out-of-limit conditions on the Remote 1
Temperature channel.
A one masks SMBALERT for out-of-limit conditions on the Local
Temperature channel.
A one masks SMBALERT for out-of-limit conditions on the Remote 2
Temperature channel.
A one masks SMBALERT for any out-of-limit condition in Status Register 2.
Table XXXIII. Register 0x75 – Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)
Bit
Name
R/W
Description
0
1
2
3
4
5
12V/VC
OVT
FAN1
FAN2
FAN3
F4P
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
6
7
D1
D2
Read/Write
Read/Write
A one masks SMBALERT for out-of-limit conditions on the 12 V channel.
A one masks SMBALERT for overtemperature THERM conditions.
A one masks SMBALERT for a Fan 1 Fault.
A one masks SMBALERT for a Fan 2 Fault.
A one masks SMBALERT for a Fan 3 Fault.
A one masks SMBALERT for a Fan 4 Fault. If the TACH4 pin is being used as the
THERM input, this bit masks SMBALERT for a THERM timer event.
A one masks SMBALERT for a diode open or short on Remote 1 channel.
A one masks SMBALERT for a diode open or short on Remote 2 channel.
Table XXXIV. Register 0x76 – Extended Resolution Register 1
Bit
Name
R/W
Description
<1:0>
<3:2>
<5:4>
<7:6>
2.5V
VCCP
VCC
5V
Read-Only
Read-Only
Read-Only
Read-Only
2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.
VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.
VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.
5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table XXXV. Register 0x77 – Extended Resolution Register 2
Bit
Name
R/W
<1:0>
<3:2>
12V
TDM1
Read-Only
Read-Only
<5:4>
LTMP
Read-Only
<7:6>
TDM2
Read-Only
Description
12 V LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.
Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1
Temperature measurement.
Local Temperature LSBs. Holds the 2 LSBs of the 10-bit Local
Temperature measurement.
Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2
Temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Rev. 4 | Page 48 of 52 | www.onsemi.com
–48–
REV. C
ADT7463
Table XXXVI. Register 0x78 – Configuration Register 3 (Power-On Default = 0x00)
Bit
Name
R/W*
Description
<0>
ALERT
Read/Write
<1>
THERM
Enable
Read/Write
<2>
BOOST
Read/Write
<3>
FAST
Read/Write
<4>
<5>
<6>
<7>
DC1
DC2
DC3
DC4
Read/Write
Read/Write
Read/Write
Read/Write
ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt
output to indicate out-of-limit error conditions.
THERM Enable = 1 enables THERM monitoring functionality on the pin
determined by Bit 1 (TH5V) of Configuration Register 4. When THERM is
asserted, fans can be run at full speed or a timer can be triggered to time how long
THERM has been asserted for.
BOOST = 1, assertion of THERM causes all fans to run at 100% duty cycle for
fail-safe cooling.
FAST = 1 enables fast TACH measurements on all channels. This increases the
TACH measurement rate from once per second, to once every 250 ms (4�).
DC1 = 1 enables TACH measurements to be continuously made on TACH1.
DC2 = 2 enables TACH measurements to be continuously made on TACH2.
DC3 = 1 enables TACH measurements to be continuously made on TACH3.
DC4 = 1 enables TACH measurements to be continuously made on TACH4.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XXXVII. Register 0x79 – THERM Status Register (Power-On Default = 0x00)
Bit
Name
R/W
Description
<7:1>
TMR
Read-Only
<0>
ASRT/TMR0 Read-Only
Times how long THERM input is asserted. These seven bits read zero until the
THERM assertion time exceeds 45.52 ms.
Gets set high on the assertion of the THERM input. Cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit gets set and becomes the LSB of the 8-bit TMR
reading. This allows THERM assertion times from 45.52 ms to 5.82 s to be reported
back with a resolution of 22.76 ms.
Bit
Name
R/W
Description
<7:0>
LIMT
Read/Write
Sets maximum THERM assertion length allowed, before an interrupt is generated. This
is an 8-bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms
to 5.82 s to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P)
of Interrupt Status Register 2 (Reg 0x42) is set. If the limit value is 0x00, then an
interrupt is generated immediately on the assertion of the THERM input.
Table XXXVIII. Register 0x7A – THERM Limit Register (Power-On Default = 0x00)
Rev. 4 | Page 49 of 52 | www.onsemi.com
REV. C
–49–
ADT7463
Table XXXIX. Register 0x7B – Fan Pulses per Revolution Register (Power-On Default = 0x55)
Bit
Name
R/W
Description
<1:0>
FAN1
Read/Write
<3:2>
FAN2
Read/Write
<5:4>
FAN3
Read/Write
<7:6>
FAN4
Read/Write
Sets number of pulses to be counted when measuring FAN 1 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring FAN 2 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring FAN 3 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Sets number of pulses to be counted when measuring FAN 4 speed. Can be used to
determine fan’s pulses per revolution for unknown fan type.
Pulses Counted
00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Table XL. Register 0x7D – Configuration Register 4 (Power-On Default = 0x00)
Bit
Name
R/W
Description
<0>
AL2.5V
Read/Write
<1>
TH5V
Read/Write
<3:2>
AINL
Read/Write
<7:4>
RES
AL2.5V = 1, Pin 22 (2.5V/SMBALERT) is configured as an SMBALERT interrupt
output to indicate out-of-limit error conditions. AL2.5V = 0, Pin 22 (2.5V/SMBALERT)
is configured as a 2.5 V measurement input.
TH5V = 1, Pin 20 (5V/THERM) is configured as THERM pin. For THERM
Monitoring, Bit 1 (THERM Timer) of Configuration Register 3 must also be set.
TH5V = 0, Pin 20 (5V/THERM) is configured as 5 V measurement input.
These two bits define the input threshold for 2-wire fan speed measurements:
00 = �20 mV
01 = �40 mV
10 = �80 mV
11 = �130 mV
Unused.
*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register will have no effect.
Table XLI. Register 0x7E – Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit
Name
Read/Write
Description
<7:0>
Reserved
Read-Only
Manufacturer’s Test Register. These bits are reserved for manufacturer’s test
purposes and should NOT be written to under normal operation.
Table XLII. Register 0x7F – Manufacturer’s Test Register 2 (Power-On Default = 0x00)
Bit
Name
Read/Write
Description
<7:0>
Reserved
Read-Only
Manufacturer’s Test Register. These bits are reserved for manufacturer’s test
purposes and should NOT be written to under normal operation.
Rev. 4 | Page 50 of 52 | www.onsemi.com
–50–
REV. C
Table XLI. Register 0x7E – Manufacturer’s Test Register 1 (Power-On Default = 0x00)
Bit
Name
Read/Write
Description
<7:0>
Reserved
Read-Only
Manufacturer’s Test Register. These bits are reserved for manufacturer’s test
purposes and should NOT be written to under normal operation.
ADT7463
Table XLII. Register 0x7F – Manufacturer’s
Test Register 2 (Power-On Default = 0x00)
OUTLINE DIMENSIONS
Bit
<7:0>
Name
Reserved
Read/Write
Description
24-Lead
Shrink Small
[QSOP]
Manufacturer’s
Test Outline
Register.Package
These bits
are reserved for manufacturer’s test
(RQ-24)
purposes and should NOT be written to under normal operation.
Read-Only
Dimensions shown in inches
–50–
0.341
BSC
24
REV. C
13
ADT7463
0.154
BSC
0.236
BSC
1
12
OUTLINE DIMENSIONS
PIN 1
0.069
0.065
24-Lead
Shrink Small0.053
Outline Package [QSOP]
0.049
(RQ-24)
Dimensions shown in inches
0.010
0.004
0.025
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8�
0�
0.050
0.016
0.341
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AE
24
13
0.154
BSC
1
0.236
BSC
12
PIN 1
0.069
0.053
0.065
0.049
0.010
0.004
COPLANARITY
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.010
0.006
COMPLIANT TO JEDEC STANDARDS MO-137AE
Rev. 4 | Page 51 of 52 | www.onsemi.com
REV. C
–51–
8�
0�
0.050
0.016
ADT7463
ADT7463
Revision History
Location
Revision
History
Page
10/04—Data
Changed
from
REV. B to REV. C.
01/08—Rev. 4:Sheet
Conversion
to ON
Semiconductor
Location
Page
Change
Table IV . . GUIDE
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RECOMMENDED
IMPLEMENTATION
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THERM
Functionality
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Renumbered
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Figure 25
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section. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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POWER-ON
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Table XXI
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Table
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Table IV . .DEFAULT
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Table IV
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Updated Table
32
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OUTLINE
DIMENSIONS
Updated Table
XXXVI
. . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 51
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Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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