PC133/PC100 Unbuffered DIMM M366S1723DTS M366S1723DTS SDRAM DIMM 16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M366S1723DTS is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S1723DTS consists of eight CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. One 0.1uF and one 0.22 uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S1723DTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range Part No. M366S1723DTS-C/L7C 133MHz (7.5ns @ CL=2) M366S1723DTS-C/L7A 133MHz (7.5ns @ CL=3) M366S1723DTS-C/L1H 100MHz (10ns @ CL=2) M366S1723DTS-C/L1L 100MHz (10ns @ CL=3) • • • • • Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,375mil), single sided component PIN CONFIGURATIONS (Front side/back side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 PIN NAMES Pin Front Pin Back Pin Back Pin Back 29 DQM1 57 DQ18 85 58 DQ19 86 CS0 30 59 87 VDD 31 DU 60 DQ20 88 32 VSS 61 89 NC 33 A0 62 *VREF 90 34 A2 63 *CKE1 91 35 A4 64 92 VSS 36 A6 65 DQ21 93 37 A8 38 A10/AP 66 DQ22 94 67 DQ23 95 39 BA1 68 96 VSS 40 VDD 69 DQ24 97 41 VDD 42 CLK0 70 DQ25 98 71 DQ26 99 43 VSS 72 DQ27 100 44 DU 73 45 CS2 VDD 101 46 DQM2 74 DQ28 102 47 DQM3 75 DQ29 103 76 DQ30 104 48 DU 77 DQ31 105 49 VDD 78 50 VSS 106 NC 79 CLK2 107 51 NC NC 108 52 *CB2 80 53 *CB3 81 NC 109 82 **SDA 110 54 VSS 55 DQ16 83 **SCL 111 VDD 112 56 DQ17 84 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 DQM5 *CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CLK1 *A12 VSS CKE0 *CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS *CLK3 NC **SA0 **SA1 **SA2 VDD Pin Front Pin Front Max Freq. (Speed) Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0, CLK2 Clock input CKE0 Clock enable input CS0, CS2 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground *VREF Power supply for reference SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS FUNCTIONAL BLOCK DIAGRAM • CS0 DQM0 DQM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U0 DQM1 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U4 DQM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U1 DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 • CS2 DQM2 DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 DQM3 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U6 DQM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 U7 Serial PD A0 ~ An, BA0 & 1 SDRAM U0 ~ U7 SCL RAS SDRAM U0 ~ U7 47KΩ CAS SDRAM U0 ~ U7 WE SDRAM U0 ~ U7 CKE0 SDRAM U0 ~ U7 WP A0 SDA A1 SA0 SA1 SA2 10Ω CLK0/2 • VDD • • Vss Every DQpin of SDRAM • • 10Ω • • U0/U2 U4/U6 • 10Ω DQn A2 U1/U3 U5/U7 3.3pF CLK1/3 One 0.1uF and one 0.22 uF Cap. To all SDRAMs per each SDRAM 10pF Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 8 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) CAPACITANCE Pin Address (A0 ~ A11, BA0 ~ BA1) RAS, CAS, WE Symbol Min Max Unit CADD 25 45 pF CIN 25 45 pF CKE (CKE0) CCKE 25 45 pF Clock (CLK0, CLK2) CCLK 15 21 pF CS (CS0, CS2) CCS 15 25 pF DQM (DQM0 ~ DQM7) CDQM 8 12 pF DQ (DQ0 ~ DQ63) COUT 9 12 pF Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3P ICC3PS ICC3N ICC3NS Version Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA - 7C -7A -1H -1L 800 720 720 720 Unit Note mA 1 CKE ≤ VIL(max), tCC = 10ns 16 CKE & CLK ≤ VIL(max), tCC = ∞ 16 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 160 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 80 CKE ≤ VIL(max), tCC = 10ns 40 CKE & CLK ≤ VIL(max), tCC = ∞ 40 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 240 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 200 mA mA mA mA ICC4 IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs 880 880 800 800 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 1760 1600 1520 1520 mA 2 Self refresh current ICC6 CKE ≤ 0.2V Operating current (Burst mode) C 16 L 6.4 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ) Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω • Output 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA • Output Z0 = 50Ω • 50pF 50pF 870Ω • (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol - 7C - 7A - 1H -1L Unit Note Row active to row active delay tRRD(min) 15 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 20 20 20 ns 1 tRP(min) 15 20 20 20 ns 1 tRAS(min) 45 45 50 50 ns 1 Row precharge time Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay 100 ns 1 2 CLK 2,5 tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Number of valid output data 60 65 us 70 CAS latency=3 2 CAS latency=2 1 70 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter - 7C Symbol Min CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 tCC CAS latency=2 CAS latency=3 7.5 Max 1000 7.5 tSAC CAS latency=2 CAS latency=3 - 7A tOH CAS latency=2 Min 7.5 - 1H Max 1000 10 Min 10 - 1L Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 5.4 5.4 6 6 5.4 6 6 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 5.4 6 6 5.4 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address Auto precharge disable H X L H L H X V Write & column address Auto precharge disable Auto precharge enable X L H L L X H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A 0 ~ A9) V L Column address (A 0 ~ A9) H All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Clock suspend or active power down 3 3 L Bank selection 1,2 X X H Note 3 H Precharge A 11, A9 ~ A 0 L Bank active & row addr. Burst stop A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS PACKAGE DIMENSIONS Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.350 (8.890) 0.700 (17.780) 0.250 (6.350) .450 (11.430) C 0.100 Min B A .118DIA ± 0.004 (3.000DIA ± 0.100) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) (2.540 Min) 0.118 0.157 ± 0.004 (4.000 ± 0.100) (3.000) 1.375 (34.925) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) 4.550 (115.57) 0.165 Min (4.19 Min) 0.100 Max (2.54 Max) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.050 (1.270) Detail C Tolerances : ± .005(.13) unless otherwise specified The used device is 16Mx8 SDRAM, TSOP SDRAM Part No. : K4S280832D Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS M366S1723DTS-L7C/L7A/L1H/L1L,C7C/C7A/C1H/C1L, (Intel SPD 1.2B ver. base) • • • • • • • • Organization : 16Mx64 Composition : 16Mx8 *8 Used component part # : K4S280832D-TL7C/TL75/TL1H/TL1L,TC7C/TC75/TC1H/TC1L # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided component Refresh : 4K/64ms Contents ; Byte # Function Supported Function Described -7C -7A -1H Hex value -1L -7C -7A -1H 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly 128bytes 80h 256bytes (2K-bit) 08h Note -1L SDRAM 04h 12 0Ch 1 10 0Ah 1 1 row 01h - 00h LVTTL 01h 9 SDRAM cycle time @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 06h 06h 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General Non parity 00h 15.625us, support self refresh 80h x8 08h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 2&3 2&3 2&3 04h 2&3 06h 06h 0 CLK 01h 0 CLK 01h Non-buffered, non-registered 00h & redundant addressing +/- 10% voltage tolerance, 0Eh Burst Read Single bit Write precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2 24 SDRAM access time from clock @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 14h 14h 26 SDRAM access time from clock @CAS latency of 1 27 Minimum row precharge time (=t RP) - 00h 15ns 20ns 00h 20ns 20ns 0Fh 14h 28 Minimum row active to row active delay (tRRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h 31 Module Row density 32 Command and address signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 33 Command and address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 20h 1 row of 128MB Rev. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M366S1723DTS Byte # 35 36~61 Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 64 72 Hex value -7A -1H -1L -7C -7A -1H -1L 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 16h 46h - 00h Intel Rev 1.2B 12h - 6Eh AFh Manufacturer JEDEC ID code Samsung CEh ...... Manufacturer JEDEC ID code Samsung 00h Onyang Korea 01h 4Dh Manufacturing location 73 Manufacturer part # (Memory module) M 74 Manufacturer part # (DIMM Configuration) 3 33h 75 Manufacturer part # (Data bits) Blank 20h 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 6 36h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 1 31h 80 ...... Manufacturer part # (Module depth) 7 37h 81 Manufacturer part # (Refresh, #of banks in Comp. & Interface) 2 32h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) S 53h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) L/C 4Ch/43h 88 Manufacturer part # (Minimum cycle time) 7 7 89 Manufacturer part # (Minimum cycle time) C A 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Year) 94 Manufacturing date (Week) 95~98 Assembly serial # 99~125 Manufacturer specific data (may be used in future) 126 System frequency for 100MHz 127 PC100 specification details 128+ Unused storage locations Note -7C Superset information (maybe used in future) 62 65~71 Function Supported Function Described 1 1 37h 37h H L 43h 41h 31h 31h 48h 4Ch Blank 20h S 53h D-die (5th Gen.) 44h - - 3 - - 3 - - 4 Undefined - 100MHz Detailed PC100 Information Undefined 64h AFh AFh AFh ADh - Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. Rev. 0.1 Sept. 2001