MCP7940N
Low-Cost I2C™ Real-Time Clock/Calendar
with SRAM and Battery Switchover
Device Selection Table
Part Number
MCP7940N
Description:
SRAM
(Bytes)
64
Features:
• Real-Time Clock/Calendar (RTCC), Battery
Backed:
- Hours, Minutes, Seconds, Day of Week, Day,
Month and Year
- Dual alarm with single output
• On-Chip Digital Trimming/Calibration:
- Range -127 to +127 ppm
- Resolution 1 ppm
• Programmable Open-Drain Output Control:
- CLKOUT with 4 selectable frequencies
- Alarm output
• 64 Bytes SRAM, Battery Backed
• Automatic VCC Switchover to VBAT Backup
Supply
• Power-Fail Time-Stamp for Battery Switchover
• Low-Power CMOS Technology:
- Dynamic Current: 400 A max read
- Battery Backup Current: <700nA @ 1.8V
• 100 kHz and 400 kHz Compatibility
• ESD Protection >4,000V
• Packages include 8-Lead SOIC, TSSOP, 2x3
TDFN, MSOP
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
2011-2013 Microchip Technology Inc.
The MCP7940N series of low-power Real-Time Clocks
(RTC) uses digital timing compensation for an accurate
clock/calendar, a programmable output control for
versatility, a power sense circuit that automatically
switches to the backup supply. Using a low-cost 32.768
kHz crystal, it tracks time using several internal
registers. For communication, the MCP7940N uses the
I2C™ bus.
The clock/calendar automatically adjusts for months
with fewer than 31 days, including corrections for
leap years. The clock operates in either the 24-hour
or 12-hour format with an AM/PM indicator and
settable alarm(s) to the second, minute, hour, day of
the week, date or month. Using the programmable
CLKOUT, frequencies of 32.768, 8.192 and 4.096
kHz and 1 Hz can be generated from the external
crystal.
The device is fully accessible through the serial
interface while VCC is between 1.8V and 5.5V, but can
operate down to 1.3V for timekeeping and SRAM
retention only.
The RTC series of devices are available in the standard
8-lead SOIC, TSSOP, MSOP and 2x3 TDFN packages.
Package Types
MSOP
X1
1
8
VCC
X2
2
7
MFP
VBAT
3
6
SCL
VSS
4
5
SDA
TDFN
X1 1
X2 2
VBAT 3
VSS 4
SOIC, TSSOP
X1
1
8
VCC
X2
2
7
MFP
VBAT
3
6
SCL
VSS
4
5
SDA
8 VCC
7 MFP
6 SCL
5 SDA
DS25010E-page 1
MCP7940N
FIGURE 1-1:
TYPICAL OPERATING
CIRCUIT
RTCC
Oscillator
X1
Time-Stamp/
Alarms
X2
VCC
SRAM
I2C™
VBAT Switch
VBAT
MFP
SCL
VSS
SDA
FIGURE 1-2:
SCHEMATIC
SYSTEM VCC
C1
Note 1
R1
R2
R3
X1
VCC
X2
MFP
MFP
SCL
SCL
SDA
SDA
CX1
CX2
VBAT
D1
VSS
R4
MCP7940N
X1
C2
BAT
Note 1: A 100nF Capacitor should be placed as close to the Vcc pin on the
device as possible.
DS25010E-page 2
Suggested Values:
C1
100nF
CX1, CX2
See Text
C2
100pF
R1
10K
R2,3
2.2K
1K
R4
D1
Schottky
BAT
Back-up Supply
X1
32.768 kHz Crystal
(See Text)
2011-2013 Microchip Technology Inc.
MCP7940N
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Extended (E):
VCC = +1.8V to 5.5V
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
—
SCL, SDA pins
—
—
—
—
D1
VIH
High-level input voltage
0.7 VCC
—
V
—
D2
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
VCC = 2.5V to 5.5V
D3
VHYS
Hysteresis of Schmitt Trig- 0.05 VCC
ger inputs
(SDA, SCL pins)
—
V
(Note 1)
D4
VOL
Low-level output voltage
(MFP, SDA)
—
0.40
V
IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D5
ILI
Input leakage current
—
±1
A
VIN = VSS or VCC
D6
ILO
Output leakage current
—
±1
A
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(SDA, SCL and MFP)
—
10
pF
VCC = 5.0V (Note 1)
TA = 25°C, f = 400 kHz
D8
ICC Read
Operating current
SRAM
—
300
A
VCC = 5.5V, SCL = 400 kHz
ICC Write
—
400
A
VCC = 5.5V, SCL = 400 kHz
ICCS
Standby current
—
1
A
5
A
VCC = 5.5V, SCL = SDA = VCC
(I-temp)
VCC = 5.5V, SCL = SDA = VCC
(E-temp)
D9
D10
IBAT
Operating Current
IVCC
—
700
—
nA
VBAT = 1.8V @ 25°C, Figure 2-1
—
5
—
A
VCC = 3.6V @ 25°C, Figure 2-2
(Note 2)
VBAT Change Over
1.3
1.7
V
1.5V typical at TAMB = 25°C
VCCFT
VCC Fall Time (Note 1)
300
—
s
From VTRIP (max) to VTRIP (min)
VCCRT
VCC Rise Time (Note 1)
0
—
s
From VTRIP (min) to VTRIP (max)
D14
VBAT
VBAT Voltage Range
(Note 1)
1.3
5.5
V
—
D15
COSC
Oscillator Pin
Capacitance
—
—
pF
(Note 1)
D11
VTRIP
D12
D13
Note 1:
2:
3
This parameter is periodically sampled and not 100% tested.
Standby with oscillator running.
2011-2013 Microchip Technology Inc.
DS25010E-page 3
MCP7940N
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Extended (E):
VCC = +1.8V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
1
FCLK
Clock frequency
—
—
100
400
kHz
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
2
THIGH
Clock high time
4000
600
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
3
TLOW
Clock low time
4700
1300
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
4
TR
SDA and SCL rise time
(Note 1)
—
—
1000
300
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
5
TF
SDA and SCL fall time
(Note 1)
—
—
1000
300
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
6
THD:STA Start condition hold time
4000
600
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
7
TSU:STA
4700
600
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
8
THD:DAT Data input hold time
0
—
ns
9
TSU:DAT
Data input setup time
250
100
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
10
TSU:STO
Stop condition setup time
4000
600
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
11
TAA
Output valid from clock
—
—
3500
900
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
—
—
ns
1.8V VCC < 2.5V (I, E-temp)
2.5V VCC 5.5V (I, E-temp)
13
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 2)
Start condition setup time
Note 1: Not 100% tested.
2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
DS25010E-page 4
2011-2013 Microchip Technology Inc.
MCP7940N
FIGURE 1-3:
BUS TIMING DATA
5
SCL
7
SDA
In
D4
2
3
8
9
4
10
6
13
11
12
SDA
Out
2011-2013 Microchip Technology Inc.
DS25010E-page 5
MCP7940N
2.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
IBAT (nA)
FIGURE 2-1:
1400
1300
1200
1100
1000
900
800
700
600
500
400
IBAT VS. VBAT
-40
0
25
65
85
1
1.5
2
2.5
3
3.5
4
VBAT (V)
FIGURE 2-2:
IVCC ACTIVE VS. VCC @ 25°C
16
14
IVCC (UA)
12
10
8
6
4
2
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
DS25010E-page 6
2011-2013 Microchip Technology Inc.
MCP7940N
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN DESCRIPTIONS
Pin Name
Vss
SDA
SCL
X1
X2
VBAT
MFP
Vcc
Pin Function
Ground
Bidirectional Serial Data
Serial Clock
Xtal Input, External Oscillator Input
Xtal Output
Battery Backup Input (3V Typ)
Multi-Function Pin
Power Supply
FIGURE 3-1:
DEVICE PINOUTS
SOIC/DFN/MSOP/TSSOP
3.1
X1
1
8
Vcc
X2
2
7
MFP
VBAT
3
6
SCL
Vss
4
5
SDA
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VCC (typically 10 k for 100 kHz, 2 k for
400 kHz). For normal data transfer, SDA is allowed to
change only during SCL low. Changes during SCL high
are reserved for indicating the Start and Stop
conditions.
3.2
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
3.3
X1, X2
External Crystal Pins.
3.4
MFP
Open-drain pin used for alarm and clock-out.
3.5
VBAT
Input for backup supply to maintain RTCC and SRAM
during the time when VCC is below VTRIP.
2011-2013 Microchip Technology Inc.
DS25010E-page 7
MCP7940N
4.0
I2C BUS CHARACTERISTICS
4.1.1.3
4.1
I2C Interface
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
The MCP7940N supports a bidirectional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the Start
and Stop conditions, while the MCP7940N works as
slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
4.1.1
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1.1.1
Bus not Busy (A)
Both data and clock lines remain high.
4.1.1.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
FIGURE 4-1:
(A)
4.1.1.4
Stop Data Transfer (C)
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.1.1.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (MCP7940N) will leave the data line high to
enable the master to generate the Stop condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
DS25010E-page 8
Data
Allowed
to Change
Stop
Condition
2011-2013 Microchip Technology Inc.
MCP7940N
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
SCL
2
3
SDA
4
5
6
7
8
9
1
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 4-2).
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
FIGURE 4-3:
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
4.1.2
2
the data byte (Figure 4-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7940N monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving an ‘1101111’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
MCP7940N will select a read or write operation.
ADDRESS SEQUENCE BIT ASSIGNMENTS
SRAM RTCC CONTROL BYTE
1
1
0
1
1
1
1 R/W
ADDRESS BYTE
X
•
•
•
•
•
•
A
0
CONTROL
CODE
X = Don’t Care
2011-2013 Microchip Technology Inc.
DS25010E-page 9
MCP7940N
5.0
RTCC FUNCTIONALITY
The MCP7940N family is a highly integrated RTCC.
On-board time and date counters are driven from a lowpower oscillator to maintain the time and date. An
integrated VCC switch enables the device to maintain
the time and date and also the contents of the SRAM
during a VCC power failure.
5.1
RTCC MEMORY MAP
The RTCC registers are contained in addresses
0x00h-0x1fh. 64 bytes of user-accessable SRAM are
located in the address range 0x20-0x5f. The SRAM
memory is a separate block from the RTCC control
and Configuration registers. All SRAM locations are
battery-backed-up during a VCC power fail. Unused
locations are not accessible, MCP7940N will noACK
after the address byte if the address is out of range, as
shown in the shaded region of the memory map in
Figure 5-1. The shaded areas are not implemented
and read as ‘0’. No error checking is provided when
loading time and date registers.
• Addresses 0x00h-0x06h are the RTCC Time and
Date registers. These are read/write registers.
Care must be taken when accessing these
registers while the oscillator is running.
• Incorrect data can appear in the Time and Date
registers if a write is attempted during the time
frame where these internal registers are being
incremented. The user can minimize the likelihood of data corruption by ensuring that any
writes to the Time and Date registers occur before
the contents of the second register reach a value
of 0x59H.
• Addresses 0x07h-0x09h are the device Configuration and Calibration.
• Addresses 0x0Ah-0x10h are the Alarm 0
registers. These are used to set up the Alarm 0,
the Interrupt polarity and the Alarm 0 compare.
• Addresses 0x11h-0x17h are the same as 0x0Bh0x11h but are used for Alarm 1.
• Addresses 0x18h-0x1Fh are used for the timestamp feature.
The detailed memory map is shown in Table 5-1.
DS25010E-page 10
FIGURE 5-1:
MEMORY MAP
0x00
Time and Date
0x06
0x07
0x09
0x0A
Configuration and Calibration
Alarm 0
0x10
0x11
Alarm 1
0x17
0x18
0x1F
0x20
Time-Stamp
SRAM (64 Bytes)
0x5F
0x60
0xFF
2011-2013 Microchip Technology Inc.
MCP7940N
TABLE 5-1:
Address
00h
Bit 7
RTCC MEMORY MAP
Bit 6
ST
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Range
Reset
State
10 Seconds
Seconds
Seconds
00-59
00h
01h
10 Minutes
Minutes
Minutes
00-59
00h
02h
10 Hour
AM/PM
10 Hour
Hours
1-12 + AM/PM
00 - 23
00h
OSCON
VBAT
Day
1-7
01h
12/24
03h
04h
VBATEN
Day
10 Date
05h
LP
06h
07h
Hour
Date
10 Month
Month
10 Year
OUT
SQWE
Year
ALM1
ALM0
EXTOSC RS2
08h
CALIBRATION
09h
RESERVED – DO NOT USE
RS1
RS0
Date
01-31
01h
Month
01-12
01h
Year
00-99
Control Reg.
01h
80h
Calibration
00h
00h
0Ah
10 Seconds
Seconds
Seconds
00-59
00h
0Bh
10 Minutes
Minutes
Minutes
00 - 59
00h
Hours
1-12 + AM/PM
00-23
00h
01h
10 Hour
AM/PM
10 Hours
12/24
ALM0C2
ALM0C1
ALM0C0
0Ch
0Dh
ALM0POL
Hour
ALM0IF
10 Date
0Eh
Day
Date
0Fh
10 Month
10h
Reserved – Do not use
Month
Day
1-7
Date
01-31
01h
Month
01-12
01h
Reserved
01h
11h
10 Seconds
Seconds
Seconds
00-59
00h
12h
10 Minutes
Minutes
Minutes
00-59
00h
Hours
1-12 + AM/PM
00-23
00h
Day
1-7
01h
Date
01-31
01h
Month
01-12
01h
10 Hour
AM/PM
10 Hours
12/24
ALM1C2
ALM1C1
ALM1C0
13h
14h
ALM1POL
16h
10 Month
17h
10 Minutes
19h
10 Hour
AM/PM
12/24
1Ah
10 Hours
10 Date
Day
10 Month
10 Minutes
1Dh
12/24
10 Hour
AM/PM
10 Hours
10 Date
1Eh
1Fh
Day
Date
Month
Reserved – Do not use
18h
1Ch
ALM1IF
10 Date
15h
1Bh
Hour
Day
2011-2013 Microchip Technology Inc.
10 Month
Reserved
01h
Minutes
00h
Hour
00h
Date
00h
Month
00h
Minutes
00h
Hour
00h
Date
00h
Month
00h
DS25010E-page 11
MCP7940N
5.1.1
RTCC REGISTER ADDRESSES
0x00h – Contains the BCD seconds and 10 seconds.
The range is 00 to 59. Bit 7 in this register is used to
start or stop the on-board crystal oscillator. Setting this
bit to a ‘1’ starts the oscillator and clearing this bit to a
‘0’ stops the on-board oscillator.
0x01h – Contains the BCD minutes and 10 minutes.
The range is 00 to 59.
0x02h – Contains the BCD hour in bits 3:0. Bits 5:4
contain either the 10 hour in BCD for 24-hour format or
the AM/PM indicator and the 10-hour bit for 12-hour
format. Bit 5 determines the hour format. Setting this
bit to ‘0’ enables 24-hour format, setting this bit to ‘1’
enables 12-hour format.
0x03h – Contains the BCD day. The range is 1-7.
Additional bits are also used for configuration and
status.
• Bit 3 is the VBATEN bit. If this bit is set, the
internal circuitry is connected to the VBAT pin
when VCC fails. If this bit is ‘0’ then the VBAT pin is
disconnected and the only current drain on the
external battery is the VBAT pin leakage.
• Bit 4 is the VBAT bit. This bit is set by hardware
when the VCC fails and the VBAT is used to power
the Oscillator and the RTCC registers. This bit is
cleared by software. Clearing this bit will also
clear all the time-stamp registers.
• Bit 5 is the OSCON bit. This is set and cleared by
hardware. If this bit is set, the oscillator is running,
if cleared, the oscillator is not running. This bit
does not indicate that the oscillator is running at
the correct frequency. The RTCC will wait 32
oscillator cycles before the bit is set. The RTCC
will wait roughly 32 clock cycles to clear this bit.
0x04h – Contains the BCD date and 10 date. The
range is 01-31. Bits 5:4 contain the 10’s date and bits
4:0 contain the date.
0x05h – Contains the BCD month. Bit 4 contains the
10 month. Bit 5 is the Leap Year bit, which is set during
a leap year and is read-only.
0x06h – Contains the BCD year and 10 year. The
Range is 00-99.
0x07h – Is the Control register.
• Bit 7 is the OUT bit. This sets the logic level on the
MFP when not using this as a square wave output.
• Bit 6 is the SQWE bit. Setting this bit enables the
divided output from the crystal oscillator.
• Bits 5:4 determine which alarms are active.
- 00 – No Alarms are active
- 01 – Alarm 0 is active
- 10 – Alarm 1 is active
- 11 – Both Alarms are active
• Bit 3 is the EXTOSC enable bit. Setting this bit will
allow an external 32.768 kHz signal to drive the
RTCC registers eliminating the need for an
external crystal.
• Bit 2:0 sets the internal divider for the 32.768 kHz
oscillator to be driven to the MFP. The duty cycle is
50%. The output is responsive to the Calibration
register. The following frequencies are available:
- 000 – 1 Hz
- 001 – 4.096 kHz
- 010 – 8.192 kHz
- 011 – 32.768 kHz
- 1xx enables the Cal output function. Cal
output appears on MFP if SQWE is set (64 Hz
Nominal). See Section 5.2.1 “Calibration”
for more details.
Note:
0x08h is the Calibration register. This is an 8-bit
register that is used to add or subtract clocks from the
RTCC counter every minute. The MSB is the sign bit
and indicates if the count should be added or
subtracted. The remaining 7 bits, with each bit adding
or subtracting 2 clocks, give the user the ability to add
or subtract up to 254 clocks per minute.
0x0Ah-0x0fh and 0x11-0x16h are the Alarm 0 and
Alarm 1 registers. The bits are the same as the RTCC
bits with the following differences:
Locations 0x10h and 0x17h are reserved and should
not be used to allow for future device compatibility.
0x0Dh/0x14h has additional bits for alarm configuration.
• ALMxPOL: This bit specifies the level that the
MFP will drive when the alarm is triggered.
ALM2POL is a copy of ALM1POL. The default
state of the MFP when used for alarms is the
inverse of ALM1POL.
• ALMxIF: This is the Alarm Interrupt Fag. This bit is
set in hardware if the alarm was triggered. The bit
is cleared in software.
• ALMxC2:0: These Configuration bits determine
the alarm match. The logic will trigger the alarm
based on one of the following match conditions:
000
DS25010E-page 12
The RTCC counters will continue to
increment during the calibration.
–
Seconds match
2011-2013 Microchip Technology Inc.
MCP7940N
001
–
Minutes match
5.2
010
–
Hours match (takes into account 12/24
hour)
5.2.1
011
–
Matches the current day, interrupt at
12.00.00 a.m. Example: 12 midnight on
100
– Date
101
– RESERVED
110
– RESERVED
111
– Seconds, Minutes, Hour, Day, Date,
Month
• The 12/24-hour bits 0xCh.6 and 0x13h.6 are copies of the bit in 0x02h.6. The bits are read-only.
0x18h-0x1Bh are used for the timesaver function.
These registers are loaded at the time when VCC fails
and the RTCC operates on the VBAT. The VBAT bit is
also set at this time. These registers are cleared when
the VBAT bit is cleared in software.
0x1Ch-0x1Fh are used for the timesaver function.
These registers are loaded at the time when VCC is
restored and the RTCC switches to VDD. These
registers are cleared when the VBAT bit is cleared in
software.
Note:
It is strongly recommended that the
timesaver function only be used when the
oscillator is running. This will ensure
accurate functionality.
FEATURES
CALIBRATION
The MCP7940N utilizes digital calibration to correct for
inaccuracies of the input clock source (either external
or crystal). Calibration is enabled by setting the value
of the Calibration register at address 08H. Calibration
is achieved by adding or subtracting a number of input
clock cycles per minute in order to achieve ppm level
adjustments in the internal timing function of the
MCP7940N.
The MSB of the Calibration register is the sign bit, with
a ‘1’ indicating subtraction and a ‘0’ indicating addition.
The remaining seven bits in the register indicate the
number of input clock cycles (multiplied by two) that
are subtracted or added per minute to the internal
timing function.
The internal timing function can be monitored using
the MFP open-drain output pin by setting bit [6]
(SQWE) and bits [2:0] (RS2, RS1, RS0) of the control
register at address 07H. Note that the MFP output
waveform is disabled when the MCP7940N is running
in VBAT mode. With the SQWE bit set to ‘1’, there are
two methods that can be used to observe the internal
timing function of the MCP7940N:
A. RS2 BIT SET TO ‘0’
With the RS2 bit set to ‘0’, the RS1 and RS0 bits
enable the following internal timing signals to be
output on the MFP pin:
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
1 Hz
4.096 kHz
8.192 kHz
32.768 kHz
The frequencies listed in the table presume an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
32768
8
4
1
With regards to the calibration function, the Calibration
register setting has no impact upon the MFP output
clock signal when bits RS1 and RS0 are set to ‘11’.
The setting of the Calibration register to a non-zero
value (i.e., values other than 00H or 80H) enables the
calibration function which can be observed on the
MFP output pin. The calibration function can be
expressed in terms of the number of input clock cycles
added/subtracted from the internal timing function.
2011-2013 Microchip Technology Inc.
DS25010E-page 13
MCP7940N
With bits RS1 and RS0 set to ‘00’, the calibration
function can be expressed as:
Toutput
=
(32768 +/- (2 * CALREG)) Tinput
=
clock period of MFP output signal
Since the calibration is done once per minute (i.e.,
when the internal minute counter is incremented), only
one cycle in sixty of the MFP output waveform is
affected by the calibration setting. Also note that the
duty cycle of the MFP output waveform will not
necessarily be at 50% when the calibration setting is
applied.
where:
Toutput
Tinput
=
clock period of input signal
CALREG
=
decimal value of Calibration
register setting and the sign is
determined by the MSB of
Calibration register.
FIGURE 5-2:
With bits RS1 and RS0 set to ‘01’ or ‘10’, the
calibration function can not be expressed in terms of
the input clock period. In the case where the MSB of
the Calibration register is set to ‘0’, the waveform
appearing at the MFP output pin will be “delayed”,
once per minute, by twice the number of input clock
cycles defined in the Calibration register. The MFP
waveform will appear as:
RS1 AND RS0 WITH AND WITHOUT CALIBRATION
Delay
In the case where the MSB of the Calibration register
is set to ‘1’, the MFP output waveforms that appear
when bits RS1 and RS0 are set to ‘01’ or ‘10’ are not
as responsive to the setting of the Calibration register.
For example, when outputting the 4.096 kHz
waveform (RS1, RS0 set to ‘01’), the output waveform
is generated using only eight input clock cycles.
Consequently, attempting to subtract more than eight
input clock cycles from this output does not have a
meaningful effect on the resulting waveform. Any
effect on the output will appear as a modification in
both the frequency and duty cycle of the waveform
appearing on the MFP output pin.
B.RS2 BIT SET TO ‘1’
With the RS2 bit set to ‘1’, the following internal timing
signal is output on the MFP pin:
RS2
RS1
RS0
Output Signal
1
x
x
64.0 Hz
Unlike the method previously described, the
calibration setting is continuously applied and affects
every cycle of the output waveform. This results in the
modulation of the frequency of the output waveform
based upon the setting of the Calibration register.
Using this setting, the calibration function can be
expressed as:
Toutput
=
(2 * (256 +/- (2 * CALREG))) Tinput
Toutput
=
clock period of MFP output signal
Tinput
=
clock period of input signal
CALREG
=
decimal value of the Calibration
register setting, and the sign is
determined by the MSB of the
Calibration register.
where:
Since the calibration is done every cycle, the frequency
of the output MFP waveform is constant.
The frequency listed in the table presumes an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
RS2
RS1
RS0
Output Signal
1
x
x
512
DS25010E-page 14
2011-2013 Microchip Technology Inc.
MCP7940N
5.2.2
MFP
Pin 7 is a multi-function pin and supports the following
functions:
• Use of the OUT bit in the Control register for
single bit I/O
• Alarm Outputs – Available in VBAT mode
• FOUT mode – driven from a FOSC divider – Not
available in VBAT mode
The internal control logic for the MFP is connected to
the switched internal supply bus, this allows operation
in VBAT mode. The Alarm Output is the only mode that
operates in VBAT mode, other modes are suspended.
5.2.3
VBAT
The MCP7940N features an internal switch that will
power the clock and the SRAM. In the event that the
VCC supply is not available, the voltage applied to the
VBAT pin serves as the backup supply. A low-value
series resistor is recommended between the external
battery and the VBAT pin to limit the current to the
internal switch circuit.
The VBAT trip point is the point at which the internal
switch operates the device from the VBAT supply and
is typically 1.5V (VTRIP specification D12) typical.
When VDD falls below 1.5V the system will continue to
operate the RTCC and SRAM using the VBAT supply.
The following conditions apply:
TABLE 5-2:
Supply
Condition
Read/Write
Access
Powered
By
VCC < VTRIP, VCC < VBAT
VCC > VTRIP, VCC < VBAT
VCC > VTRIP, VCC > VBAT
No
Yes
Yes
VBAT
VCC
VCC
If the VBAT feature is not being used, the VBAT pin must
be connected to GND. For more information on VBAT
conditions see application note AN1365, “RTCC Best
Practices” (DS01365).
2011-2013 Microchip Technology Inc.
DS25010E-page 15
MCP7940N
5.2.4
CRYSTAL SPECS
The MCP7940N has been designed to operate with a
standard 32.768 kHz tuning fork crystal. The on-board
oscillator has been characterized to operate with a
crystal of maximum ESR of 70K Ohms.
Crystals with a comparable specification are also suitable for use with the MCP7940N.
The table below is given as design guidance and a
starting point for crystal and capacitor selection.
Manufacturer
Part Number
Crystal
Capacitance
CX1 Value
CX2 Value
Micro Crystal
CM7V-T1A
7pF
10pF
12pF
Citizen
CM200S-32.768KDZB-UT
6pF
10pF
8 pF
Please work with your crystal vendor.
EQUATION 5-1:
C load
The following must also be taken into consideration:
CX2 CX1
= ----------------------------- + C stray
CX2 + CX1
• Pin capacitance (to be included in Cx2 and Cx1)
• Stray Board Capacitance
The recommended board layout for the oscillator area
is shown in Figure 5-3. This actual board shows the
crystal and the load capacitors. In this example, C2 is
CX1, C3 is CX2 and the crystal is designated as Y1.
FIGURE 5-3:
BOARD LAYOUT
Gerber files are available from
www/microchip.com/rtcc.
It is required that the final application should be tested
with the chosen crystal and capacitor combinations
across all operating and environmental conditions.
Please also consult with the crystal specification to
observe correct handling and reflow conditions and for
information on ideal capacitor values.
For more information please see application note
AN1365, “RTCC Best Practices” (DS01365).
DS25010E-page 16
2011-2013 Microchip Technology Inc.
MCP7940N
5.2.5
POWER-FAIL TIME-STAMP
The MCP7941X family of RTCC devices feature a
power-fail time-stamp feature. This feature will store
the time at which VCC crosses the VTRIP voltage and is
shown in Figure 5-4. To use this feature, a VBAT
supply must be present and the oscillator must also be
running.
There are two separate sets of registers that are used
to record this information:
FIGURE 5-4:
• The first set, located at 0x18h through 0x1Bh, is
loaded at the time when VCC falls below VTRIP
and the RTCC operates on the VBAT. The VBAT
(register 0x03h bit 4) bit is also set at this time.
• The second set of registers, located at 0x1Ch
through 0x1Fh, is loaded at the time when VCC is
restored and the RTCC switches to VCC.
The power-fail time-stamp registers are cleared when
the VBAT bit is cleared in software.
POWER-FAIL GRAPH
VCC
VTRIP(max)
VTRIP(min)
Power-Down
Time-Stamp
VCCRT
VCCFT
2011-2013 Microchip Technology Inc.
Power-Up
Time-Stamp
DS25010E-page 17
MCP7940N
6.0
ON BOARD MEMORY
The MCP7940N has battery-backed SRAM. The
SRAM is arranged as 64 x 8 bytes and is retained when
the VCC supply is removed, provided the VBAT supply
is present and enabled.
6.1
SRAM
FIGURE 6-1:
SRAM/RTCC BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S11 0 1111 0
S
T
O
P
DATA
x
P
A
C
K
BUS ACTIVITY
FIGURE 6-2:
ADDRESS
BYTE
A
C
K
A
C
K
SRAM/RTCC MULTIPLE BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
S
T
O
P
DATA BYTE N
DATA BYTE 0
x
S110 11110
A
C
K
P
A
C
K
A
C
K
A
C
K
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
Note:
Entering an address past 5F for an SRAM
operation will result in the MCP7940N not
acknowledging the address.
DS25010E-page 18
2011-2013 Microchip Technology Inc.
MCP7940N
6.2
6.2.1
RTCC/SRAM
Pointer of the MCP7940N. After receiving another
Acknowledge signal from the MCP7940N, the master
device transmits the data word to be written into the
addressed memory location. The MCP7940N
acknowledges again and the master generates a Stop
condition. After a Byte Write command, the internal
address counter will point to the address location
following the one that was just written.
SRAM BYTE WRITE
Following the Start condition from the master, the
control code and the R/W bit (which is a logic low) are
clocked onto the bus by the master transmitter. This
indicates to the addressed slave receiver that a byte
with a word address will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
FIGURE 6-3:
Note:
SRAM BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S1 1 01111 0
ADDRESS
BYTE
A
C
K
6.2.2.2
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.2.2.1
Current Address Read
The MCP7940N contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the MCP7940N issues an Acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition and the
MCP7940N discontinues transmission (Figure 6-4).
FIGURE 6-4:
A
C
K
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
MCP7940N as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The MCP7940N will then issue an Acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but it does generate a Stop
condition which causes the MCP7940N to discontinue
transmission (Figure 6-5). After a Random Read
command, the internal address counter will point to the
address location following the one that was just read.
CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 1 1 0 1 1 1 1 1
BUS ACTIVITY
DATA
P
A
C
K
x = don’t care for 1K devices
READ OPERATION
S
T
O
P
x
BUS ACTIVITY
6.2.2
Addressing undefined SRAM locations will
result
in
the
MCP7940N
not
acknowledging the address.
CONTROL
BYTE
S
T
O
P
DATA
BYTE
P
A
C
K
2011-2013 Microchip Technology Inc.
N
O
A
C
K
DS25010E-page 19
MCP7940N
6.2.2.3
Sequential Read
generate an Acknowledge but will generate a Stop
condition. To provide sequential reads, the MCP7940N
contains an internal Address Pointer which is
incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The internal Address Pointer will automatically roll over to the start of the Block.
Sequential reads are initiated in the same way as a
random read except that after the MCP7940N
transmits the first data byte, the master issues an
Acknowledge as opposed to the Stop condition used in
a random read. This Acknowledge directs the
MCP7940N to transmit the next sequentially
addressed 8-bit word (Figure 6-6). Following the final
byte transmitted to the master, the master will NOT
FIGURE 6-5:
RANDOM READ
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S1 1 0 1 1 1 1 0
BUS ACTIVITY
MASTER
CONTROL
BYTE
S1 0 1 0
A
C
K
BUS ACTIVITY
FIGURE 6-6:
S
T
A
R
T
ADDRESS
BYTE
P
1
A
C
K
N
O
A
C
K
A
C
K
SEQUENTIAL READ
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DS25010E-page 20
S
T
O
P
DATA n + X
P
SDA LINE
BUS ACTIVITY
S
T
O
P
DATA
BYTE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
2011-2013 Microchip Technology Inc.
MCP7940N
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead SOIC (3.90 mm)
Example:
XXXXXT
XXYYWW
NNN
7940NI
SN e3 1133
13F
Example:
8-Lead TSSOP
XXXX
940N
TYWW
I133
NNN
13F
Example:
8-Lead MSOP
XXXXX
7940NI
YWWNNN
13313F
8-Lead 2x3 TDFN
Example:
XXX
YWW
NN
AAV
133
13
Part Number
MCP7940N
Note:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
1st Line Marking Codes
TSSOP
MSOP
TDFN
940N
7940NT
AAV
T = Temperature grade
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2013 Microchip Technology Inc.
DS25010E-page 21
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25010E-page 22
2011-2013 Microchip Technology Inc.
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS25010E-page 23
MCP7940N
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MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25010E-page 26
2011-2013 Microchip Technology Inc.
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS25010E-page 27
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25010E-page 28
2011-2013 Microchip Technology Inc.
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS25010E-page 29
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25010E-page 30
2011-2013 Microchip Technology Inc.
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc.
DS25010E-page 31
MCP7940N
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DS25010E-page 33
MCP7940N
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25010E-page 34
2011-2013 Microchip Technology Inc.
MCP7940N
APPENDIX A:
REVISION HISTORY
Revision A (04/2011)
Original release of this document.
Revision B (09/2011)
• Added Figure 1-2
• Added Parameter D15 to Table 1-1
• Added Section 3.3 “X1, X2”, Section 3.4
“MFP”, Section 3.5 “VBAT”
• Added Figure 5-1
• Updated Section 5.2.3 “VBAT”, Section 5.2.4
“Crystal Specs”, Section 5.2.5 “Power-fail
Time-stamp”.
Revision C (12/2011)
Added DC/AC Char. Charts.
Revision D (11/2012)
Added Extended Temp.
Revision E (01/2013)
Revised Table 1-2: AC Characteristics; temperature
range.
2011-2013 Microchip Technology Inc.
DS25010E-page 35
MCP7940N
NOTES:
DS25010E-page 36
2011-2013 Microchip Technology Inc.
MCP7940N
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
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resources, user’s guides and hardware support
documents, latest software releases and archived
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Questions (FAQ), technical support requests,
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representatives
•
•
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•
•
Distributor or Representative
Local Sales Office
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Technical Support
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Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011-2013 Microchip Technology Inc.
DS25010E-page 37
MCP7940N
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: MCP7940N
Literature Number: DS25010E
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS25010E-page 38
2011-2013 Microchip Technology Inc.
MCP7940N
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
PART NO.
Device
Device:
X
/XX
Temperature Package
Range
MCP7940N =
MCP7940NT=
1.8V - 5.5V I2C™ Serial RTCC
1.8V - 5.5V I2C™ Serial RTCC
(Tape and Reel)
Temperature
Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C (SN, MS package only)
Package:
SN
ST
=
=
8-Lead Plastic Small Outline (3.90 mm body)
8-Lead Plastic Thin Shrink Small Outline
(4.4 mm)
8-Lead Plastic Micro Small Outline
8-Lead Plastic Dual Flat, No Lead
MS
=
MNY(1) =
Examples:
a)
MCP7940N-I/SN: Industrial
ture, SOIC package.
Tempera-
b)
MCP7940NT-I/SN: Industrial Temperature, SOIC package, Tape and Reel.
c)
MCP7940NT-I/MNY: Industrial Temperature, TDFN package.
d)
MCP7940N-I/MS: Industrial Temperature
MSOP package.
e)
MCP7940N-I/ST: Industrial Temperature,
TSSOP package.
f)
MCP7940NT-I/ST: Industrial Temperature,
TSSOP package, Tape and Reel.
g)
MCP7940N-E/SN: Extended Temperature,
SOIC package.
Note 1: ’Y’ indicates a Nickel Palladium Gold (NiPdAu) finish.
2011-2013 Microchip Technology Inc.
DS25010E-page 39
MCP7940N
NOTES:
DS25010E-page 40
2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769546
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2011-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS25010E-page 41
Worldwide Sales and Service
AMERICAS
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Tel: 65-6334-8870
Fax: 65-6334-8850
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DS25010E-page 42
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11/29/12
2011-2013 Microchip Technology Inc.