AD AD9858 1 gsps direct digital synthesizer Datasheet

1 GSPS Direct Digital Synthesizer
AD9858
FEATURES
GENERAL DESCRIPTION
1 GSPS internal clock speed
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit DAC
Excellent phase noise and SFDR
32-bit programmable frequency register
Simplified 8-bit parallel and SPI serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation: 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit digital-to-analog converter (DAC) operating up to 1 GSPS.
The AD9858 uses advanced DDS technology coupled with an
internal high speed, high performance DAC to form a digitally
programmable, complete high frequency synthesizer capable of
generating a frequency-agile analog output sine wave at up to
400 MHz. The AD9858 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9858 via parallel (8-bit) or serial loading formats. The
AD9858 contains an integrated charge pump (CP) and phase
frequency detector (PFD) for synthesis applications requiring
the combination of a high speed DDS along with phase-locked
loop (PLL) functions. An analog mixer is also provided on chip
for applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops and tuners. The AD9858
also features a divide-by-2 on the clock input, allowing the external
reference clock to be as high as 2 GHz.
APPLICATIONS
VHF/UHF LO synthesis
Tuners
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizers
Radars
SONET/SDH clock synthesis
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
LO LO
DIV
DIV
÷M
PD
÷N
CP
CHARGE
PUMP
IF IF
PHASE
DETECTOR
AD9858
ANALOG
MULTIPLIER
DIGITAL PLL
CPISET
PHASE ACCUMULATOR
FREQUENCY ACCUMULATOR
32
DACISET
15
PHASE
ACCUMULATOR
RESET
15
PHASE-TOAMPLITUDE
CONVERSION
10
DAC
POWERDOWN
LOGIC
FUD
÷8
M
U
X
÷2
SYNCLK
REFCLK
REFCLK
03166-001
PS0 PS1
SYNC
CONTROL REGISTERS
IOUT
SYSCLK
TIMING AND CONTROL LOGIC
RESET
IOUT
14
PHASE
OFFSET
ADJUST
FREQUENCY
TUNING
WORD
FREQUENCY
ACCUMULATOR
RESET
DELTA
FREQUENCY
RAMP RATE
DELTA
FREQUENCY
WORD
32
32
RF RF
I/O PORT
(SER/PAR)
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
AD9858
TABLE OF CONTENTS
Features .............................................................................................. 1
Component Blocks ..................................................................... 14
Applications ....................................................................................... 1
Modes of Operation ................................................................... 16
General Description ......................................................................... 1
Synchronization .......................................................................... 18
Functional Block Diagram .............................................................. 1
Programming the AD9858........................................................ 19
Revision History ............................................................................... 2
Register Map ................................................................................... 22
Electrical Specifications ................................................................... 3
Register Bit Descriptions ........................................................... 23
Absolute Maximum Ratings............................................................ 6
Other Registers ........................................................................... 25
Thermal Performance .................................................................. 6
User Profile Registers ................................................................. 25
Explanation of Test Levels ........................................................... 6
Applications Information .............................................................. 27
ESD Caution .................................................................................. 6
Evaluation Boards ...................................................................... 28
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 29
Typical Performance Characteristics ............................................. 9
Warning ....................................................................................... 29
Theory of Operation ...................................................................... 14
Ordering Guide .......................................................................... 29
REVISION HISTORY
2/09—Rev. B to Rev. C
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 6
Added Thermal Performance Section ........................................... 6
Changes to Figure 3, Figure 4, and Figure 5.................................. 9
Changes to Figure 9, Figure 10 Caption, Figure 11 Caption,
Figure 13, and Figure 14 ................................................................ 10
Changes to Figure 17 ...................................................................... 11
Changes to Theory of Operation Section and DAC Output
Section .............................................................................................. 14
Changes to Charge Pump Section ................................................ 15
Changes to Modes of Operation Section ..................................... 16
Changes to Single-Tone Mode Section and Frequency Sweeping
Mode Section................................................................................... 17
Changes to SYNCLK and FUD Pins Section and Figure 33 ..... 18
Changes to I/O Port Functionality Section, Parallel
Programming Mode Section, and Figure 35 ............................... 20
Changes to Figure 36 and Serial Programming
Mode Section................................................................................... 21
Changes to Table 6 .......................................................................... 22
Changes to Control Function Register (CFR) Section .............. 23
Changes to CFR[21]: Load Delta Frequency Timer Section .... 24
Changed CFR[14]: Sine/Cosine Select Bit Section to CFR[14]:
Enable Sine Output Bit Section..................................................... 24
Changes to Delta Frequency Tuning Word (DFTW) Section,
Delta Frequency Ramp Rate Word (DFRRW) Section, and
Phase Offset Control Section ........................................................ 25
Changes to Profile Selection Section ........................................... 26
Deleted Frequency Tuning Control Section ............................... 27
Changed AD9858 Application Suggestions Section to
Applications Information Section ................................................ 27
Changes to Table 13 ....................................................................... 28
Added Exposed Paddle Notation to Outline Dimensions ........ 29
4/07—Rev. A to Rev. B
Changed EPAD to TQFP_EP............................................ Universal
Updated Outline Dimensions ....................................................... 31
11/03—Rev. 0 to Rev. A
Changes to Specifications .................................................................5
Moved ESD Caution to .....................................................................6
Moved Pin Configuration to ............................................................7
Moved Pin Function Description to ...............................................8
Changes to Equations .................................................................... 19
Changes to Delta Frequency Ramp Rate Word (DFRRW) ....... 27
4/03—Revision 0: Initial Version
Rev. C | Page 2 of 32
AD9858
ELECTRICAL SPECIFICATIONS
Unless otherwise noted, VDD = 3.3 V ± 5%, CPVDD = 5 V ± 5%, RSET = 2 kΩ, CPISET = 2.4 kΩ, reference clock frequency = 1 GHz.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS 1
Reference Clock Frequency Range (Divider Off )
Reference Clock Frequency Range (Divider On)
Duty Cycle at 1 GHz
Input Capacitance
Input Impedance
Input Sensitivity
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
26 MHz fOUT
65 MHz fOUT
126 MHz fOUT
375 MHz fOUT
180 MHz fOUT (700 MHz REFCLK)
Narrow-Band SFDR 2
40 MHz fOUT (±15 MHz)
40 MHz fOUT (±1 MHz)
40 MHz fOUT (±50 kHz)
100 MHz fOUT (±15 MHz)
100 MHz fOUT (±1 MHz)
100 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz)
180 MHz fOUT (±1 MHz)
180 MHz fOUT (±50 kHz)
360 MHz fOUT (±15 MHz)
360 MHz fOUT (±1 MHz)
360 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz, 700 MHz REFCLK)
180 MHz fOUT (±1 MHz, 700 MHz REFCLK)
180 MHz fOUT (±50 kHz, (700 MHz REFCLK)
OUTPUT PHASE NOISE CHARACTERISTICS (AT 103 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
OUTPUT PHASE NOISE CHARACTERISTICS (AT 403 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
Temp
Test Level
Min
Full
Full
25°C
25°C
25°C
Full
VI
VI
V
V
IV
VI
10
20
42
Full
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
Full
Full
Full
Full
Full
V
V
V
V
IV
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Typ
50
3
1500
–20
5
–10
Max
Unit
1000
2000
58
MHz
MHz
%
pF
Ω
dBm
+5
10
20
0.5
1
100
AVDD – 1.5
40
+10
15
1
1.5
AVDD + 0.5
Bits
mA
% FS
μA
LSB
LSB
kΩ
V
70
66
62
58
dBc
dBc
dBc
dBc
dBc
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
82
87
88
81
82
86
74
84
85
75
85
86
65
80
84
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Full
Full
Full
V
V
V
–147
–150
–152
dBc/Hz
dBc/Hz
dBc/Hz
Full
Full
Full
V
V
V
–133
–137
–140
dBc/Hz
dBc/Hz
dBc/Hz
Rev. C | Page 3 of 32
52
AD9858
Parameter
OUTPUT PHASE NOISE CHARACTERISTICS
(AT 100 MHz IOUT With 700 MHz REFCLK)
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency
Phase Detector Frequency (Divide-by-4 Enabled) 3
Charge Pump Sink and Source Current 4
Fast Lock Current (Acquisition Only)
Open-Loop Current (Acquisition Only)
Sink and Source Current Absolute Accuracy 5
Sink and Source Current Matching5
Input Sensitivity PDIN and DIVIN (50 Ω) 6
Input Impedance PDIN and DIVIN (Single-Ended)
Phase Noise @ 100 MHz Input Frequency
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
Charge Pump Output Range 7
MIXER
IFOUT 8
fRF
fLO
Conversion Gain
LO Level
RF Level
Input IP3
1 dB Input Compression Power 9
Input Impedance (Single-Ended)
LO
RF
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic 1 Voltage
Logic 0 Voltage
POWER DISSIPATION
PDISS (Worst-Case Conditions—Everything on
PFD Input Frequency 150 MHz)
PDISS (DAC and DDS Core Only Worst-Case)
PDISS (Power-Down Mode)
PDISS Mixer Only
PDISS PFD and CP (at 100 MHz) Only
Temp
Test Level
Min
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
–125
–140
–148
–150
–150
–150
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
V
V
IV
V
Full
Full
Full
Full
V
V
V
V
110
140
148
Full
Full
Full
Full
Full
Full
Full
Full
V
VI
VI
VI
VI
VI
VI
VI
400
Full
Full
V
V
Full
Full
Full
Full
Full
VI
VI
VI
VI
V
2.0
Full
Full
VI
VI
2.8
Full
VI
Full
Full
Full
Full
VI
VI
VI
VI
Rev. C | Page 4 of 32
Typ
Max
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
150
400
4
7
30
2.5
1
–15
0
1
CPVDD
2
2
0.0
–10
–20
5
–3
Unit
3.5
+5
9
1
1
MHz
MHz
mA
mA
mA
%
%
dBm
kΩ
dBc/Hz
dBc/Hz
dBc/Hz
V
MHz
GHz
GHz
dB
dBm
dBm
dBm
dBm
kΩ
kΩ
0.8
12
12
3
V
V
μA
μA
pF
0.4
V
V
2
2.5
W
1.7
65
60
350
2
100
75
435
W
mW
mW
mW
AD9858
Parameter
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low (tPWL)
Minimum Clock Pulse Width High (tPWH)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
Parallel Control Bus 10
WR Minimum Low Time (tWRLOW)
WR Minimum High Time (tWRHIGH)
WR Minimum Period (tWR)
Address to WR Setup (tASU)
Address to WR Hold (tAHU)
Data to WR Setup (tDSU)
Data to WR Hold (tDHU)
Miscellaneous Timing Specifications
REFCLK to SYNCLK
FUD/PS[1:0] to SYNCLK Setup Time 11
FUD/PS[1:0] to SYNCLK Hold Time11
REFCLK to SYNCLK Delay
DATA LATENCY (PIPELINE DELAY)
FTW/POW to DAC Output
DFTW to DAC Output
Temp
Test Level
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
3
6
9
3
0
3.5
0
Full
Full
Full
Full
V
IV
IV
IV
4
0
25°C
IV
83
83
25°C
IV
99
99
1
REFCLK input is internally dc biased. AC coupling should be used.
Reference clock frequency is selected to ensure that the second harmonic is out of the bandwidth of interest.
PD inputs set at 400 MHz with divide-by-4 enabled.
4
The charge pump current is programmable in eight discrete steps; minimum value assumes current sharing.
5
For 0.75 V < VCP < CPVDD − 0.75 V.
6
These differential inputs are internally dc biased. AC coupling should be used.
7
The charge pump supply voltage can range from 4.75 V to 5.25 V.
8
DAC output is differential open collector.
9
For 1 dB output compression; input power measured at 50 Ω.
10
See Figure 35 and Figure 36 for timing diagrams.
11
See Figure 34 for timing diagram.
12
SYSCLK = REFCLK/x, where x is 1 or 2, as set using CFR[6].
2
3
Rev. C | Page 5 of 32
Min
Typ
Max
Unit
10
MHz
ns
ns
ns
ns
ns
ns
5.5
15
1
7
0
20
ns
ns
ns
ns
ns
ns
ns
2.5
2.5
3
ns
ns
ns
ns
SYSCLK
cycles 12
SYSCLK
cycles12
AD9858
ABSOLUTE MAXIMUM RATINGS
The AD9858 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source may be used.
Table 2.
Parameter
Maximum Junction Temperature
AVDD
DVDD
CPVDD
Digital Input Voltage Range
Digital Output Current
Storage Temperature Range
Operating Temperature Range
Rating
150°C
4V
4V
6V
−0.7 V to +VDD
5 mA
−65°C to +150°C
−40°C to +85°C
To determine the junction temperature on the application
printed circuit board (PCB),
TJ = TCASE + (ΨJT × PD)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
the top center of package.
ΨJT is found in Table 3.
PD is the power dissipation (see the total power dissipation in
Table 1).
Values of θJA are provided for package comparison and
PCB design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
THERMAL PERFORMANCE
where TA is the ambient temperature (°C).
Table 3.
Values of θJB are provided for package comparison and PCB
design considerations (see Table 3).
Symbol
θJA
θJMA
θJMA
θJB
θJC
ΨJT
Description (Using a 2S2P Test Board)
Junction-to-ambient thermal resistance,
0.0 m/sec airflow per JEDEC JESD51-2
(still air)
Junction-to-ambient thermal resistance,
1.0 m/sec airflow per JEDEC JESD51-6
(moving air)
Junction-to-ambient thermal resistance,
2.0 m/sec airflow per JEDEC JESD51-6
(moving air)
Junction-to-board thermal resistance,
1.0 m/sec airflow per JEDEC JESD51-8
(moving air)
Junction-to-case thermal resistance
(die to heat sink) per MIL-STD-883,
Method 1012.1
Junction-to-top-of-package
characterization parameter, 0 m/sec
airflow per JEDEC JESD51-2 (still air)
Value (°C/W)
19.8
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required
(see Table 3).
15.6
EXPLANATION OF TEST LEVELS
14.6
8.2
I.
100% production tested.
III.
Sample tested only.
IV.
Parameter is guaranteed by design and characterization
testing.
V.
Parameter is a typical value only.
VI.
Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for industrial
operating temperature range.
0.6
0.15
ESD CAUTION
Rev. C | Page 6 of 32
AD9858
FUD
PS1
PS0
DGND
DGND
DVDD
DVDD
RESET
SPSELECT
AVDD
AVDD
AGND
AGND
AVDD
AGND
IOUT
IOUT
IOUT
IOUT
AGND
DACISET
DACBP
AVDD
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D7
1
75
NC
D6
2
74
AGND
D5
3
73
AVDD
D4
4
72
DIV
DGND
5
71
DIV
DGND
6
70
AVDD
DVDD
7
69
AGND
DVDD
8
68
CPGND
D3
9
67
CPVDD
D2 10
66
CP
D1 11
65
CP
64
CPFL
63
CPGND
62
CPVDD
AD9858
D0 12
TOP VIEW
(Not to Scale)
ADDR5 13
ADDR4 14
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AGND
AVDD
AGND
51
AVDD
AGND
13
DVDD 25
LO
52
AVDD
RF
DVDD 24
LO
53
AVDD
RF
DVDD 23
AVDD
54
AGND
IF
RD/CS 22
AGND
55
AVDD
21
AGND
IF
DGND
AGND
56
AVDD
20
AGND
PFD
DVDD
AVDD
57
REFCLK
PFD
WR/SCLK 19
REFCLK
58
AVDD
NC
ADDR0/SDIO 18
AVDD
59
AGND
17
AGND
NC
ADDR1/SDO
DGND
CPISET
DVDD
61
60
ADDR3
DVDD
15
ADDR2/IORESET 16
NOTES
1. NC = NO CONNECT.
2. THE TQFP_EP (THERMAL SLUG) MUST BE ATTACHED TO THE GROUND PLANE OR SOME OTHER LARGE
METAL MASS FOR THERMAL TRANSFER. FAILURE TO DO SO MAY CAUSE EXCESSIVE DIE TEMPERATURE
RISE AND DAMAGE TO THE DEVICE.
03166-044
SYNCLK
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1 to 4, 9 to 12
Mnemonic
D7 to D0
5, 6, 21, 28, 95, 96
7, 8, 20, 23 to 27,
93, 94
13 to 18
DGND
DVDD
16
ADDR5 to
ADDR0
IORESET
I/O
I
Description
Parallel Port Data. The functionality of these pins is valid only when the I/O port is configured as
a parallel port.
Digitial Ground.
Digital Supply Voltage.
I
When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select for
accessing the on-chip registers (see the IORESET, SDO, and SDIO pins for the serial port mode).
This is valid for serial programming mode only. Active high input signal that resets the serial I/O
bus controller. It serves as a means of recovering from an unresponsive serial bus caused by
an improper programming protocol. Asserting an I/O reset does not affect the contents of
previously programmed registers, nor does it invoke their default values.
I
Rev. C | Page 7 of 32
AD9858
Pin No.
17
Mnemonic
SDO
I/O
O
18
SDIO
I/O
19
WR/SCLK
I
22
RD/CS
I
29, 30, 37 to 39,
41, 42, 49, 50, 52,
69, 74, 80, 85, 87, 88
31, 32, 35, 36,
40, 43, 44, 47,
48, 51, 70, 73,
77, 86, 89, 90
33
AGND
I
Description
This is valid for serial programming mode only. When operating the I/O port as a 3-wire
serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire
serial port, this pin is unused.
This is valid for serial programming mode only. When operating the I/O port as a 3-wire serial
port, this pin is the serial data input. When operated as a 2-wire serial port, this pin is the
bidirectional serial data pin.
When the I/O port is configured for parallel programming mode, this pin functions as an active
low write pulse (WR). When configured for serial programming mode, this pin functions as the
serial data clock (SCLK).
When the I/O port is configured for parallel programming mode, this pin functions as an active
low read pulse (RD). When configured for serial programming mode, this pin functions as an
active low chip select (CS) that allows multiple devices to share the serial bus.
Analog Ground.
AVDD
I
Analog Supply Voltage.
REFCLK
I
34
45
REFCLK
LO
I
I
46
53
LO
RF
I
I
54
55
56
57
RF
IF
IF
PFD
I
O
O
I
58
59, 60, 75, 76
61
PFD
NC
CPISET
I
62, 67
63, 68
64
65, 66
71
72
CPVDD
CPGND
CPFL
CP
DIV
DIV
I
I
O
O
I
I
78
79
81, 82
83, 84
91
DACBP
DACISET
IOUT
IOUT
SPSELECT
I
O
O
I
92
RESET
I
97, 98
99
PS0, PS1
FUD
I
I
100
SYNCLK
EPAD
O
Reference Clock Complementary Input. When the REFCLK port operates in single-ended mode,
REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.
Reference Clock Input.
Mixer Local Oscillator (LO) Complementary Input. When the LO port operates in single-ended
mode, LO should be decoupled to AVDD with a 0.1 μF capacitor.
Mixer Local Oscillator (LO) Input.
Analog Mixer RF Complementary Input. When the RF port operates in single-ended mode,
RF should be decoupled to AVDD with a 0.1 μF capacitor.
Analog Mixer RF Input.
Analog Mixer IF Output.
Analog Mixer IF Complementary Output.
Phase Frequency Detector Complementary Input. When the PFD port operates in single-ended
mode, PFD should be decoupled to AVDD with a 0.1 μF capacitor.
Phase Frequency Detector Input.
No Connection.
Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes
the reference current for the charge pump.
Charge Pump Supply Voltage.
Charge Pump Ground.
Charge Pump Fast Lock Output.
Charge Pump Output.
Phase Frequency Detector Feedback Input.
Phase Frequency Detector Feedback Complementary Input. When the DIV port operates in
single-ended mode, DIV should be decoupled to AVDD with a 0.1 μF capacitor.
DAC Baseline Decoupling Pin. Typically bypassed to Pin 77 with a 0.1 μF capacitor.
A resistor connected from DACISET to AGND establishes the reference current for the DAC.
DAC Output.
DAC Complementary Output.
I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0 is serial programming mode, and
Logic 1 is parallel programming mode.
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default
operating conditions.
Used to select one of the four internal profiles. These pins are synchronous to the SYNCLK output.
Frequency Update. The rising edge transfers the contents of the internal buffer registers to the
memory registers. This pin is synchronous to the SYNCLK output.
Clock Output Pin. Serves as a synchronizer for external hardware. SYNCLK runs at REFCLK/8.
Exposed paddle must be soldered to ground.
I
Rev. C | Page 8 of 32
AD9858
TYPICAL PERFORMANCE CHARACTERISTICS
0
MARKER 1 [T1]
–0.59dBm
26.0MHz
REF LVL
5dBm
1
RBW
VBW
SWT
5kHz
5kHz
64s
RF ATT
UNIT
20dB
REF LVL
5dBm
dB
MARKER 1 [T1]
1.73dBm
26.10050100MHz
0
1
RBW
VBW
SWT
200Hz RF ATT
200Hz
64s
UNIT
20dB
dB
A
A
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
START: 0Hz
50MHz/
03166-103
–100
1AP
03166-A-006
–10
STOP: 500MHz
–100
0
MARKER 1 [T1]
–0.57dBm
65.0MHz
1
RBW
VBW
SWT
5kHz
5kHz
50s
RF ATT
UNIT
50kHz/
SPAN 500kHz
Figure 6. Narrow-Band SFDR, 26 MHz fOUT, 1 MHz BW
Figure 3. Wideband SFDR, 26 MHz fOUT
REF LVL
0dBm
CENTER 26.1MHz
20dB
REF LVL
5dBm
dB
MARKER 1 [T1]
1.58dBm
65.10200401MHz
RBW
VBW
SWT
500Hz RF ATT
500Hz
40s
UNIT
20dB
dB
1
0
A
A
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
START: 0Hz
50MHz/
03166-104
–100
1AP
03166-A-007
–10
STOP: 500MHz
–100
Figure 4. Wideband SFDR, 65 MHz fOUT
MARKER 1 [T1]
–0.73dBm
126.0MHz
1
REF LVL
0dBm
0
RBW
VBW
SWT
5kHz
5kHz
50s
RF ATT
UNIT
CENTER 65.1MHz
200kHz/
SPAN 2MHz
Figure 7. Narrow-Band SFDR, 65 MHz fOUT, 1 MHz BW
20dB
REF LVL
5dBm
dB
MARKER 1 [T1]
1.27dBm
126.10200401MHz
0
1
RBW
VBW
SWT
500Hz RF ATT
500Hz
40s
UNIT
20dB
dB
A
A
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
START: 0Hz
50MHz/
STOP: 500MHz
03166-105
–100
1AP
03166-A-008
–10
–100
Figure 5. Wideband SFDR, 126 MHz fOUT
CENTER 126.1MHz
200kHz/
SPAN 2MHz
Figure 8. Narrow-Band SFDR, 126 MHz fOUT, 1 MHz BW
Rev. C | Page 9 of 32
AD9858
RBW
VBW
SWT
0
5kHz
5kHz
50s
RF ATT
1
UNIT
20dB
REF LVL
5dBm
dB
MARKER 1 [T1]
–1.35dBm
375.10501002MHz
0
RBW
VBW
SWT
500Hz RF ATT
500Hz
100s UNIT
20dB
dB
1
A
A
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
50MHz/
STOP: 500MHz
–100
RBW
VBW
SWT
300Hz RF ATT
300Hz
56s
UNIT
500kHz/
SPAN 5MHz
Figure 12. Narrow-Band SFDR, 375 MHz fOUT, 1 MHz BW
Figure 9. Wideband SFDR, 375 MHz fOUT
REF LVL
5dBm
CENTER 375.1MHz
20dB
REF LVL
0dBm
dB
0
0
MARKER 1 [T1]
–0.94dBm
216.0MHz
1
RBW
VBW
SWT
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
A
–10
–10
–20
–20
–30
–30
1AP
–40
–50
–50
–60
–60
–70
–70
–80
–80
03166-A-010
–40
–90
–100
CENTER 216.1MHz
100kHz/
SPAN 1MHz
–90
–100
Figure 10. Narrow-Band SFDR, 216 MHz fOUT,
1 MHz BW, 1 GHz Clock, Divider Off
REF LVL
5dBm
RBW
VBW
SWT
300Hz RF ATT
300Hz
56s
UNIT
START: 0Hz
50MHz/
STOP: 500MHz
Figure 13. Wideband SFDR, 216 MHz fOUT, 1 GHz Clock, Divider Off
20dB
REF LVL
0dBm
dB
0
0
MARKER 1 [T1]
–0.97dBm
216.0MHz
1
RBW
VBW
SWT
5kHz
5kHz
50s
RF ATT
UNIT
20dB
dB
A
A
–10
–10
–20
–20
–30
–30
1AP
–40
–50
–50
–60
–60
–70
–70
–80
–80
03166-A-012
–40
–90
–100
CENTER 216.1MHz
100kHz/
03166-113
START: 0Hz
03166-109
–100
1AP
03166-A-009
–10
SPAN 1MHz
–90
–100
Figure 11. Narrow-Band SFDR, 216 MHz fOUT,
1 MHz BW, 2 GHz Clock, Divider On
START: 0Hz
50MHz/
STOP: 500MHz
Figure 14. Wideband SFDR, 216 MHz fOUT, 2 GHz Clock, Divider On
Rev. C | Page 10 of 32
03166-114
MARKER 1 [T1]
–1.60dBm
375.0MHz
REF LVL
0dBm
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
PHASE NOISE, L(f) (dBc/Hz)
–100
–110
–120
–130
–140
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
03166-016
–150
–160
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
Figure 16. Fractional Divider Loop Residual Phase Noise,
fIN = 115 MHz, fOUT = 1550 MHz, Loop BW = 50 kHz
DELTA 1 [T1]
REF LVL
0dBm
0.0dB
0.00000000Hz
RBW
VBW
SWT
1kHz
1kHz
3.8s
RF ATT
UNIT
100
1k
10
10dB
REF LVL
0dBm
dBm
0
100
1k
–20
–20
–50
–50
–60
–60
–70
–70
–80
–80
150kHz/
10M
100M
RBW
VBW
SWT
2kHz
2kHz
940s
RF ATT
UNIT
10dB
dBm
1AP
1
03166-A-021
–40
CENTER 1.55GHz
1M
–30
1AP
–40
–100
10M
A
–10
1
1M
1
A
–10
–90
10k
100k
FREQUENCY (Hz)
DELTA 1 [T1]
–56.76dB
423.84769539kHz
0
–30
10k
100k
FREQUENCY (Hz)
Figure 19. Translation Loop Residual Phase Nois,e
fLO = 1500 MHz, fOUT = 1550 MHz, Loop BW = 50 kHz
03166-018
PHASE NOISE, L(f) (dBc/Hz)
–50
–60
–70
–80
–90
100
10
Figure 18. Residual Phase Noise, 403 MHz fOUT, 1 GHz REFCLK
0
–10
–20
–30
–40
10
–120
–130
–140
–150
–160
–170
Figure 15. Residual Phase Noise, 103 MHz fOUT, 1 GHz REFCLK
–170
–50
–60
–70
–80
–90
–100
–110
–90
–100
SPAN 1.5MHz
CENTER 1.55GHz
150kHz/
SPAN 1.5MHz
Figure 20. Fractional Divider Loop SFDR, fIN = 97.3 MHz,
fOUT = 1550 MHz, BW = 1.5 MHz
Figure 17. Fractional Divider Loop SFDR, fIN = 96.9 MHz,
fOUT = 1550 MHz, BW = 1.5 MHz
Rev. C | Page 11 of 32
03166-019
–150
–160
–170
0
–10
–20
–30
–40
03166-015
PHASE NOISE, L(f) (dBc/Hz)
0
–10
–20
–30
–40
03166-014
PHASE NOISE, L(f) (dBc/Hz)
AD9858
AD9858
RBW
VBW
SWT
0.0dB
0.00000000Hz
5kHz
5kHz
15s
RF ATT
10dB
UNIT
REF LVL
0dBm
dBm
0
0
∗
A
–10
–10
–20
–20
–30
–50
–50
–60
–60
–70
–70
–80
–80
03166-017
–40
–90
CENTER 1.55GHz
15MHz/
DELTA 1 [T1]
–81.10dB
57.11422845kHz
0
1
RBW
VBW
SWT
SPAN 150MHz
1kHz
500kHz
7.6s
RF ATT
RF ATT
10dB
UNIT
dBm
1
A
1AP
1
CENTER 1.55GHz
15MHz/
SPAN 150MHz
Figure 24. Fractional Divider Loop SFDR, fIN = 97.3 MHz,
fOUT = 1550 MHz, BW = 150 MHz
10dB
UNIT
5kHz
5kHz
15s
–90
–100
Figure 21. Fractional Divider Loop SFDR, fIN = 96.9 MHz,
fOUT = 1550 MHz, BW = 150 MHz
REF LVL
0dBm
RBW
VBW
SWT
–30
1AP
–40
–100
DELTA 1 [T1]
–64.55dB
–1.20240481MHz
03166-A-020
DELTA 1 [T1]
REF LVL
0dBm
REF LVL
0dBm
dBm
DELTA 1 [T1]
–60.67dB
–57.11422846kHz
RBW
VBW
SWT
1kHz RF ATT
500Hz
7.6s
UNIT
10dB
dBm
1
0
A
A
–10
–10
–20
–20
–30
1AP
–40
–50
–50
–60
–60
–70
–70
–80
–80
03166-A-022
–40
–90
CENTER 1.55GHz
150kHz/
–90
–100
SPAN 1.5MHz
Figure 22. Translation Loop SFDR, fLO = 1459 MHz,
fOUT = 1550 MHz, BW = 1.5 MHz
REF LVL
0dBm
DELTA 1 [T1]
–96.36dB
–42.98597194MHz
RBW
VBW
SWT
10kHz RF ATT
500Hz
75s
UNIT
10dB
REF LVL
0dBm
dBm
–20
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
03166-A-023
–40
1
15MHz/
DELTA 1 [T1]
–64.55dB
–1.20240481MHz
RBW
VBW
SWT
5kHz
5kHz
15s
RF ATT
10dB
UNIT
dBm
1
–30
1AP
CENTER 1.55GHz
SPAN 1.5MHz
A
–10
–90
150kHz/
0
∗
A
–10
–100
CENTER 1.55GHz
Figure 25. Translation Loop SFDR, fLO = 1410 MHz,
fOUT = 1550 MHz, BW = 1.5 MHz
1
0
1
1AP
1
03166-A-046
–100
1AP
03166-A-045
–30
–90
–100
SPAN 150MHz
Figure 23. Translation Loop SFDR, fLO = 1459 MHz,
fOUT = 1550 MHz, BW = 150 MHz
CENTER 1.55GHz
15MHz/
SPAN 150MHz
Figure 26. Translation Loop SFDR, fLO = 1410 MHz,
fOUT = 1550 MHz, BW = 150 MHz
Rev. C | Page 12 of 32
AD9858
600
2.0
3.3V
1.8
SUPPLY CURRENT (mA)
1.4
1.2
1.0
0.8
0.6
0.4
0
225
450
675
REFCLK (MHz)
900
300
200
100
03166-A-025
0.2
3.1V
400
0
1125
0
70
140
210
280
350
fOUT (MHz)
Figure 27. Power Dissipation vs. REFCLK (Single-Tone Mode, fOUT = REFCLK/5)
Rev. C | Page 13 of 32
Figure 28. Supply Current vs. fOUT (1 GHz REFCLK)
420
03166-024
POWER DISSIPATION (W)
1.6
0
3.5V
500
AD9858
THEORY OF OPERATION
The AD9858 DDS is a flexible device that can address a wide range
of applications. The device consists of a numerically controlled
oscillator (NCO) with a 32-bit phase accumulator, 14-bit phase
offset adjustment, a power efficient DDS core, and a 1 GSPS,
10-bit DAC. The AD9858 incorporates additional capabilities
for automated frequency sweeping. The device also offers an
analog mixer, a PFD, and a programmable CP with advanced fast
lock capability. These RF building blocks can be used for various
frequency synthesis loops or, as needed, in system design.
The AD9858 can directly generate frequencies up to 400 MHz
when driven at a 1 GHz internal clock speed. This clock can be
derived from an external clock source of up to 2 GHz by using
the on-chip, divide-by-2 feature. The on-chip mixer, PFD, and CP
make possible a variety of synthesizer configurations capable of
generating frequencies in the 1 GHz to 2 GHz range or higher.
The AD9858 offers the advantages of a DDS with the additional
flexibility to work in concert with analog frequency synthesis
techniques (PLL, mixing) to generate precision frequency signals
with high resolution, fast frequency hopping, fast settling time,
and automated frequency sweeping capabilities.
Writing data to its on-chip digital registers that control all
operations of the device easily configures the AD9858. The
AD9858 offers a choice of serial or parallel ports for controlling
the device. Four user profiles can be selected by a pair of
external pins. These profiles allow independent setting of the
frequency tuning word and the phase offset adjustment word
for each of the four selectable configurations.
The AD9858 can be programmed to operate in single-tone mode
or in frequency sweeping mode. To save on power consumption,
there is also a programmable full sleep mode, during which most
of the device is powered down to reduce current flow.
The operation of a direct digital synthesizer (DDS) is described
in detail in a tutorial available from Analog Devices at
www.analog.com/dds.
COMPONENT BLOCKS
DDS Core
The DDS core generates the numeric values that represent a
sinusoid in the digital domain. Depending on the operating
mode of the DDS, this sinusoid may be changed in frequency,
phase, or perhaps modulated by an information carrying signal.
The frequency of the output signal is determined by a userprogrammed frequency tuning word (FTW). The relation of
the output frequency of the device to the system clock (SYSCLK)
is determined by
f OUT =
(FTW × SYSCLK )
where N = 32.
2N
For a more detailed explanation of a DDS core, consult the DDS
tutorial at www.analog.com/dds.
DAC Output
The AD9858 includes a 10-bit current output DAC. Two
complementary outputs provide a combined full-scale output
current (IOUT, IOUT). Differential outputs reduce the amount
of common-mode noise that may be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio (SNR).
The full-scale current is controlled by means of an external
resistor (RSET) connected between the DACISET pin and analog
ground. The full-scale current is proportional to the resistor
value as
RSET = 39.19/IOUT
The maximum full-scale output current of the combined DAC
outputs is 40 mA, but limiting the output to 20 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is (AVDD − 1.5 V) to (AVDD + 0.5 V).
Voltages developed beyond this range cause excessive DAC
distortion and can damage the DAC output circuitry. Proper
attention should be paid to the load termination to keep the
output voltage within this compliance range. When terminating
the differential outputs into a transformer, the center tap should
be attached to AVDD.
PLL Frequency Synthesizer
The PLL frequency synthesizer is a group of independent
synthesis blocks designed to be used with the DDS to expand
the range of synthesis applications. These blocks are a digital
PFD that drives a CP. The charge pump incorporates fast locking
logic, described in the Fast Locking Logic section. Based on
system requirements, the user supplies an external loop filter
and VCO. A high speed analog mixer is included for translation
synthesis loops. Using the different blocks in the PLL frequency
synthesizer, in conjunction with the DDS, the user can create
translation loops (also known as offset loops), fractional divider
loops, and traditional PLL loops to multiply the output of the DDS
in frequency.
Phase Frequency Detector (PFD)
The phase frequency detector has two inputs: PDIN and DIVIN.
Both are analog inputs that can operate in differential mode or
single-ended mode. Both operate at frequencies up to 150 MHz,
although signals of up to 400 MHz can be accommodated on the
inputs when the divide-by-4 functions are used. The expected
input level for both PDIN and DIVIN is in the range of 800 mV p-p
(differential) and 400 mV p-p (single-ended). A programmable
divider that offers division ratios of M, N = {1, 2, 4} immediately
follows the input. The division ratio is controlled by means of
the control function register.
Rev. C | Page 14 of 32
AD9858
The charge pump output reference current is determined by an
external resistor (~2.4 kΩ), which establishes a 500 μA maximum
internal baseline current (ICP0). The baseline current is scaled to
provide the appropriate drive current for the various operating
modes (frequency detect, wide closed-loop, and final closedloop) of the CP. The amount of scaling in each mode is
programmable by means of the values stored in the control
function register, giving the user maximum flexibility of the
frequency locking capability of the PLL.
The CP polarity can be configured as either positive or negative
with respect to PDIN. When the CP polarity is positive, if DIVIN
leads PDIN, the charge pump attempts to decrease the voltage at
the VCO control node. If DIVIN lags PDIN, the charge pump works
to increase the voltage at the VCO control node. When the CP
polarity is negative, the opposite occurs. This allows the user to
define either input as the feedback path. This also allows the
AD9858 to accommodate ground-referenced or supply-referenced
VCOs. This functionality is defined by the charge pump polarity
bit in the control function register, CFR[10].
Internal to the CP, the ICP0 current is scaled to provide different
output drive current values for the various modes of operation.
In normal operating mode, the final closed-loop mode can be
programmed to scale ICP0 by 1, 2, 3, or 4. Setting the charge
pump current offset bit, CFR[13], applies a 2 mA offset to the
programmed charge pump current, allowing ICP0 scaler values
of 5, 6, 7, or 8. The wide closed-loop mode can be programmed
to scale ICP0 by 0, 2, 4, 6, 8, 10, 12, or 14. The frequency detect
mode can be programmed to scale ICP0 by 0, 20, 40, or 60. The
different modes of operation, controlled by the fast locking
logic, are discussed in the Fast Locking Logic section.
The CP has an independent set of power pins that can operate
at up to 5.25 V. While the device can operate from ground to
rail, the voltage compliance should be kept in the 0.5 V to
4.5 V range to ensure the best steady-state performance. The
combination of programmable output current, programmable
polarity, wide compliance range, and a proprietary fast lock
capability offers the flexibility necessary for the digital PLL to
operate within a broad range of PLL applications.
Fast Locking Logic
The charge pump includes a fast locking algorithm that helps
to overcome the traditional limitations of PLLs with regard to
frequency switching time. The fast locking algorithm works in
conjunction with the loop filter shown in Figure 29 to provide
extremely fast frequency switching performance.
Based on the error seen between the feedback signal and the
reference signal, the fast locking algorithm puts the charge
pump into one of three states: frequency detect mode, a wide
closed-loop mode, or a final closed-loop mode. In the frequency
detect mode, the feedback and reference signals register
substantial phase and frequency errors. Rather than operating
in a continuous closed-loop feedback mode, the charge pump
supplies a fixed current of the correct polarity to the VCO control
node that drives the loop towards frequency lock. When frequency
lock is detected, the fast locking logic shifts the part into one of
the closed-loop modes. In the closed-loop modes, either wide
or final, the charge pump supplies current to the loop filter as
directed by the PFD. The frequency detect mode is intended to
bring the system to a level of frequency lock from which the
intermediary closed-loop system can quickly achieve phase lock.
The level of frequency lock accuracy aimed for is typically
referred to as the lock range. When the frequency is within
the lock range, the time required to achieve phase lock can be
determined by standard PLL transient analysis methods. The
charge pump current sources associated with the frequency
detect mode are connected to Pin 64 (CPFL), and the closedloop current sources are connected to Pin 65 (CP) and Pin 66 (CP).
Pin 64 is connected directly to the loop filter zero compensation
capacitor, as shown in Figure 29. This connection allows the
smoothest transition from the frequency detect mode to the
closed-loop modes and enables faster overall switching times.
Pin 65 and Pin 66 are connected to the loop filter in the
conventional manner.
CP
AD9858
CP
R2
CPFL
C2
03166-A-032
Charge Pump (CP)
Figure 29. Charge Pump to Loop Filter Connection
The frequency detection block works as follows. The comparison
logic in the frequency detection circuitry operates one eighth of
the DDS system clock. A comparison is made of the frequencies
present at PDIN and DIVIN over 19 DDS clock cycles.
To ensure that frequency lock detection is achieved while the
frequency difference is within the PLL lock range, the slew rate
of the VCO input should be limited such that the lock range
cannot be traversed within 152 system clock cycles. The slew
rate of the VCO input is determined by the programmed level
of frequency detect current and the size of the zero compensation
capacitor according to the following relationship:
dv
dt
Rev. C | Page 15 of 32
=
If
det
CZ
AD9858
When frequency detection occurs, the loop is closed and the
loop is locked based on the current programmed for the wide
closed-loop mode. It is important that the loop be designed for
closed-loop stability while in the wide closed-loop mode. In this
mode, less phase margin can usually be tolerated, because this
mode is only used to enhance the lock time but is not used in
the locked free running state. When the wide closed-loop mode
achieves phase lock as determined by an internal lock detector,
the phase detector/charge pump transitions into the final
closed-loop state. If no wide closed-loop current is programmed,
the loop transitions directly from the frequency detect mode
into the final closed-loop state. In the final closed-loop state,
optimize the loop characteristics for the desired free running
loop bandwidth.
The frequency detect mode is primarily useful in offset or
translation loop applications where the phase detector inputs
are more likely to detect large frequency transitions. For loop
applications with significant amounts of division in the feedback
loop, the frequency detection mode may not activate. This is due
to the limited amount of frequency difference that is experienced
at the phase detector inputs. For these applications, the primary
means of accelerating the frequency settling time is to design
the loop to acquire lock with the wide closed-loop setting and
then switch to the final closed-loop setting.
As previously mentioned, care should be taken when planning
for a large transition using the frequency detect mode to ensure
that the charge pump does not cause the VCO to overshoot the
closed-loop lock range, because cycle slipping can occur, which
results in extended delays. Figure 30 shows two system responses.
In the first response, the charge pump output current is
maximized during the frequency detect mode so that, after
152 clock cycles, the VCO voltage exceeds the closed-loop lock
range. The second system response provides less current during
the frequency detect mode. Although this results in a longer
delay in approaching the closed-loop lock range, because the
system does not exceed the closed-loop range, the fast locking
logic shifts the charge pump into intermediary closed-loop
mode, resulting in a shorter overall frequency switching time.
Analog Mixer
The analog mixer is included for translation loops, also known
as offset loops. The radio frequency (RF) and local oscillator
(LO) inputs are designed to operate at frequencies up to 2 GHz.
Both inputs are differential analog input stages. Both input stages
are internally dc biased and should be connected through an
external ac coupling mechanism. The expected input level is
in the range of 800 mV p-p (differential). The intermediate
frequency (IF) output is a differential analog output stage
designed to operate at frequencies less than 400 MHz. This
mixer is based on the Gilbert cell architecture.
MODES OF OPERATION
The AD9858 DDS section has three modes of operation: single
tone, frequency sweeping, and full sleep. The RF building blocks
(PFD, CP, and mixer) can be active or powered down, used or
unused, in the active modes.
In the single-tone mode, the device generates a single output
frequency determined by a 32-bit word (frequency tuning word,
FTW) loaded to an internal register. This frequency can be changed
as desired, and frequency hopping can be accomplished at a rate
limited only by the time required to update the appropriate
registers. If even faster hopping is needed, the four profiles
allow rapid hopping among the four frequencies stored in them
by means of external select pins.
The frequency sweeping mode allows for the automation of most of
the frequency sweeping task, making chirp and other frequency
sweeping applications possible without multiple register operations
via the I/O port.
In whatever mode the device is operating, changes in frequency
are phase continuous (they do not cause discontinuities in the
phase of the output signal). The first phase value after a frequency
change is an increment of the last phase value before the change,
but at the phase increment value (FTW) of the new tuning
word. (This is not the same as phase coherent over frequency
changes; see Figure 31.)
REFERENCE SIGNAL
fREF = A
PHASE CONTINUOUS
fREF = A
fOUT = 2A
θ = 2θREFФ
VCO VOLTAGE
fOUT = A
fOUT = 2A
θ = 2θREF+Ф + Ф'
θ = θREF
PHASE COHERENT
fOUT = A
fREF = A
fOUT = 2A
θ = 2θREF
fOUT = A
θ = θREF
TIME
Figure 30. Typical Charge Pump Responses
WHERE θ = PHASE OF OUTPUT SIGNAL, Ф = PHASE AT TIME OF FIRST FREQUENCY
TRANSITION, AND Ф' = PHASE AT TIME OF SECOND FREQUENCY TRANSITION.
Figure 31. Difference Between a Phase Continuous Frequency Change and
a Phase Coherent Frequency Change
Rev. C | Page 16 of 32
03166-034
03166-A-033
θ = θREF
AD9858
Single-Tone Mode
When the decimal number is calculated, it must be rounded to
an integer and converted to a 32-bit binary value. The frequency
resolution of the AD9858 is 0.233 Hz when the SYSCLK is 1 GHz.
When in single-tone mode, the AD9858 generates a signal, or
tone, of a single desired frequency. This frequency is set by the
value loaded by the user into the chip’s FTW register. This
frequency can be between 0 Hz and somewhat below one-half
of the DAC sampling frequency (SYSCLK). One-half of the
sampling frequency is commonly called the Nyquist frequency.
The practical upper limit to the fundamental frequency range of
a DDS is determined by the characteristics of the external lowpass filter, known as the reconstruction filter, which must follow
the DAC output of the DDS. This filter reconstructs the desired
analog sine wave output signal from the stream of sampled
amplitude values output by the DAC at the sample rate (SYSCLK).
Frequency Sweeping Mode
The AD9858 provides an automated frequency sweeping capability.
This allows the AD9858 to generate frequency swept signals for
chirped radar or other applications. The AD9858 includes features
that automate much of the task of executing frequency sweeps.
The frequency sweep feature is implemented through the use
of a frequency accumulator (not to be confused with the phase
accumulator). The frequency accumulator repeatedly adds an
incremental quantity to the current FTW, thereby creating new
instantaneous frequency tuning words, causing the frequency
generated by the DDS to change with time. The frequency
increment, or step size, is loaded into the delta frequency
tuning word (DFTW) register. The rate at which the frequency
is incremented is set by the delta frequency ramp rate word
(DFRRW) register. Together these registers enable the AD9858 to
sweep from a beginning frequency set by the FTW, upwards or
downwards, at a desired rate and frequency step size. The result is
a linear frequency sweep or chirp.
A DDS is a sampled data system. As the fundamental frequency
of the DDS approaches the Nyquist frequency, the lower first
image approaches the Nyquist frequency from above. As the
fundamental frequency approaches the Nyquist frequency, it
becomes difficult, and finally impossible, to design and construct a
low-pass filter that provides adequate attenuation for the first
image frequency component.
The maximum usable frequency in the fundamental range of
the DDS is typically between 40% and 45% relative to the SYSCLK
frequency, depending on the reconstruction filter. With a 1 GHz
SYSCLK, the AD9858 is capable of producing maximum output
frequencies of between 400 MHz and 450 MHz, depending on the
reconstruction filter and the application system requirements.
The DFRRW functions as a countdown timer, in which the
value of the DFRRW is decremented at the rate of SYSCLK/8.
This means that the most rapid frequency word update occurs
when a value of 1 is loaded into the DFRRW and results in a
frequency increment at 1/8 of the SYSCLK rate. With a SYSCLK
of 1 GHz, the frequency can be incremented at a maximum rate
of 125 MHz (DFRRW = 1). The DFTW must specify whether
the frequency sweep should proceed up or down from the starting
frequency (FTW). Therefore, the DFTW is expressed as a twos
complement binary value, in which positive indicates up and
negative indicates down.
For a desired output frequency (fOUT) and sampling rate (SYSCLK),
the FTW of the AD9858 is calculated by
FTW = (fOUT × 2N)/SYSCLK
DELTA FREQUENCY TUNING WORD
16ns
24ns
32ns
40ns
80ns
120ns
DELTA FREQUENCY RAMP RATE WORD (≥8ns)
TIME
TIME
Figure 32. Frequency vs. Time Plots for a Given Sweep Profile
Rev. C | Page 17 of 32
160ns
03166-035
8ns
FREQUENCY
FREQUENCY
where:
N is the phase accumulator resolution in bits (32 in the AD9858).
SYSCLK is in Hertz.
FTW is a decimal number.
AD9858
Full Sleep Mode
A DFRRW value of 0 written to the register stops all frequency
sweeping. There is no automated stop-at-a-given-frequency
function. The user must calculate the time interval required to
reach the final frequency and then issue a command to write 0
into the DFRRW register. The time required for a frequency
sweep is calculated by
SYSCLK 2
SYNCHRONIZATION
DFRRW
×
DFTW
SYNCLK and FUD Pins
Timing for the AD9858 is provided via the user-supplied REFCLK
input. The REFCLK input is buffered and is the source for the
internally generated SYSCLK. The frequency of SYSCLK can be
either the same as REFCLK or half that of REFCLK (CFR[6]).
The REFCLK input is capable of handling input frequencies as
high as 2 GHz. However, the device is designed for a maximum
SYSCLK frequency of 1 GHz. Thus, it is mandatory that the
divide-by-2 SYSCLK function be enabled when the frequency
of REFCLK is greater than 1 GHz.
where:
T is the duration of the sweep in seconds.
fS is the starting frequency determined by
fS =
FTW
× SYSCLK
2 32
fF is the final frequency.
The delta frequency step size is given by
Δf =
DFTW × SYSCLK
,
2 31
SYSCLK serves as the sample clock for the DAC and is fed to
a divide-by-8 frequency divider to produce SYNCLK. SYNCLK
is provided to the user on the SYNCLK pin. This enables
synchronization of external hardware with the internal DDS
clock of the AD9858. External hardware that is synchronized
to the SYNCLK signal can then be used to provide the frequency
update (FUD) signal to the AD9858. The FUD signal and
SYNCLK are used to transfer the internal buffer register
contents into the memory registers of the device. Figure 33
shows a block diagram of the synchronization methodology,
and Figure 34 shows an I/O synchronization timing diagram.
remembering that DFTW is a signed (twos complement) value.
The time between each frequency step (Δt) is given by
Δt =
8 × DFRRW
SYSCLK
The value of the stop frequency fF is determined by
fF = fS +t ×
Δf
Δt
Returning to Starting Frequency
SYNCLK is also used to synchronize the assertion of the profile
select pins (PS0 and PS1). The FUD, PS0, and PS1 pins must be
set up and held around the rising edge of SYNCLK.
The original frequency tuning word (FTW), which is written into
the frequency tuning register, does not change at any time during
a sweep operation. This means that the DDS can return to the
sweep starting frequency at any time during a sweep. Setting the
control bit, autoclear frequency accumulator, forces the frequency
accumulator to 0, instantly returning the DDS to the frequency
stored as FTW.
SYNCLK
DISABLE
2 GHz DIVIDER
DISABLE
÷8
SYNCLK
0
÷2
Q
UPDATE REGS
EDGE
DETECTION
LOGIC
TO CORE LOGIC
0
SYNCLK
0
SYSCLK
1
1
REFCLK
REGISTER
MEMORY
Q
D
PS0, PS1
D
FUD
BUFFER
MEMORY
Figure 33. I/O Synchronization Block Diagram
Rev. C | Page 18 of 32
WR/SCLK
ADDRx
DATA
03166-036
t=
f F − f S × 2 34
Setting all of the power-down bits in the control function register
activates full sleep mode. During the power-down condition,
the clocks associated with the various functional blocks of the
device are turned off, thereby offering a significant power savings.
AD9858
SYSCLK
FUD REGISTERED
FUD REGISTERED
FUD EDGE DETECTED
FUD EDGE DETECTED
SYNCLK
FUD*
CONTROL
REGISTER
DATA
VALUE 2
VALUE 1 (ASYNCHRONOUSLY LOADED VIA I/O PORT)
VALUE 0
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
VALUE 1
VALUE 2
* FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF THE
RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATE REGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE
TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PIN IS EQUIVALENT TO ASSERTING A VALID
FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
03166-037
I/O BUFFER
MEMORY
Figure 34. I/O Synchronization Timing Diagram
Frequency Planning
To achieve the best possible spurious performance when using
the AD9858 in a hybrid synthesizer configuration, employ
frequency planning. Frequency planning consists of being
aware of the mechanisms that determine the location of the
worst-case spurs and then using the appropriate loop tuning
parameters to place these spurs either outside the loop bandwidth,
so that they are attenuated, or completely outside the frequency
range of interest.
When using the fractional divider configuration, the worst-case
spurs occur whenever the images of the DAC harmonics fold
back such that they are close to the DAC fundamental or carrier
frequency. If these images fall within the loop bandwidth, they
are gained up by approximately 20 × logN, where N is the gain
in the loop. If N is relatively high, these spurs can still realize
significant gain, even if they are slightly outside the loop bandwidth, because the loop attenuation rate is typically 20 dB/dec
in this region. DAC images occur at
N × fCLOCK ± M × fOUT
where N and M are integer multiples of fCLOCK and fOUT,
respectively.
Figure 20 shows a high spurious condition where the low-order
odd harmonics are folding back around the fundamental. Figure 24
shows that the worst spurs are confined to a narrow region
around the carrier and that wideband spurs are attenuated.
Figure 17 shows an alternate frequency plan that results in the
same carrier frequency. The output frequency of the DAC is set by
fOUT = fCLOCK × FTW/2N
This makes it possible to produce the same fOUT by different
combinations of fCLOCK and FTW. In this case, the worst DAC
spurs are placed well outside the loop bandwidth such that they
are attenuated below the noise floor. Figure 21 shows a wideband
plot for this frequency plan.
Other frequency combinations that result in high spurious signals
are when subharmonics of fCLOCK fall within or near the loop
bandwidth. To avoid this, ensure that the DAC fOUT is sufficiently
offset from the subharmonics of fCLOCK such that these products
are attenuated by the loop.
Frequency planning for the translation loop is similar in that
the DAC images and the fCLOCK subharmonics need to be
considered. Figure 25 and Figure 26 show results for a high
spurious configuration where odd order images are folding
back close to the carrier. Figure 22 and Figure 23 show an
alternative frequency plan that generates the same carrier
frequency with low spurious content. Because this loop also
requires a mixer LO frequency, additional care is required in
planning for this frequency arrangement. Generally, there is
some mixer LO feedthrough. The amount of feedthrough
depends on the PCB layout isolation as well as the mixer LO
power level, but levels of −80 dBc can typically be achieved.
Figure 26 shows results for a situation where the mixer LO
component shows up in the spectrum at 1.41 GHz, and another
spur component shows up at Mixer LO + fCLOCK/8. This places
the mixer LO frequency well outside the bandwidth of interest,
resulting in the spectrum shown in Figure 25.
PROGRAMMING THE AD9858
The transfer of data from the user to the DDS core of the device
is a 2-step process. In a write operation, the user first writes the
data to the I/O buffer by using either the parallel port (which
includes bits for address and data) or the serial port (where the
address and data are combined in a serial word). Regardless of
the method used to enter data to the I/O buffer, the DDS core
cannot access the data until the data is latched into the memory
registers from the I/O buffer. Toggling the FUD pin or changing
one of the profile select pins causes an update of all elements of
the I/O buffer memory into the register memory of the DDS core.
Rev. C | Page 19 of 32
AD9858
I/O Port Functionality
Parallel Programming Mode
The I/O port can operate in either serial or parallel programming
mode. Mode selection is accomplished via the SPSELECT pin.
In parallel programming mode, the I/O port makes use of eight
bidirectional data pins (D7 to D0), six address input pins (ADDR5
to ADDR0), a read input pin (RD), and a write input pin (WR).
A register is selected by providing the proper address combination
as defined in the register map (see Table 6). Read or write
functionality is invoked by pulsing the appropriate pin (RD or
WR); the two operations are mutually exclusive. The read or write
data is transported on the D7 to D0 pins. The correlation between
the D7 to D0 data bits and their functionality at a specific register
address is detailed in the register map (see Table 6) and register
bit description.
The ability to read back the contents of a register is provided in
both modes to facilitate the debug process during the user’s
prototyping phase of a design. In either mode, however, the
reading back of profile registers requires that the profile select
pins (PS0 and PS1) be configured to select the desired register
bank. When reading a register that resides in one of the profiles,
the register address acts as an offset to select one of the registers
among the group of registers defined by the profile. The profile
select pins control the base address of the register bank and
select the appropriate register grouping.
ADDR[5:0]
A1
Parallel I/O operation allows write access to each byte of any
register in the I/O buffer memory in a single I/O operation.
Readback capability is slower than write capability. It is intended as
a low speed function for debug purposes. Timing for both write
and read cycles is depicted in Figure 35 and Figure 36.
A2
D1
D[7:0]
A3
D2
D3
WR
tASU
tDSU
tAHU
tDHU
tWRHIGH
tWRLOW
SPECIFICATION
tASU
tDSU
tAHU
tDHU
tWRLOW
tWRHIGH
tWR
VALUE
DESCRIPTION
3ns
3.5ns
0ns
0ns
3ns
6ns
9ns
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL INACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
WR SIGNAL MINIMUM PERIOD
Figure 35. I/O Port Write Cycle Timing (Parallel)
Rev. C | Page 20 of 32
03166-038
tWR
AD9858
ADDR[5:0]
A1
A2
D[7:0]
D1
D2
A3
D3
RD
tRDLOV
tRDHOZ
tADV
SPECIFICATION
tADV
tAHD
tRDLOV
tRDHOZ
VALUE
DESCRIPTION
15ns
5ns
15ns
10ns
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
03166-039
tAHD
Figure 36. I/O Port Read Cycle Timing (Parallel)
Serial Programming Mode
In serial programming mode, the I/O port uses a chip select pin
(CS), a serial clock pin (SCLK), an I/O reset pin (IORESET),
and either one or two serial data pins (SDIO and/or SDO). The
number of serial data pins used depends on the configuration of
the I/O port, that is, whether it has been configured for 2-wire
or 3-wire serial operation as defined by the control function
register. In 2-wire mode, the SDIO pin operates as a bidirectional
serial data pin. In 3-wire mode, the SDIO pin operates as a
serial data input pin only, and the SDO pin acts as the serial
output. The maximum rate of SCLK is guaranteed only for write
operation.
The serial port is an SPI-compatible serial interface. Serial port
communication occurs in two phases. Phase 1 is an instruction
cycle consisting of an 8-bit word. The MSB of the instruction
byte flags the ensuing operation as a read or write operation.
The six LSBs define the serial address of the target register as
defined in the register map. The instruction byte format is given in
Table 5.
Table 5.
D7 (MSB)
1: Read
0: Write
D6
X
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0 (LSB)
A0
Phase 2 of a serial port communication contains the data to be
routed to/from the addressed register. The number of bytes
transferred during Phase 2 depends on the length of the target
register. Serial operation requires that all bits associated with a
serial register address be transferred.
Both phases of a serial port communication require the serial
data clock (SCLK) to be operating. When writing to the device,
serial bits are transferred on the rising edge of SCLK. When
reading from the device, serial output bits are transferred on the
falling edge of SCLK. The bit order for both phases of a serial
port communication is selectable via the control function register.
The CS pin serves as a chip select control line. When CS is in a
Logic 1 state, the SDO and SDIO pins are disabled (forced into a
high impedance state). When the CS pin is in a Logic 0 state,
the SDO and SDIO pins are active. This allows multiple devices
to reside on a single serial bus. If multiple devices are connected
to the same serial bus, then communication with an individual
device is accomplished by setting CS to a Logic 0 state on the
target device, but to a Logic 1 state on all other devices. In this
way, serial communication occurs only between the controller
and the target device.
When I/O synchronization is lost between the AD9858 and
the external controller, the IORESET pin provides a means
to reestablish synchronization without initializing the entire
device. Asserting the active high IORESET pin resets the serial
port state machine. This terminates the current I/O operation
and puts the device into a state in which the next eight SCLK
pulses are expected to be the instruction byte of the next I/O
transfer. Any information previously written to the memory
registers during the last valid communication cycle prior to loss
of synchronization remains intact.
Rev. C | Page 21 of 32
AD9858
REGISTER MAP
The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in
hexadecimal format. Square brackets [] are used to reference specific bits or ranges of bits. For example, [3] designates Bit 3, and [7:3]
designates the range of bits from 7 down to 3, inclusive.
Table 6.
Register
Name
Control
function
register
(CFR)
Address
Ser
Par
0x00 0x00
[7:0]
0x01
[15:8]
0x02
[23:16]
0x03
[31:24]
Delta freq.
tuning
word
(DFTW)
0x01
Delta
frequency
ramp rate
(DFRRW)
Frequency
Tuning
Word 0
(FTW0)
0x02
Phase
Offset
Word 0
(POW0)
Frequency
Tuning
Word 1
(FTW1)
0x04
Phase
Offset
Word 1
(POW1)
Frequency
Tuning
Word 2
(FTW2)
0x06
0x03
0x05
0x07
(MSB)
Bit 7
Not
used
Freq.
sweep
enable
Auto Clr
freq.
accum
Bit 6
2 GHz
divider
disable
Bit 5
SYNCLK
disable
Enable
sine
output
Auto Clr
phase
accum
Charge
pump
offset
Load
delta
freq
timer
Final closed-loop
mode charge pump current
(see Table 8)
Frequency detect
mode charge
pump current
(see Table 7)
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Bit 4
Mixer
powerdown
Bit 3
Phase
detect
powerdown
Phase detector
divider ratio (N)
(see Table 10)
Clear
Clear
freq
phase
accum accum
(LSB)
Bit 0
LSB first
Bit 2
Powerdown
Bit 1
SDIO
input
only
Charge
pump
polarity
Not
used
Phase detector
divider ratio (M)
(see Table 11)
Fast
FTW for
lock
fast lock
enable
Wide closed-loop mode
charge pump current
(see Table 9)
Default
Value
0x18
Profile
N/A
0x00
N/A
0x00
N/A
0x00
N/A
Delta Frequency Word[7:0]
Delta Frequency Word[15:8]
Delta Frequency Word[23:16]
Delta Frequency Word[31:24]
Delta Frequency Ramp Rate Word[7:0]
Delta Frequency Ramp Rate Word[15:8]
N/A
N/A
N/A
N/A
N/A
N/A
Not used
Frequency Tuning Word 0[7:0]
Frequency Tuning Word 0[15:8]
Frequency Tuning Word 0[23:16]
Frequency Tuning Word 0[31:24]
Phase Offset Word 0[7:0]
Phase Offset Word 0[13:8]
Not used
Frequency Tuning Word 1[7:0]
Frequency Tuning Word 1[15:8]
Frequency Tuning Word 1[23:16]
Frequency Tuning Word 1[31:24]
Phase Offset Word 1[7:0]
Phase Offset Word 1[13:8]
1
1
1
1
1
1
Frequency Tuning Word 2[7:0]
Frequency Tuning Word 2[15:8]
Frequency Tuning Word 2[23:16]
Frequency Tuning Word 2[31:24]
2
2
2
2
Rev. C | Page 22 of 32
0x00
0x00
0x00
0x00
0x00
0x00
0
0
0
0
0
0
AD9858
Register
Name
Phase
Offset
Word 2
(POW2)
Frequency
Tuning
Word 3
(FTW3)
Address
Ser
Par
0x08 0x1A
0x1B
Phase
Offset
Word 3
(POW3)
Reserved
0x0A
0x09
0x0B
(MSB)
Bit 7
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Phase Offset Word 2[7:0]
Phase Offset Word 2[13:8]
Not used
Reserved, do not write, leave at 0xFF
Reserved, do not write, leave at 0xFF
REGISTER BIT DESCRIPTIONS
The CFR comprises four bytes. CFR is used to control the
various functions, features, and modes of the AD9858. The
functionality of each bit follows. Note that the register bits are
identified according to their serial register bit locations beginning
with the most significant bit.
CFR[31:30]: Frequency Detect Mode Charge Pump Current
These bits are used to set the scale factor for the frequency
detect mode charge pump output current (see Table 7). The
charge pump delivers the scaled output current when the
control logic forces the charge pump into its frequency detect
operating mode. The charge pump’s baseline output current
(ICP0) is determined by the external CPISET resistor and is
given by
3
3
3
3
3
3
0xFE
0xFF
N/A
N/A
CFR[29:27]
0xx
100
101
110
111
Final Closed-Loop Mode
Charge Pump Scale Value
0
1
2
3
4
Notes
IOUT = 0 (default)
IOUT = ICP0
IOUT = 2 × ICP0
IOUT = 3 × ICP0
IOUT = 4 × ICP0
CFR[26:24]: Wide Closed-Loop Mode Charge Pump
Current
These bits are used to set the scale factor for the wide closedloop charge pump output current (see Table 9). The charge
pump delivers the scaled output current when the control logic
forces the charge pump into its wide closed-loop operating mode.
Table 9.
ICP0 = 1.24/CPISET
The recommended nominal value of the CPISET resistor is
2.4 kΩ, which yields a baseline current of 500 μA.
Table 7.
Frequency Detect Mode
Charge Pump Scale Value
0
2
3
4
Profile
2
2
Table 8.
Control Function Register (CFR)
CFR[31:30]
00
01
10
11
Default
Value
Frequency Tuning Word 3[7:0]
Frequency Tuning Word 3[15:8]
Frequency Tuning Word 3[23:16]
Frequency Tuning Word 3[31:24]
Phase Offset Word 3[7:0]
Phase Offset Word 3[13:8]
Not used
0x22
0x23
(LSB)
Bit 0
Notes
IOUT = 0 (default)
IOUT = 20 × ICP0
IOUT = 40 × ICP0
IOUT = 60 × ICP0
CFR[26:24]
000
001
010
011
100
101
110
111
Wide Closed-Loop Mode
Charge Pump Scale Value
0
2
4
6
8
10
12
14
Notes
IOUT = 0 (default)
IOUT = 2 × ICP0
IOUT = 4 × ICP0
IOUT = 6 × ICP0
IOUT = 8 × ICP0
IOUT = 10 × ICP0
IOUT = 12 × ICP0
IOUT = 14 × ICP0
CFR[23]: Auto Clear Frequency Accumulator Bit
CFR[29:27]: Final Closed-Loop Mode Charge Pump
Current
These bits are used to set the scale factor for the final closedloop mode charge pump output current (see Table 8). The
charge pump delivers the scaled output current when the control
logic forces the charge pump into its final closed-loop mode.
When CFR[23] = 0 (default), a new delta frequency word is
applied to the input of the accumulator and added to the
currently stored value.
When CFR[23] = 1, this bit automatically synchronously clears
(loads zeros into) the frequency accumulator for one cycle upon
reception of the FUD sequence indicator.
Rev. C | Page 23 of 32
AD9858
CFR[22]: Auto Clear Phase Accumulator Bit
CFR[13]: Charge Pump Offset Bit
When CFR[22] = 0 (default), a new frequency tuning word is
applied to the input of the phase accumulator and added to the
currently stored value.
When CFR[13] = 0 (default), the charge pump operates with
normal current settings.
When CFR[22] = 1, this bit automatically synchronously clears
(loads zeros into) the phase accumulator for one cycle upon
reception of the FUD sequence indicator.
CFR[21]: Load Delta Frequency Timer
When CFR[21] = 0 (default), the contents of the delta frequency
ramp rate word are loaded into the ramp rate timer (down counter)
upon detection of a FUD sequence.
When CFR[21] = 1, the contents of the delta frequency ramp
rate word are loaded into the ramp rate timer upon timeout
with no regard to the state of the FUD sequence indicator (that
is, the FUD sequence indicator is ignored).
CFR[20]: Clear Frequency Accumulator Bit
When CFR[20] = 1, the frequency accumulator is synchronously
cleared and is held clear until CFR[20] is returned to a Logic 0
state (default).
CFR[19]: Clear Phase Accumulator Bit
When CFR[19] = 1, the phase accumulator is synchronously
cleared and is held clear until CFR[19] is returned to a Logic 0
state (default).
When CFR[13] = 1, the charge pump operates with offset
current settings (see Charge Pump section).
CFR[12:11]: Phase Detector Divider Ratio (N)
These bits set the phase detector divide value (see Table 10).
Table 10.
CFR[12:11]
00
01
1x
Phase Detector Divider Ratio (N)
1
2
4
Notes
Default value
LSB ignored
CFR[10]: Charge Pump Polarity Bit
When CFR[10] = 0 (default), the charge pump is set up for
operation with a ground-referenced VCO. In this mode, the charge
pump sources current when the frequency at PDIN is less than
the frequency at DIVIN. It sinks current when the opposite is true.
When CFR[10] = 1, the charge pump is set up for a supplyreferenced VCO. In this mode, the source/sink operation of the
charge pump is opposite that for a ground-referenced VCO.
CFR[9:8]: Phase Detector Divider Ratio (M)
These bits set the phase detector divide value (see Table 11).
CFR[18]: Not Used.
Table 11.
CFR[17]: Fast Lock Enable Bit
When CFR[17] = 0 (default), the PLL’s fast lock algorithm is
disabled. When CFR[17] = 1, the PLL’s fast-lock algorithm is active.
CFR[16]: FTW for Fast Lock Bit
This bit allows the user to control whether or not the PLL’s fast
lock algorithm uses the tuning word value to determine
whether or not to enter fast locking mode.
CFR[9:8]
00
01
1x
Phase Detector Divider Ratio (M)
1
2
4
Notes
Default value
LSB ignored
CFR[7]: Not Used
CFR[6]: 2 GHz Divider Disable Bit
When CFR[16] = 0 (default), the fast locking algorithm of the
PLL considers the relationship between the programmed
frequency tuning word and the instantaneous frequency as part
of the locking process.
When CFR[6] = 0 (default), the REFCLK divide-by-2 function
is enabled. REFCLK input can be up to 2 GHz.
When CFR[16] = 1, the fast locking algorithm of the PLL does
not use the frequency tuning word as part of the locking process.
CFR[5]: SYNCLK Disable Bit
CFR[15]: Frequency Sweep Enable Bit
When CFR[15] = 0 (default), the device is in single-tone mode.
When CFR[15] = 1, the device is in the frequency sweep mode.
CFR[14]: Enable Sine Output Bit
When CFR[14] = 0 (default), the angle-to-amplitude conversion
logic employs a cosine function.
When CFR[6] = 1, the REFCLK divide-by-2 function is
disabled. REFCLK input must be no more than 1 GHz.
When CFR[5] = 0 (default), the SYNCLK pin is active.
When CFR[5] = 1, the SYNCLK pin assumes a static Logic 0
state (disabled). In this state, the pin drive logic is shut down to
keep noise generated by the digital circuitry at a minimum.
However, the synchronization circuitry remains active (internally)
to maintain normal device timing.
When CFR[14] = 1, the angle-to-amplitude conversion logic
employs a sine function.
Rev. C | Page 24 of 32
AD9858
CFR[4:2]: Power-Down Bits
Active high (Logic 1) powers down the respective function.
Writing a Logic 1 to all three bits causes the device to enter full
sleep mode.
CFR[4] is used to shut down the analog mixer stage (default = 1).
CFR[3] is used to shut down the phase detector and charge
pump circuitry (default = 1).
CFR[2] is used to shut down the DDS core and DAC and to
stop all internal clocks except SYNCLK (default = 0).
CFR[1]: SDIO Input Only
When CFR[1] = 0 (default), the SDIO pin has bidirectional
operation (2-wire serial programming mode).
When CFR[1] = 1, the serial data I/O pin (SDIO) is configured
as an input only pin (3-wire serial programming mode).
CFR[0]: LSB First
This bit has an effect on device operation only if the I/O port is
configured as a serial port.
When CFR[0] = 0 (default), MSB first format is active.
The AD9858 also provides a 14-bit phase offset word (POW)
for each profile. The value in this register is a 14-bit unsigned
number (POW) that represents the proportional (PO/214) phase
offset to be added to the instantaneous phase value. This allows
the phase of the output signal to be adjusted in fine increments
of phase (about 0.022°). It is possible to update the FTW and
POW of any profile while the AD9858 is operating at the
frequency specified by another profile and then switch to the
profile containing the newly loaded frequency. Changing the
current profile updates both parameters so care must be taken
to ensure that no unwanted parameter changes take place.
It is also possible to repeatedly write a new frequency into the
FTW register of a selected profile and to jump to the new
frequency by strobing the frequency update pin (FUD). This
allows hopping to arbitrary frequencies but is limited in the rate
at which this can be accomplished by the speed of the I/O port
(100 MHz in parallel mode) and the necessity to transfer several
bytes of data for each new frequency tuning word. This can be
accomplished rapidly enough for many applications.
Phase Offset Control
A 14-bit phase offset (θ) can be added to the output of the phase
accumulator by means of the phase offset words stored in the
memory registers. This feature provides the user with three
different methods of phase control.
When CFR[0] = 1, LSB first format is active.
OTHER REGISTERS
Delta Frequency Tuning Word (DFTW)
The DFTW register comprises four bytes. The contents of the
DFTW are applied to the input of the frequency accumulator.
When the device is in the frequency sweep mode, the output of
the frequency accumulator is added to the frequency tuning
word and fed to the phase accumulator. This provides the
frequency sweep capability of the AD9858.
Delta Frequency Ramp Rate Word (DFRRW)
The DFRRW comprises two bytes. The DFRRW is a 16-bit
unsigned number used to clock the frequency accumulator.
USER PROFILE REGISTERS
The user profile registers are comprised of the four frequency
tuning words and four phase offset words. Each pair of
frequency and phase registers forms a configurable user profile,
selected by the user profile pins.
User Profiles
The AD9858 features four user profiles (0 to 3) that are selected
by the profile select pins (PS0 and PS1) on the device. Each
profile has its own frequency tuning word. This allows the user
to load a different frequency tuning word into each profile,
which can then be selected as desired by the profile select pins.
This makes it possible to hop among the different frequencies at
rates up to 1/16 of the SYSCLK while in single-tone mode.
The first method is a static phase adjustment, where a fixed phase
offset is loaded into the appropriate phase offset register and left
unchanged. The result is that the output signal is offset by a
constant angle relative to the nominal signal. This allows the user to
phase align the DDS output with an external signal, if necessary.
The second method of phase control is where the user regularly
updates the appropriate phase offset register via the I/O port. By
properly modifying the phase offset as a function of time, the
user can implement a phase modulated output signal. The rate
at which phase modulation can be performed is limited by both
the speed of the I/O port and the frequency of SYSCLK.
The third method of phase control involves the profile registers,
in which the user loads up to four different phase offset values
into the appropriate profiles. The user can then select among
the four preloaded phase offset values via the AD9858 profile
select pins. Therefore, the phase changes are accomplished by
driving the hardware pins rather than writing to the I/O port,
thereby avoiding the speed limitation imposed by the I/O port.
However, this method is restricted to only four phase offset
values (one phase offset value per profile). Each profile has an
associated frequency and phase value. Changing the current
profile updates both parameters; therefore, care must be taken
to ensure that no unwanted parameter changes take place.
The phase offset value is routed through a unit delay (z–1) block.
This is done to ensure that updates of the phase offset values
exhibit the same amount of latency as updates of the frequency
tuning word.
Rev. C | Page 25 of 32
AD9858
Profile Selection
A profile consists of a specific group of memory registers (see
Table 6). In the AD9858, each profile contains a 32-bit frequency
tuning word and a 14-bit phase offset word. Each profile is
selectable via two external profile select pins (PS0 and PS1), as
defined in Table 12. The specific mapping of registers to profiles is
detailed in the Register Bit Descriptions section. The user should
be aware that selection of a profile is internally synchronized
with DDS CLK using the SYNCLK timing. That is, SYNCLK is
used to synchronize the assertion of the profile select pins (PS0
and PS1). Therefore, the PS0 and PS1 pins must be set up and
held around the rising edge of SYNCLK.
The profiles are available to the user to provide rapid changing
of device parameters via external hardware, which alleviates the
speed limitations imposed by the I/O port. For example, the user
might preprogram the four phase offset registers with values that
correspond to phase increments of 90°. By controlling the PS0 and
PS1 pins, the user can implement π/2 phase modulation. The data
modulation rate is much higher than that possible by repeatedly
reloading a single phase offset register via the I/O port.
Table 12.
PS1
0
0
1
1
PS0
0
1
0
1
Profile
0
1
2
3
Rev. C | Page 26 of 32
AD9858
APPLICATIONS INFORMATION
FREQUENCY
TUNING WORD
32
fREF
DC TO 400MHz
10
DDS
1GSPS
DAC
DC TO 150MHz
PHASE/
FREQUENCY
DETECTOR
150MHz
DIVIDER
1/2/4
FILTER
VCO
CHARGE PUMP
0.5mA TO 2mA
(0.5mA STEPS)
DDS/DAC
CLOCK 1000MHz
LOOP
FILTER
2GHz ±150MHz
ANALOG
MIXER
DIVIDER
1/2
AD9858
2GHz
FILTER
2GHz
03166-040
FIXED
LOOP
(LO1)
Figure 37. DDS Synthesizer Translation Loop Oscillator (Implemented in Translation Loop Evaluation Board)
FREQUENCY
TUNING WORD
DDS
1GSPS
10
DAC
FILTER
DC TO 150MHz
PHASE/
FREQUENCY
DETECTOR
150MHz
DIVIDER
1/2/4
CHARGE PUMP
0.5mA TO 2mA
(0.5mA STEPS)
VCO
LOOP
FILTER
F = M × fREF
DIVIDER
DDS/DAC CLOCK
Figure 38. DDS Synthesizer Single-Loop PLL Up-Conversion
150MHz
REFERENCE
DIVIDER
1/2/4
PHASE/
FREQUENCY
DETECTOR
150MHz
CHARGE PUMP
0.5mA TO 2mA
(0.5mA STEPS)
VCO
LOOP
FILTER
AD9858
150MHz
FILTER
DAC
DDS
1GSPS
1000
MHz
DIVIDER
1/2
2GHz MAX
32
FREQUENCY
TUNING WORD
Figure 39. DDS Synthesizer AD9858 as Fractional N Synthesizer (Implemented in Fractional Divide Evaluation Board)
Rev. C | Page 27 of 32
03166-041
AD9858
03166-042
32
fREF
DC TO 400MHz
AD9858
EVALUATION BOARDS
The AD9858 has three different evaluation board designs. The
first design is the traditional DDS evaluation board (see Figure 38).
In this design, the DDS is clocked and the output is taken
directly from the DAC. The analog mixer and PLL blocks are
made available for separate evaluation.
The second design is a fractional divide loop (see Figure 39).
This evaluation board was designed to incorporate the DDS, the
phase frequency detector, and the charge pump. In this
application, the DDS is used in a PLL loop. Unlike a fixed
divider used in traditional PLL loops, the output signal is
divided and fed back to the phase frequency detector by the
DDS. To do this, the output signal of the PLL loop is fed to the
DDS as REFCLK. The DDS is programmed to match the
reference input frequency. Because the DDS output frequency
can take on 232 potential values between 0 Hz and one-half of
the PLL loop output frequency, this enables frequency
resolution on the order of 470 MHz, assuming a PLL loop
output frequency of 2 GHz.
The third design is a translation loop or offset loop (see Figure 37).
In this design, the analog mixer is incorporated into the feedback
path of the loop. This allows direct up-conversion to the
transmission frequency.
The three evaluation boards have separate schematics, BOMs, and
instructions. See www.analog.com/dds for more information.
Table 13. Evaluation Boards for the AD9858
Model
AD9858/PCBZ
AD9858/FDPCB
AD9858/TLPCBZ
Rev. C | Page 28 of 32
Description
AD9858 Frequency Synthesizer Board
AD9858 Fractional Divide Loop Frequency
Synthesizer Board
AD9858 Translation Loop Frequency
Synthesizer Board
AD9858
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
SEATING
PLANE
76
76
75
100
1
75
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.27
0.22
0.17
0.50 BSC
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
021809-A
51
25
26
0.20
0.09
Figure 40. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
WARNING
The TQFP_EP (thermal slug) must be attached to the ground plane or some other large metal mass for thermal transfer. Failure to do so
may cause excessive die temperature rise and damage to the device.
ORDERING GUIDE
Model
AD9858BSV
AD9858BSVZ 1
AD9858/PCBZ1
AD9858/FDPCB
AD9858/TLPCBZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
100-Lead TQFP_EP
100-Lead TQFP_EP
Generic Evaluation Board
Fractional Divide Evaluation Board
Translation Loop Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
Package Option
SV-100-1
SV-100-1
AD9858
NOTES
Rev. C | Page 30 of 32
AD9858
NOTES
Rev. C | Page 31 of 32
AD9858
NOTES
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03166-0-2/09(C)
Rev. C | Page 32 of 32