TI GTLP2034 8-bit lvttl-to-gtlp adjustable-edge-rate registered transceiver with split lvttl port and feedback path Datasheet

SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Open-Drain Outputs
(100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGG OR DGV PACKAGE
(TOP VIEW)
IMODE1
AI1
AO1
GND
AI2
AO2
VCC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
VCC
AO7
AI7
GND
AO8
AI8
OMODE0
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
IMODE0
BIAS VCC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
VCC
B7
LOOPBACK
GND
B8
VREF
OMODE1
description
The SN74GTLP2034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP
and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of
data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and
diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11 Ω.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP2034 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistor
and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
GQL PACKAGE
(TOP VIEW)
1
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
IMODE1
NC
NC
NC
NC
IMODE0
B
B
AO1
AI1
GND
GND
BIAS VCC
B1
C
AO2
AI2
OEAB
B2
AO3
AI3
VCC
GND
ERC
D
GND
OEAB
B3
E
AO4
AI4
CLKAB/LEAB
B4
F
AO5
AI5
CLKBA/LEBA
B5
G
AO6
AI6
GND
GND
OEBA
B6
LOOPBACK
B7
VREF
NC
OMODE1
C
D
E
F
G
H
AO7
AI7
H
J
AO8
AI8
VCC
GND
VCC
GND
J
K
OMODE0
NC
NC
NC
K
2
2
NC = No internal connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B8
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
ORDERING INFORMATION
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74GTLP2034DGGR
GTLP2034
TVSOP – DGV
Tape and reel
SN74GTLP2034DGVR
GT2034
VFBGA – GQL
Tape and reel
SN74GTLP2034GQLR
GR034
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLP2034 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type latches
and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data transmission
is true, with AI data going to the B port and B data going to AO. The split LVTTL AI and AO provides a feedback
path for control and diagnostics monitoring.
The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,
OMODE1 and OMODE0 for A to B) inputs as a buffer, D-type flip-flop, or D-type latch. When configured in the
buffer mode, the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge
of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve as
active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element is the B-to-A input.
The AO enable/disable control is provided by OEBA. When OEBA is low or when VCC is less than 1.5 V, AO
is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).
The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or VCC is less than 1.5 V, the B port
is inactive. If OEAB is high and OEAB is low, the B port is active.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO) or inactive (B port) states.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
Function Tables
FUNCTION/MODE
INPUTS
OEBA
OEAB
OEAB
OMODE1
OMODE0
IMODE1
IMODE0
LOOPBACK
L
L
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
H
L
L
L
X
X
X
X
H
L
L
H
X
X
X
X
H
L
H
X
X
X
X
H
L
X
X
X
L
L
L
H
X
H
X
X
L
L
L
H
L
X
X
X
L
H
L
H
X
H
X
X
L
H
L
H
L
X
X
X
H
X
L
H
X
H
X
X
H
X
L
H
L
X
X
X
L
L
H
H
X
H
X
X
L
L
H
H
L
X
X
X
L
H
H
H
X
H
X
X
L
H
H
H
L
X
X
X
H
X
H
H
X
H
X
X
H
X
H
H
H
L
X
X
X
X
L
OEAB
OEAB
AO
L
X
X
Z
H
X
X
Active
X
L
L
Z
X
L
H
Z
X
H
L
Active
X
H
H
Z
B
BUFFER
OUTPUT
L
L
H
LATCH
INPUTS
CLK/LE
4
DATA
OUTPUT
H
L
L
H
H
H
L
X
Q0
POST OFFICE BOX 655303
Isolation
Flip-flop
Latch
OEBA
H
Z
AI to B
OUTPUTS
INPUT
MODE
Buffer
ENABLE/DISABLE
INPUTS
OUTPUT
• DALLAS, TEXAS 75265
B to
t AO
B ff
Buffer
B to
t AO
Fli fl
Flip-flop
B to
t AO
L t h
Latch
AI to AO
Buffer
AI to AO
Flip flop
Flip-flop
AI to AO
Latch
AI to B, B to AO
Transparent with
feedback path
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
Function Tables (Continued)
LOOPBACK
LOOPBACK
Q†
L
B port
H
Point P‡
† Q is the input to the B-to-A
logic element.
‡ P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
MODE1
SELECTED LOGIC
ELEMENT
MODE0
L
L
Buffer
L
H
Flip-flop
H
X
Latch
FLIP-FLOP
INPUTS
CLK/ LE
DATA
L
X
OUTPUT
Q0
↑
L
L
↑
H
H
B-PORT EDGE-RATE CONTROL (ERC)
INPUT
ERC
LOGIC LEVEL
OUTPUT
B-PORT
EDGE RATE
H
Slow
L
Fast
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
functional block diagram
VREF
26
42
ERC
44
OEAB
OEAB
OMODE0
41
24
25
OMODE1
38
CLKAB/LEAB
Transceiver
1D
C1
46
B1
AI1
2
P
1D
C1
IMODE0
48
1
IMODE1
35
CLKBA/LEBA
1D
C1
3
AO1
Q
1D
OEBA
32
C1
One of Eight Channels
LOOPBACK
29
Pin numbers shown are for the DGG and DGV packages.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1): AI port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): AO port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, IO: AO port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
recommended operating conditions (see Notes 4 through 7)
VCC,
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
High-level output current
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
B port
Except B port and VREF
B port
Except B port
VREF+0.05
2
B port
V
V
V
VREF–0.05
0.8
Except B port
V
V
–18
mA
AO
–24
mA
AO
24
B port
100
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3
V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable but, generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
VIK
VOH
AO
TEST CONDITIONS
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
II = –18 mA
IOH = –100 µA
VCC = 3
3.15
15 V
IOH = –12 mA
IOH = –24 mA
VCC = 3.15 V to 3.45 V,
AO
VCC = 3
3.15
15 V
VOL
B port
II‡
IOZ‡
ICC
MIN
VCC = 3.15 V
TYP†
MAX
UNIT
–1.2
V
VCC–0.2
2.4
V
2
IOL = 100 µA
IOL = 12 mA
0.2
IOL = 24 mA
IOL = 10 mA
0.5
0.4
0.2
IOL = 64 mA
IOL = 100 mA
0.55
0.4
AI and
control inputs
VCC = 3.45 V,
VI = 0 or 5.5 V
±10
AO
VCC = 3.45 V,
VO = 0 to 5.5 V
±10
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
±10
AO or B port
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
VO = 0 to 2.3 V
Outputs high
AI
µA
µA
40
Outputs low
40
Outputs disabled
40
VCC = 3.45 V, One AI or control input at VCC – 0.6 V,
Other AI or control inputs at VCC or GND
∆ICC§
V
1.5
mA
mA
3.5
4.5
3.5
5.5
5
6
pF
Cio
B port
8.5
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
10
pF
Ci
Control inputs
Co
AO
VI = 3.15
3 15 V or 0
VO = 3.15 V or 0
VO = 1.5 V or 0
pF
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
10
µA
OEBA = VCC
±30
µA
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OEBA = VCC
±30
µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
Ioff
IOZPU
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
IOZPD
±30
ICC
(BIAS VCC)
VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
VCC = 0 to 3.15 V
BIAS VCC = 3
3.15
15 V to 3
3.45
45 V
V, VO (B port) = 0 to 1.5
15V
VCC = 3.15 V to 3.45 V
VO
IO
VCC = 0,
VCC = 0,
0.95
BIAS VCC = 3.3 V,
BIAS VCC = 3.15 V to 3.45 V,
POST OFFICE BOX 655303
IO = 0
VO (B port) = 0.6 V
• DALLAS, TEXAS 75265
–1
MAX
UNIT
10
µA
±30
µA
±30
µA
5
mA
10
µA
1.05
V
µA
9
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN
fclock
tw
tsu
th
10
Clock frequency
Pulse duration
Setup time
Hold time
POST OFFICE BOX 655303
CLKAB/LEAB or CLKBA/LEBA
2.8
AI before CLKAB↑
1.1
AI before CLKBA↑
1.4
B before CLKBA↑
1.3
AI before LEAB↓
1.3
AI before LEBA↓
2.1
B before LEBA↓
2.2
AI after CLKAB↑
0.3
AI after CLKBA↑
0.2
B after CLKBA↑
0.2
AI after LEAB↓
0.3
AI after LEBA↓
0
B after LEBA↓
0
• DALLAS, TEXAS 75265
MAX
UNIT
175
MHz
ns
ns
ns
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
MIN
TYP‡
MAX
175
AI
(buffer)
B
Sl
Slow
AI
(buffer)
B
F t
Fast
B
(buffer)
AO
–
LEAB
(latch mode)
B
Slo
Slow
LEAB
(latch mode)
B
F t
Fast
LEAB
(latch mode)
AO
–
LEBA
(latch mode)
AO
–
OEAB
B
Sl
Slow
OEAB
B
Fast
OEAB
B
Sl
Slow
OEAB
B
F t
Fast
OEBA
AO
–
OEBA
AO
–
CLKAB
(flip-flop mode)
B
Sl
Slow
CLKAB
(flip-flop mode)
B
F t
Fast
CLKAB
(flip-flop mode)
AO
–
CLKBA
(flip-flop mode)
AO
–
OMODE
B
Sl
Slow
OMODE
B
F t
Fast
IMODE
AO
–
tPHL
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
3
7.1
3
7
2
5.6
2
5.7
1
5.4
1
4.8
4.2
8.5
3.2
7.3
3.2
7.1
2.8
6.3
2
6.6
1.8
5.8
1
5.3
1
4.5
3.8
7.5
3.1
7
2.5
6
2.5
6
3.5
7.5
3
7.2
2.5
6
2.5
6
1
4.7
1
3.4
1
5.2
1
4.9
4.4
8.6
3.6
8
3.2
7.1
3.1
6.8
2
6.9
1.8
6.4
1
5.6
1
4.9
3.8
8.7
3.2
8.2
2.7
7
2.7
7
1
5.6
1
4.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
LOOPBACK
AO
–
tPLH
tPHL
AI
(loopback high)
AO
–
tr
Rise time,
time B-port
B port outputs (20% to 80%)
MIN
MAX
2.5
5.5
2
4.7
1
5.3
1
4.9
Slow
2.8
Fast
1.5
Rise time, AO (10% to 90%)
tf
TYP‡
UNIT
ns
ns
ns
3.5
Fall time
time, B
B-port
port outputs (80% to 20%)
Slow
3
Fast
1.8
Fall time, AO (90% to 10%)
ns
1.5
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)§
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tsk(LH)¶
tsk(HL)¶
AI
B
Slow
tsk(LH)¶
tsk(HL)¶
AI
tsk(LH)¶
tsk(HL)¶
CLKAB/LEAB
tsk(LH)¶
tsk(HL)¶
CLKAB/LEAB
B
AI
B
B
B
tsk(t)
k(t)¶
CLKAB/LEAB
B
Fast
Slow
Fast
MIN
TYP‡
MAX
0.5
1
0.5
1
0.4
0.9
0.4
0.9
0.5
1
0.5
1
0.4
0.9
0.4
0.9
Slow
1.4
2
Fast
0.6
1.4
Slow
1.8
2.5
Fast
0.9
1.8
UNIT
ns
ns
ns
ns
ns
† Slow (ERC = L) and Fast (ERC = H)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
§ Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
¶ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
12.5 Ω
S1
Open
6V
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
From Output
Under Test
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR A OUTPUTS
tw
3V
3V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu
th
VOH
Data
Input
VM
VM
0V
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOH
Output
1V
1V
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to B port)
1V
1V
0V
tPLH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
Input
Output
Control
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to AO)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application is probably a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be closely approximated to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
.25”
1”
1”
.25”
22 Ω
22 Ω
1.5 V
ZO = 50 Ω
11 Ω
Conn.
1”
Conn.
1”
Conn.
1”
Conn.
From Output
Under Test
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 19
Slot 20
LL = 14 nH
Test
Point
CL = 18 pF
Drvr
Slot 1
Figure 2. High-Drive Test Backplane
14
POST OFFICE BOX 655303
Figure 3. High-Drive RLC Network
• DALLAS, TEXAS 75265
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
AI
(buffer)
B
Sl
Slow
tPLH
tPHL
AI
(buffer)
B
F t
Fast
tPLH
tPHL
LEAB
(latch mode)
B
Sl
Slow
tPLH
tPHL
LEAB
(latch mode)
B
Fast
tPLH
tPHL
CLKAB
(flip-flop mode)
B
Sl
Slow
tPLH
tPHL
CLKAB
(flip-flop mode)
B
F t
Fast
tPLH
tPHL
OMODE
B
Sl
Slow
tPLH
tPHL
OMODE
B
F t
Fast
TYP‡
5.7
5.2
3.7
tr
time B-port
B port outputs (20% to 80%)
Rise time,
tf
Fall time
time, B
B-port
port outputs (80% to 20%)
4.1
5.9
5.7
4.8
4.8
5.7
6.4
4.7
5.2
5.4
6
4.5
4.9
Slow
2
Fast
1.1
Slow
3.3
Fast
2.3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
† Slow (ERC = H) and Fast (ERC = L)
‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74GTLP2034DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74GTLP2034DGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLP2034DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLP2034DGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLP2034GQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
SNPB
Level-1-240C-UNLIM
SN74GTLP2034ZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power Wireless www.ti.com/lpw
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2006, Texas Instruments Incorporated