NB3N5573 3.3 V, Crystal to 25 MHz, 100 MHz, 125 MHz and 200 MHz Dual HCSL Clock Generator www.onsemi.com Description The NB3N5573 is a precision, low phase noise clock generator that supports PCI Express and Ethernet requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal and generates a differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies. Outputs can interface with LVDS with proper termination (See Figure 4). This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16 pin package. MARKING DIAGRAM 16 16 1 TSSOP−16 DT SUFFIX CASE 948F Features • • • • • • • • • • • A L Y W G Uses 25 MHz Fundamental Mode Parallel Resonant Crystal External Loop Filter is Not Required HCSL Differential Output or LVDS with Proper Termination Four Selectable Multipliers of the Input Frequency Output Enable with Tri−State Outputs PCIe Gen1, Gen2, Gen3 Jitter Compliant Phase Noise: @ 100 MHz Offset Noise Power 100 Hz −109.4 dBc 1 kHz −127.8 dBc 10 kHz −136.2 dBc 100 kHz −138.8 dBc 1 MHz −138.2 dBc 10 MHz −161.4 dBc 20 MHz −163.00 dBc Typical Period Jitter RMS of 1.5 ps Operating Range 3.3 V ±10% Industrial Temperature Range −40°C to +85°C These are Pb−Free Devices 1 NB3N 5573 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. VDD X1/CLK 25 MHz Clock or Crystal Clock Buffer Crystal Oscillator CLK0 Charge Pump Phase Detector HSCL Output VCO X2 HSCL Output BM CLK0 CLK1 CLK1 GND S0 S1 OE IREF Figure 1. NB3N5573 Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 10 1 Publication Order Number: NB3N5573/D NB3N5573 S0 1 16 VDD S1 2 15 CLK0 NC 3 14 X1/CLK 4 13 GND X2 5 12 VDD OE 6 11 CLK1 GND 7 10 NC 8 9 CLK0 CLK1 IREF Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O 1 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDD. See output select table 2 for details. Description 2 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDD. See output select Table 2 for details. 12, 16 VDD Power Supply 4 X1/CLK Input Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock. 5 X2 Input Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. Output enable tri−states output when connected to GND. Internal pullup resistor to VDD. Positive supply voltage pins are connected to +3.3 V supply voltage. 6 OE Input 7, 13 GND Power Supply 9 IREF Output 11 CLK1 HCSL or LVDS Output Noninverted clock output. (For LVDS levels see Figure 4) 10 CLK1 HCSL or LVDS Output Inverted clock output. (For LVDS levels see Figure 4) 15 CLK0 HCSL or LVDS Output Noninverted clock output. (For LVDS levels see Figure 4) 14 CLK0 HCSL or LVDS Output Inverted clock output. (For LVDS levels see Figure 4) 3, 8 NC Ground 0 V. These pins provide GND return path for the devices. Output current reference pin. Precision resistor (typ. 475 W) is connected to set the output current. Do not connect Recommended Crystal Parameters Table 2. OUTPUT FREQUENCY SELECT TABLE WITH 25MHz CRYSTAL S1* S0* CLK Multiplier fCLKout (MHz) L L 1x 25 L H 4x 100 H L 5x 125 H H 8x 200 Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25 °C Temperature Stability Aging Drive Level *Pins S1 and S0 default high when left open. www.onsemi.com 2 Fundamental AT−Cut 25 MHz 16−20 pF 7 pF Max 50 W Max ±20 ppm ±30 ppm ±20 ppm 100 mW Max NB3N5573 Table 3. ATTRIBUTES Characteristic ESD Protection Value Human Body Model > 2 kV RPU − OE, S0 and S1 Pull−up Resistor 100 kW Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 7623 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Unit 4.6 V −0.5 V to VDD+0.5 V V VDD Positive Power Supply GND = 0 V VI Input Voltage (VIN) GND = 0 V TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP–16 TSSOP–16 138 108 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) TSSOP−16 33 to 36 °C/W Tsol Wave Solder 265 °C GND v VI v VDD Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C, Note 4) Symbol Characteristic Min Typ Max Unit 2.97 3.3 3.63 V 120 135 mA VDD Power Supply Voltage IDD Power Supply Current IDDOE Power Supply Current when OE is Set Low 65 mA VIH Input HIGH Voltage (X/CLK, S0, S1, and OE) 2000 VDD + 300 mV VIL Input LOW Voltage (X/CLK, S0, S1, and OE) GND − 300 800 mV VOH Output HIGH Voltage for HCSL Output (See Figure 5) 660 700 850 mV VOL Output LOW Voltage for HCSL Output (See Figure 5) −150 0 150 mV Vcross Crossing Voltage Magnitude (Absolute) for HCSL Output 250 550 mV DVcross Change in Magnitude of Vcross for HCSL Output 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 3. www.onsemi.com 3 NB3N5573 Table 6. AC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C; Note 5) Symbol Characteristic fCLKIN Clock/Crystal Input Frequency fCLKOUT Output Clock Frequency qNOISE Phase−Noise Performance Min Max 25 25 Unit MHz 200 MHz dBc/Hz fCLKx = 200 MHz/100 MHz @ 100 Hz offset from carrier tJITTER Typ −103/−109 @ 1 kHz offset from carrier −118/−127.8 @ 10 kHz offset from carrier −122/−136.2 @ 100 kHz offset from carrier −130/−138.8 @ 1 MHz offset from carrier −132/−138.2 @ 10 MHz offset from carrier −149/−164 Period Jitter Peak−to−Peak (Note 6) fCLKx = 200 MHz 10 20 Period Jitter RMS (Note 6) fCLKx = 200 MHz 1.5 3 Cycle−Cycle RMS Jitter (Note 7) fCLKx = 200 MHz 2 5 Cycle−to−Cycle Peak to Peak Jitter (Note 7) fCLKx = 200 MHz 20 35 ps ps tJIT(F) Additive Phase RMS Jitter, Integration Range 12 kHz to 20 MHz 0.4 ps OE Output Enable/Disable Time 10 ms tDUTY_CYCLE Output Clock Duty Cycle (Measured at cross point) 45 50 55 % tR Output Risetime (Measured from 175 mV to 525 mV, Figure 5) 175 340 700 ps tF Output Falltime (Measured from 525 mV to 175 mV, Figure 5) 175 340 700 ps DtR Output Risetime Variation (Single−Ended) 125 ps DtF Output Falltime Variation (Single−Ended) 125 ps Stabilization Time Stabilization Time From Powerup VDD = 3.3 V 3.0 ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 5. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 3. 6. Sampled with 10000 cycles. 7. Sampled with 1000 cycles. www.onsemi.com 4 NB3N5573 Table 7. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS Symbol Parameter tjphPCIeG1 tjphPCIeG2 tjphPCIeG3 RMS Phase Jitter tjphQPI_SMI Typ Max Unit PCIe Gen 1 (Notes 10 and 11) Conditions (Notes 8 and 9) Min 10 86 ps (p−p) PCIe Gen 2 Lo Band 10 kHz < f < 1.5 MHz (Note 10) 0.2 3 ps (rms) PCIe Gen 2 High Band 1.5 MHz < f < Nyquist (50 MHz) (Note 10) 0.9 3.1 ps (rms) PCIe Gen 3 (PLL BW of 2−4 MHz, CDR = 10 MHz) (Note 10) 0.2 1 ps (rms) QPI & SMI (100.00 MHz or 133.33 MHz, 4.8 Gb/s, 6.4 Gb/s 12UI) (Note 12) 0.1 0.5 ps (rms) QPI & SMI (100.00 MHz, 8.0 Gb/s, 12UI) (Note 12) 0.1 0.3 ps (rms) QPI & SMI (100.00 MHz, 9.6 Gb/s, 12UI) (Note 12) 0.07 0.2 ps (rms) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Applies to all outputs. 9. Guaranteed by design and characterization, not tested in production 10. See http://www.pcisig.com for complete specs 11. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12. 12. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3. HCSL INTERFACE NB3N5573 CLK0 RL = 33.2 W Zo = 50 W RL = 33.2 W Zo = 50 W CLK0 RL = 49.9 W RL = 49.9 W RL = 49.9 W RL = 49.9 W HCSL Driver CLK1 RL = 33.2 W Zo = 50 W RL = 33.2 W Zo = 50 W CLK2 IREF RREF = 475 W Figure 3. Typical Termination for Output Driver and Device Evaluation www.onsemi.com 5 HCSL Receiver NB3N5573 LVDS COMPATIBLE INTERFACE CLK0 Zo = 50 W CLK0 Zo = 50 W 100 W 100 W RL = 150 W RL = 150 W LVDS Receiver NB3N5573 CLK1 Zo = 50 W 100 W 100 W Zo = 50 W CLK2 IREF RL = 150 W RL = 150 W LVDS Device Load RREF = 475 W Figure 4. Typical Termination for LVDS Device Load 700 mV 525 mV 525 mV 175 mV 175 mV 0 mV tR 340 ps 340 ps tF Figure 5. HCSL Output Parameter Characteristics ORDERING INFORMATION Package Shipping† NB3N5573DTG TSSOP−16 (Pb−Free) 96 Units / Rail NB3N5573DTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 6 NB3N5573 PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB3N5573 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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