AD ADUM3220BRZ Isolated, 4 a dual-channel gate driver Datasheet

Isolated, 4 A Dual-Channel Gate Driver
ADuM3220/ADuM3221
Data Sheet
FEATURES
GENERAL DESCRIPTION
4 A peak output current
Precise timing characteristics
60 ns maximum isolator and driver propagation delay
5 ns maximum channel-to-channel matching
High junction temperature operation: 125°C
3.3 V to 5 V input logic
4.5 V to 18 V output drive
UVLO at 2.5 V VDD1
ADuM3220A/ADuM3221A UVLO at 4.1 V VDD2
ADuM3220B/ADuM3221B UVLO at 7.0 V VDD2
Thermal shutdown protection at >150°C
Output shoot-through logic protection on the ADuM3220
Default low output
High frequency operation: dc to 1 MHz
CMOS input logic levels
High common-mode transient immunity: >25 kV/μs
Enhanced system-level ESD performance per IEC 61000-4-x
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
Small footprint and low profile
Narrow body, RoHS-compliant, 8-lead SOIC
5 mm × 6 mm × 1.6 mm
Qualified for automotive applications
The ADuM3220/ADuM32211 are isolated, 4 A dual-channel gate
drivers based on the Analog Devices, Inc., iCoupler® technology.
Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance
characteristics superior to the alternatives, such as the combination
of pulse transformers and gate drivers.
The ADuM3220/ADuM3221 provide digital isolation in two
independent isolation channels. They have a maximum propagation
delay of 60 ns and 5 ns channel-to-channel matching. In comparison
to gate drivers that employ high voltage level translation methodologies, the ADuM3220/ADuM3221 offer the benefit of true,
galvanic isolation between the input and each output, enabling
voltage translation across the isolation barrier. The ADuM3220
has shoot-through protection logic, which prevents both outputs
from being on at the same time, whereas the ADuM3221 allows
both outputs to be on at the same time. Both parts offer a default
output low characteristic as required for gate drive applications.
The ADuM3220/ADuM3221 operate with an input supply voltage
ranging from 3.0 V to 5.5 V, providing compatibility with lower
voltage systems. The outputs of the ADuM3220A/ADuM3221A
can be operated at supply voltages from 4.5 V to 18 V. The outputs
of the ADuM3220B/ADuM3221B can be operated at supply
voltages from 7.6 V to 18 V.
The junction temperature of the ADuM3220/ADuM3221 is
specified from −40°C to +125°C.
APPLICATIONS
Isolated synchronous dc-to-dc converters
MOSFET/IGBT gate drivers
ADuM3220
8
VIA 2
ENCODE
DECODE
AND
LEVEL
SHIFT
VIB 3
ENCODE
DECODE
AND
LEVEL
SHIFT
GND1 4
VDD2
7
VOA
VIA 2
6
VOB
VIB 3
5
GND2
Figure 1.
1
ADuM3221
8
VDD2
ENCODE
DECODE
AND
LEVEL
SHIFT
7
VOA
ENCODE
DECODE
AND
LEVEL
SHIFT
6
VOB
5
GND2
VDD1 1
08994-001
VDD1 1
GND1 4
08994-102
FUNCTIONAL BLOCK DIAGRAMS
Figure 2.
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239.
Rev. C
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ADuM3220/ADuM3221
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................8
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................9
General Description ......................................................................... 1
Applications Information .............................................................. 12
Functional Block Diagrams ............................................................. 1
PC Board Layout ........................................................................ 12
Revision History ............................................................................... 2
Propagation Delay-Related Parameters................................... 12
Specifications..................................................................................... 3
Thermal Limitations and Switch Load Characteristics ......... 12
Electrical Characteristics—5 V Operation................................ 3
Output Load Characteristics ..................................................... 12
Electrical Characteristics—3.3 V Operation ............................ 4
DC Correctness and Magnetic Field Immunity.......................... 13
Package Characteristics ............................................................... 5
Power Consumption .................................................................. 14
Regulatory Information ............................................................... 5
Insulation Lifetime ..................................................................... 14
Insulation and Safety-Related Specifications ............................ 5
Outline Dimensions ....................................................................... 15
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Ordering Guide .......................................................................... 15
Automotive Products ................................................................. 15
Recommended Operating Conditions ...................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
REVISION HISTORY
10/12—Rev. B to Rev. C
Changes to Features Section and General Description Section .... 1
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Added Output Pulsed Source Resistance Parameter
and Output Pulsed Sink Resistance Parameter to Table 1 .......... 3
Added Output Pulsed Source Resistance Parameter
and Output Pulsed Sink Resistance Parameter to Table 2 .......... 4
Added IC Junction-to-Ambient Thermal Resistance
Parameter to Table 3 ......................................................................... 5
Changes to Introductory Sentence of Regulatory
Information Section ......................................................................... 5
Changed Supply Voltage Ranges Parameter in Table 8 ............... 7
Changes to Table 9 ............................................................................ 7
Changes to Table 11 and Table 12 .................................................. 8
Added Figure 17 and Figure 18; Renumbered Sequentially ..... 11
Moved Figure 21 ............................................................................. 12
Changes to Power Consumption Section and Insulation
Lifetime Section .............................................................................. 14
Changes to Ordering Guide .......................................................... 15
Added Automotive Products Section........................................... 15
3/11—Rev. A to Rev. B
Added ADuM3220BRZ and ADuM3221BRZ models.... Universal
Changes to Features Section and General Description Section ..1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Added Figure 17 and Figure 18; Renumbered Sequentially ..... 11
Changes to Ordering Guide .......................................................... 14
1/11—Rev. 0 to Rev. A
Added ADuM3221 ............................................................. Universal
Changes to Features Section and General Description Section ..1
Added Figure 2; Renumbered Sequentially ...................................1
Changes to Endnote 3, Endnote 4, and Endnote 5, Table 1 .........3
Changes to Endnote 3, Endnote 4, and Endnote 5, Table 2 .........4
Changes to Table 8.............................................................................7
Changes to Figure 4, Table 10, and Table 11 ..................................8
Added Table 12; Renumbered Sequentially ...................................8
Added Figure 8...................................................................................9
Change to Figure 19 and DC Correctness and Magnetic Field
Immunity Section ........................................................................... 12
Changes to Ordering Guide .......................................................... 14
4/10—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
ADuM3220/ADuM3221
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 10 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels, Quiescent
Total Supply Current, Two Channels 1
DC to 1 MHz
VDD1 Supply Current
VDD2 Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD2 Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
ADuM3220B/ADuM3221B
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current 2
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width 3
Data Rate 4
Propagation Delay 5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
Symbol
Typ
Max
Unit
IDDI(Q)
IDDO(Q)
1.2
4.7
1.5
10
mA
mA
IDD1(Q)
IDD2(Q)
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
1.4
11
+0.01
1.7
17
+10
mA
mA
µA
V
V
V
V
VDD2UV+
VDD2UV−
VDD2UVH
Min
−10
0.7 × VDD1
0.3 × VDD1
VDD2 − 0.1
3.2
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC)
ROA, ROB
ROA, ROB
2.0
0.3
0.3
PW
50
tDLH, tDHL
tDLH, tDHL
tPSK
tPSKCD
tPSKCD
tR/tF
tR/tF
IDDI(D)
IDDO(D)
fr
6.0
35
36
14
14
VDD2
0.0
0.15
4.1
3.7
0.4
4.4
V
V
V
7.0
6.5
0.5
4.0
1.3
0.9
7.5
V
V
V
A
Ω
Ω
45
50
1
1
20
22
0.05
1.5
1.2
1
3.0
3.0
1
60
68
12
5
7
25
28
ns
MHz
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
Test Conditions/Comments
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0 V ≤ VIA, VIB ≤ VDD1
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
VDD2 = 10 V
VDD2 = 10 V
VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
VDD2 = 10 V
VDD2 = 10 V
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency.
2
Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
6
tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. C | Page 3 of 16
ADuM3220/ADuM3221
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching
specifications are tested with CMOS signal levels.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels,
Quiescent
Total Supply Current, Two Channels 1
DC to 1 MHz
VDD1 Supply Current
VDD2 Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD2 Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
ADuM3220B/ADuM3221B
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current 2
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width 3
Data Rate 4
Propagation Delay 5
Propagation Delay Skew 6
Channel-to-Channel Matching 7
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
Symbol
Typ
Max
Unit
IDDI(Q)
IDDO(Q)
0.7
4.7
1.0
10
mA
mA
IDD1(Q)
IDD2(Q)
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
0.8
11
+0.01
1.0
17
+10
mA
mA
µA
V
V
V
V
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC)
ROA, ROB
ROA, ROB
PW
tDLH, tDHL
tDLH, tDHL
tPSK
tPSKCD
tPSKCD
tR/tF
tR/tF
IDDI(D)
IDDO(D)
fr
Min
−10
0.7 × VDD1
0.3 × VDD1
VDD2 − 0.1
3.2
6.0
2.0
0.3
0.3
VDD2
0.0
0.15
4.1
3.7
0.4
4.4
V
V
V
7.0
6.5
0.5
4.0
1.3
0.9
7.5
V
V
V
A
Ω
Ω
3.0
3.0
50
36
37
14
14
48
53
1
1
20
22
0.025
1.5
1.1
1
1
62
72
12
5
7
25
28
ns
MHz
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
Test Conditions/Comments
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0 V ≤ VIA, VIB ≤ VDD1
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
VDD2 = 10 V
VDD2 = 10 V
VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
VDD2 = 10 V
VDD2 = 10 V
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency.
2
Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
6
tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. C | Page 4 of 16
Data Sheet
ADuM3220/ADuM3221
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance
IC Junction-to-Case Thermal Resistance, Side 1
Symbol
RI-O
CI-O
CI
θJCI
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
41
°C/W
IC Junction-to-Ambient Thermal Resistance
θJA
85
°C/W
1
Min
Typ
1012
1.0
4.0
46
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center
of package underside
Thermocouple located at center
of package underside
Thermocouple located at center
of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM3220/ADuM3221 are approved by the organizations listed in Table 4.
Table 4.
UL
Recognized Under UL 1577
Component Recognition
Program 1
Single/Basic 2500 V rms
Isolation Voltage
File E214100
1
2
CSA
Approved under CSA Component Acceptance Notice #5A
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage
Functional insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
File 205078
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection
limit = 5 µA).
In accordance with DIN V VDE V 0884-10, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial
discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
2500
4.90 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
4.01 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>175
IIIa
mm
V
Rev. C | Page 5 of 16
Test Conditions/Comments
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM3220/ADuM3221
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 6.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Tests Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
896
672
V peak
V peak
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 3)
VTR
4000
V peak
TS
IS1
IS2
RS
150
160
47
>109
°C
mA
mA
Ω
VIO = 500 V
RECOMMENDED OPERATING CONDITIONS
200
180
SAFETY-LIMITING CURRENT (mA)
Symbol
Table 7.
160
Parameter
Operating Junction
Temperature
Supply Voltages 1
140
SIDE 1
120
100
80
60
SIDE 2
40
0
0
50
100
150
CASE TEMPERATURE (°C)
200
08994-002
20
Figure 3. Thermal Derating Curve; Dependence of Safety-Limiting Values
on Case Temperature, per DIN V VDE V 0884-10 (Safety-Limiting Current
Is Defined as the Average Current at Maximum VDD)
VDD1 Rise Time
Common-Mode Transient
Immunity, Input to Output
Input Signal Rise and Fall
Times
1
Symbol
TJ
Min
−40
Max
+125
Unit
°C
VDD1
VDD2
tVDD1
3.0
4.5
5.5
18
1
+25
V
V
V/µs
kV/µs
1
ms
−25
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information about immunity to
external magnetic fields.
Rev. C | Page 6 of 16
Data Sheet
ADuM3220/ADuM3221
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9. Maximum Continuous Working Voltage1
Table 8.
Parameter
Storage Temperature (TST)
Operating Temperature (TJ)
Supply Voltage Ranges1
VDD1
VDD2
Input Voltage Range (VIA, VIB)1, 2
Output Voltage Range (VOA, VOB)1, 2
Average Output Current per Pin (IO)3
Common-Mode Transients,
(CMH, CML)4
Rating
−55°C to +150°C
−40°C to +150°C
Parameter
AC Bipolar Voltage2
AC Unipolar Voltage3
DC Voltage4
−0.5 V to +7.0 V
−0.5 V to +20 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−23 mA to +23 mA
−100 kV/µs to +100 kV/µs
1
Max
565
1131
1131
Unit
V peak
V peak
V peak
Constraint
50-year minimum lifetime
50-year minimum lifetime
50-year minimum lifetime
Refers to the continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.
2
See Figure 24.
3
See Figure 25.
4
See Figure 26.
ESD CAUTION
1
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of
a given channel, respectively.
3
See Figure 3 for information about maximum allowable current for various
temperatures.
4
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latch-up
or permanent damage.
2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 16
ADuM3220/ADuM3221
Data Sheet
VDD1 1
VIA 2
VIB 3
GND1 4
ADuM3220/
ADuM3221
TOP VIEW
(Not to Scale)
8
VDD2
7
VOA
6
VOB
5
GND2
08994-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
VIA
VIB
GND1
GND2
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Logic Input A.
Logic Input B.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 4.5 V to 18 V.
Table 11. Truth Table, ADuM3220 (Positive Logic)1
VIA Input
L
L
H
H
X
VIB Input
L
H
L
H
X
VDD1 State
Powered
Powered
Powered
Powered
Unpowered
VDD2 State
Powered
Powered
Powered
Powered
Powered
VOA Output
L
L
H
L
L
VOB Output
L
H
L
L
L
X
X
Powered
Unpowered
L
L
1
Notes
Outputs return to the input state within 1 µs of
VDD1 power restoration.
Outputs return to the input state within 1 µs of
VDD2 power restoration.
X = don’t care, L = low, H = high.
Table 12. Truth Table, ADuM3221 (Positive Logic)1
VIA Input
L
L
H
H
X
VIB Input
L
H
L
H
X
VDD1 State
Powered
Powered
Powered
Powered
Unpowered
VDD2 State
Powered
Powered
Powered
Powered
Powered
VOA Output
L
L
H
H
L
VOB Output
L
H
L
H
L
X
X
Powered
Unpowered
L
L
1
X = don’t care, L = low, H = high.
Rev. C | Page 8 of 16
Notes
Outputs return to the input state within 1 µs of
VDD1 power restoration.
Outputs return to the input state within 1 µs of
VDD2 power restoration.
Data Sheet
ADuM3220/ADuM3221
TYPICAL PERFORMANCE CHARACTERISTICS
300
VDD2
VDD2
VDD2
VDD2
250
GATE CHARGE (nC)
CH2 = VO (2V/DIV)
2
= 15V
= 10V
= 8V
= 5V
200
150
100
CH1 = VI (5V/DIV)
50
CH2 2V Ω
M40ns
T 22.2%
2.5GSPS
CH2
10k POINTS
7.2V
Figure 5. Output Waveform for 2 nF Load with 10 V Output Supply
0
0
200
400
600
800
1000
SWITCHING FREQUENCY (kHz)
08994-107
CH1 5V Ω
08994-004
1
Figure 8. Typical Maximum Load vs. Switching Frequency (RGATE = 1 Ω)
2.0
CH2 = VO (2V/DIV)
IDD1 CURRENT (mA)
1.5
2
CH1 = VI (5V/DIV)
VDD1 = 5V
1.0
VDD1 = 3.3V
0.5
CH2 2V Ω
M40ns
T 21.4%
2.5GSPS
CH2
10k POINTS
7.2V
0
0
0.25
0.50
0.75
1.00
FREQUENCY (MHz)
Figure 6. Output Waveform for 1 nF Load with 10 V Output Supply
08994-015
CH1 5V Ω
08994-005
1
Figure 9. Typical IDD1 Supply Current vs. Frequency
80
CH2 = VO (2V/DIV)
VDD2 = 15V
70
IDD2 CURRENT (mA)
60
2
CH1 = VI (5V/DIV)
VDD2 = 10V
50
40
30
VDD2 = 5V
20
CH2 2V Ω
M40ns
T 22.1%
2.5GSPS
CH2
10k POINTS
7.2V
08994-006
CH1 5V Ω
0
0
0.25
0.50
0.75
1.00
FREQUENCY (MHz)
Figure 7. Output Waveform for 1 nF Load with 5 Ω Series Resistance
and 10 V Output Supply
Figure 10. Typical IDD2 Supply Current vs. Frequency with 2 nF Load
Rev. C | Page 9 of 16
08994-016
10
1
Data Sheet
60
30
50
25
RISE/FALL TIME (ns)
40
30
20
20
RISE TIME
10
5
10
20
40
60
80
100
120
140
JUNCTION TEMPERATURE (°C)
0
Figure 11. Typical Propagation Delay vs. Temperature
5
PROPAGATION DELAY CHANNEL-TO-CHANNEL
MATCHING (ns)
PROPAGATION DELAY (ns)
tDLH
30
20
3.5
4.0
4.5
5.0
5.5
INPUT SUPPLY VOLTAGE (V)
08994-018
10
0
3.0
Figure 12. Typical Propagation Delay vs. Input Supply Voltage, VDD2 = 10 V
tDLH
40
30
20
7
9
11
13
OUTPUT SUPPLY VOLTAGE (V)
15
17
17
Figure 13. Typical Propagation Delay vs. Output Supply Voltage, VDD1 = 5 V
4
3
2
PD MATCH tDLH
1
PD MATCH tDHL
0
7
9
11
13
15
17
Figure 15. Typical Propagation Delay Channel-to-Channel Matching
vs. Output Supply Voltage
5
4
3
2
PD MATCH tDLH
1
PD MATCH tDHL
0
–40
08994-019
10
5
15
OUTPUT SUPPLY VOLTAGE (V)
PROPAGATION DELAY CHANNEL-TO-CHANNEL
MATCHING (ns)
tDHL
0
13
5
5
60
50
11
Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage
tDHL
40
9
OUTPUT SUPPLY VOLTAGE (V)
60
50
7
08994-020
0
08994-021
–20
08994-017
0
–40
PROPAGATION DELAY (ns)
FALL TIME
15
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
120
140
08994-022
PROPAGATION DELAY (ns)
ADuM3220/ADuM3221
Figure 16. Typical Propagation Delay Channel-to-Channel Matching
vs. Temperature, VDD2 = 10 V
Rev. C | Page 10 of 16
Data Sheet
ADuM3220/ADuM3221
1.6
VOUT SOURCE RESISTANCE
1.2
ROUT (Ω)
1.0
VOUT SINK RESISTANCE
0.8
0.6
0.4
0.2
4
6
8
10
12
14
OUTPUT SUPPLY VOLTAGE (V)
16
18
Figure 17. Typical Output Source Resistance vs. Output Supply Voltage
6
SOURCE IOUT
5
4
3
SINK IOUT
2
1
0
08994-116
0
7
4
6
8
10
12
14
OUTPUT SUPPLY VOLTAGE (V)
16
18
08994-117
1.4
MAXIMUM SOURCE/SINK CURRENT (A)
8
Figure 18. Typical Maximum Source/Sink Current vs. Output Supply Voltage
Rev. C | Page 11 of 16
ADuM3220/ADuM3221
Data Sheet
APPLICATIONS INFORMATION
The ADuM3220/ADuM3221 digital isolators require no external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 19. Use a small ceramic capacitor with a value
from 0.01 µF to 0.1 µF to provide a good high frequency bypass.
On the output power supply pin, VDD2, it is recommended that a
10 µF capacitor also be added to provide the charge required to
drive the gate capacitance at the ADuM3220/ADuM3221 outputs.
On the output supply pin, the use of vias with the bypass capacitor
should be avoided, or multiple vias should be used to reduce the
inductance in the bypassing. The total lead length between both
ends of the smaller capacitor and the input or output power
supply pin should not exceed 20 mm.
VDD1
VIA
VOA
VIB
VOB
GND1
GND2
08994-023
VDD2
Figure 19. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a
logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output. The ADuM3220/ADuM3221 specify tDLH
as the time between the input rising high logic threshold, VIH,
and the output rising 10% threshold (see Figure 20). Likewise, the
falling propagation delay, tDHL, is defined as the time between the
input falling logic low threshold, VIL, and the output falling 90%
threshold. The rise and fall times are dependent on the loading
conditions and are not included in the propagation delay, as is
the industry standard for gate drivers.
90%
OUTPUT
10%
VIL
Package thermal dissipation limits the performance of switching
frequency vs. output load, as illustrated in Figure 8, which shows
the maximum load capacitance that can be driven with a 1 Ω series
gate resistor for different values of output voltage. For example,
this curve shows that a typical ADuM3220/ADuM3221 can drive
a large MOSFET with 120 nC gate charge at 8 V output (which is
equivalent to a 15 nF load) up to a frequency of about 300 kHz.
OUTPUT LOAD CHARACTERISTICS
The ADuM3220/ADuM3221 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate-to-source capacitance (CGS), as
shown in Figure 21.
VIA
ADuM3220/
ADuM3221
VOA RSW
RGATE
LTRACE
VO
CGS
Figure 21. RLC Model of the Gate of an N-Channel MOSFET
RSW is the switch resistance of the internal ADuM3220/ADuM3221
driver output, which is about 1.5 Ω. RGATE is the intrinsic gate
resistance of the MOSFET and any external series resistance. A
MOSFET that requires a 4 A gate driver has a typical intrinsic
gate resistance of about 1 Ω and a gate-to-source capacitance,
CGS, from 2 nF to 10 nF. LTRACE is the inductance of the printed
circuit board trace, typically a value of 5 nH or less for a welldesigned layout with a very short and wide connection from the
ADuM3220/ADuM3221 output to the gate of the MOSFET.
tF
08994-007
tDHL
tR
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal pad
beneath the part; therefore, heat is dissipated mainly through
the package pins.
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3220/ADuM3221 output responds
to a step change. For a well-damped output, Q is less than 1.
Adding a series gate resistor dampens the output response.
VIH
INPUT
tDLH
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
08994-118
PC BOARD LAYOUT
Q=
Figure 20. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3220/ADuM3221 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3220/
ADuM3221 components operating under the same conditions.
(RSW
1
×
+ RGATE )
LTRACE
CGS
In Figure 5 and Figure 6, the ADuM3220/ADuM3221 output
waveforms for 10 V output are shown for a CGS of 2 nF and 1 nF,
respectively. Note the ringing of the output in Figure 6 with CGS
of 1 nF and a calculated Q factor of 1.5, where less than 1 is
desired for good damping.
Rev. C | Page 12 of 16
Data Sheet
ADuM3220/ADuM3221
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions of more than 1 µs at the input, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output.
If the decoder receives no internal pulses for more than about
3 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default
low state by the watchdog timer circuit. In addition, the outputs
are in a low default state while the power is rising before the
UVLO threshold is crossed.
The ADuM3220/ADuM3221 are immune to external magnetic
fields. The limitation on the ADuM3220/ADuM3221 magnetic
field immunity is set by the condition in which induced voltage
in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3220/ADuM3221 is examined because
it represents the most susceptible mode of operation. The pulses
at the transformer output have an amplitude greater than 1.0 V.
The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
0.1
0.01
1M
10k
100k
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 22. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse
(and had the worst-case polarity), the received pulse is reduced
from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3220/ADuM3221 transformers. Figure 23 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM3220/ADuM3221
are immune and can be affected only by extremely large currents
operated at a high frequency very close to the component. For
the 1 MHz example, a 0.5 kA current must be placed 5 mm
away from the ADuM3220/ADuM3221 to affect the operation
of the component.
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 23. Maximum Allowable Current for Various
Current-to-ADuM3220/ADuM3221 Spacings
Rev. C | Page 13 of 16
100M
08994-010
MAXIMUM ALLOWABLE CURRENT (kA)
Given the geometry of the receiving coil in the ADuM3220/
ADuM3221 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder,
a maximum allowable magnetic field is calculated, as shown
in Figure 22.
1
0.001
1k
V = (−dβ/dt) ∑ πrn2; n = 1, 2, ... , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
10
08994-009
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
Output ringing can be reduced by adding a series gate resistor
to dampen the response. For applications that use a load of 1 nF
or less, it is recommended that a series gate resistor of about 5 Ω
be added. As shown in Figure 7, RGATE is 5 Ω, which yields a
calculated Q factor of about 0.3. Figure 7 illustrates a damped
response in comparison with Figure 6.
ADuM3220/ADuM3221
Data Sheet
IDDI = IDDI(Q)
f ≤ 0.5fr
IDDI = IDDI(D) × (2f − fr) + IDDI(Q)
f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO(Q)
f ≤ 0.5fr
−3
IDDO = (IDDO(D) + (0.5 × 10 ) × CLVDDO) × (2f − fr) + IDDO(Q)
f > 0.5fr
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI(Q), IDDO(Q) are the specified input and output quiescent supply
currents (mA).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled.
The insulation lifetime of the ADuM3220/ADuM3221 depends
on the voltage waveform type imposed across the isolation
barrier. The iCoupler insulation structure degrades at different
rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 24, Figure 25, and Figure 26 illustrate these
different isolation voltage waveforms.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. Any crossinsulation voltage waveform that does not conform to Figure 25
or Figure 26 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 9.
Note that the voltage presented in Figure 25 is shown as sinusoidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
Figure 9 provides total input IDD1 supply current as a function of
frequency for both input channels. Figure 10 provides total IDD2
supply current as a function of frequency for both outputs loaded
with 2 nF capacitance.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries out
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM3220/ADuM3221.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
Rev. C | Page 14 of 16
RATED PEAK VOLTAGE
08994-011
For each input channel, the supply current is given by
0V
Figure 24. Bipolar AC Waveform
RATED PEAK VOLTAGE
08994-012
The supply current at a given channel of the ADuM3220/
ADuM3221 isolator is a function of the supply voltage, channel
data rate, and channel output load.
The values shown in Table 9 summarize the peak voltage for
50 years of service life. In many cases, the approved working
voltage is higher than the 50-year service life voltage. Operation
at these high working voltages can lead to shortened insulation
life in some cases.
0V
Figure 25. Unipolar AC Waveform
RATED PEAK VOLTAGE
08994-013
POWER CONSUMPTION
0V
Figure 26. DC Waveform
Data Sheet
ADuM3220/ADuM3221
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 27. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1, 2
ADuM3220ARZ
ADuM3220ARZ-RL7
ADuM3220BRZ
ADuM3220BRZ-RL7
ADuM3220WARZ
ADuM3220WARZ-RL7
ADuM3220WBRZ
ADuM3220WBRZ-RL7
ADuM3221ARZ
ADuM3221ARZ-RL7
ADuM3221BRZ
ADuM3221BRZ-RL7
ADuM3221WARZ
ADuM3221WARZ-RL7
ADuM3221WBRZ
ADuM3221WBRZ-RL7
1
2
No. of
Inputs,
VDD1 Side
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Maximum
Data Rate
(MHz)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Maximum
Propagation
Delay, 5 V (ns)
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
Minimum
VDD2
Operating
Voltage (V)
4.5
4.5
7.6
7.6
4.5
4.5
7.6
7.6
4.5
4.5
7.6
7.6
4.5
4.5
7.6
7.6
Output ShootThrough
Protection
(Yes/No)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Junction
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package
Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADuM3220W and ADuM3221W models are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial
models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products
shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product
ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. C | Page 15 of 16
ADuM3220/ADuM3221
Data Sheet
NOTES
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08994-0-10/12(C)
Rev. C | Page 16 of 16