Microchip MCP6281 450 ua, 5 mhz rail-to-rail op amp Datasheet

MCP6281/2/3/4/5
450 µA, 5 MHz Rail-to-Rail Op Amp
Features
Description
•
•
•
•
•
•
•
•
The Microchip Technology Inc. MCP6281/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 5 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This family also operates from a single supply
voltage as low as 2.2V, while drawing 450 µA (typ.)
quiescent current. Additionally, the MCP6281/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD + 300 mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
Gain Bandwidth Product: 5 MHz (typ.)
Supply Current: IQ = 450 µA (typ.)
Supply Voltage: 2.2V to 5.5V
Rail-to-Rail Input/Output
Extended Temperature Range: -40°C to +125°C
Available in Single, Dual and Quad Packages
Single with Chip Select (CS) (MCP6283)
Dual with Chip Select (CS) (MCP6285)
Applications
•
•
•
•
•
•
The MCP6285 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in Low-power mode.
Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
The MCP6281/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 5.5V.
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
NC 1
VIN_
MCP6281
SOT-23-5
8 NC
2
VIN+ 3
VSS 4
7 VDD
VSS 2
6 VOUT
VIN+ 3
5 NC
MCP6283
PDIP, SOIC, MSOP
NC 1
VSS 4
8 CS
+
7 VDD
4 VIN–
6 VDD
VSS 2
6 VOUT
VIN+ 3
5 NC
-
5 CS
_
4 VIN
VOUTA 1
14 VOUTD
- + + - 13 VIND_
VINA+ 3
12 VIND+
VDD 4
VINB+ 5
VINB_ 6
VOUTB 7
 2004 Microchip Technology Inc.
4 VIN–
VINA_ 2
11 VSS
10 VINC+
8 VDD
VINA_ 2
-
MCP6284
PDIP, SOIC, TSSOP
SOT-23-6
VOUT 1
VIN+ 3
VOUTA 1
5 VSS
VOUT 1
VDD 2
-
MCP6283
+
VIN_ 2
VIN+ 3
MCP6282
PDIP, SOIC, MSOP
SOT-23-5
5 VDD
VOUT 1
+
+
MCP6281R
+
MCP6281
PDIP, SOIC, MSOP
7 VOUTB
- +
VINA+ 3
+ -
VSS 4
6 VINB_
5 VINB+
MCP6285
PDIP, SOIC, MSOP
VOUTA/VINB+ 1
VINA_
2
VINA+ 3
VSS 4
8 VDD
7 VOUTB
- +
+ -
_
6 VINB
5 CS
-+ +- 9 V _
INC
8 VOUTC
DS21811D-page 1
MCP6281/2/3/4/5
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................. Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature (TJ) . .........................................+150°C
ESD Protection On All Pins (HBM;MM) ................ ≥ 4 kV;400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND,
VCM = VDD/2, RL = 10 kΩ to VDD/2 and VOUT ≈ VDD/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
-3.0
—
+3.0
mV
VCM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature)
VOS
-5.0
—
+5.0
mV
TA= -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift
∆VOS/∆TA
—
±1.7
—
Power Supply Rejection Ratio
PSRR
70
90
—
Input Offset
µV/°C TA= -40°C to +125°C,
VCM = VSS (Note 1)
dB
VCM = VSS (Note 1)
Input Bias, Input Offset Current and Impedance
IB
—
±1.0
—
pA
Note 2
At Temperature
IB
—
50
200
pA
TA= +85°C (Note 2)
At Temperature
IB
—
2
5
nA
TA= +125°C (Note 2)
Input Bias Current
Input Offset Current
IOS
—
±1.0
—
pA
Note 3
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Note 3
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF
Note 3
Common Mode Input Range
VCMR
VSS − 0.3
—
VDD + 0.3
V
Common Mode Rejection Ratio
CMRR
70
85
—
dB
VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio
CMRR
65
80
—
dB
VCM = -0.3V to 5.3V, VDD = 5V
AOL
90
110
—
dB
VOUT = 0.2V to VDD – 0.2V,
VCM = VSS (Note 1)
VOL, VOH
VSS + 15
—
VDD – 15
mV
ISC
—
±25
—
mA
VDD
2.2
—
5.5
V
IQ
300
450
570
µA
Common Mode (Note 4)
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
3:
4:
IO = 0
The MCP6285’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
The current at the MCP6285’s VINB– pin is specified by IB only.
This specification does not apply to the MCP6285’s VOUTA/VINB+ pin.
The MCP6285’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6285’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.
DS21811D-page 2
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
MHz
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
5.0
—
Phase Margin at Unity-Gain
PM
—
65
—
°
Slew Rate
SR
—
2.5
—
V/µs
Input Noise Voltage
Eni
—
3.5
—
µVP-P
Input Noise Voltage Density
eni
—
16
—
nV/√Hz
f = 1 kHz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
Noise
f = 0.1 Hz to 10 Hz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note:
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
 2004 Microchip Technology Inc.
DS21811D-page 3
MCP6281/2/3/4/5
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
—
0.01
—
µA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.7
2
µA
CS = VDD
GND Current per Amplifier
ISS
—
-0.7
—
µA
CS = VDD
Amplifier Output Leakage
—
—
0.01
—
µA
CS = VDD
CS Low to Valid Amplifier
Output, Turn-on Time
tON
—
4
10
µs
CS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output High-Z
tOFF
—
0.01
—
µs
CS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
VHYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS = VSS
CS High Specifications
Dynamic Specifications (Note 1)
Hysteresis
Note 1:
The input condition (VIN) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested
at the output of op amp B (VOUTB).
CS
VIL
VIH
tOFF
tON
VOUT
ISS
ICS
Hi-Z
Hi-Z
-0.7 µA (typ.)
-0.7 µA (typ.)
-450 µA (typ.)
0.7 µA (typ.)
0.7 µA (typ.)
10 nA (typ.)
FIGURE 1-1:
Timing Diagram for the
Chip Select (CS) pin on the MCP6283 and
MCP6285.
DS21811D-page 4
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
30%
832 Samples
VCM = VSS
10%
8%
6%
4%
2%
20%
15%
10%
5%
0%
2.8
2.4
2.0
1.6
-10
-8
Input Offset Voltage (mV)
FIGURE 2-4:
35%
70
80
90
Input Offset Voltage Drift.
210 Samples
TA = +125°C
25%
20%
15%
10%
5%
0%
100
Input Bias Current (pA)
Input Bias Current (pA)
FIGURE 2-2:
TA = +85 °C.
FIGURE 2-5:
TA = +125 °C.
Input Bias Current at
300
VDD = 2.2V
Input Offset Voltage (µV)
250
200
150
100
50
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
-50
VDD = 5.5V
200
150
100
50
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
-50
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.2V.
 2004 Microchip Technology Inc.
6.0
5.5
5.0
4.5
4.0
2.5
3.5
2.0
3.0
1.5
2.5
1.0
2.0
0.5
Common Mode Input Voltage (V)
1.0
0.0
0.5
-100
0.0
-100
-0.5
Input Bias Current at
250
-0.5
Input Offset Voltage (µV)
300
10
3600
60
8
3200
50
6
2800
0%
40
4
2400
5%
30
2
2000
10%
20
0
1600
15%
10
-2
1200
20%
30%
0
210 Samples
TA = +85°C
Percentage of Occurrences
Percentage of Occurrences
25%
0
-4
800
Input Offset Voltage.
200
FIGURE 2-1:
-6
Input Offset Voltage Drift (µV/°C)
400
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-2.8
0%
832 Samples
VCM = VSS
TA = -40°C to +125°C
25%
1.5
12%
Percentage of Occurrences
Percentage of Occurrences
14%
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21811D-page 5
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
10,000
VCM = VSS
Representative Part
250
Input Bias, Offset Currents
(pA)
Input Offset Voltage (µV)
300
200
150
100
50
0
VDD = 5.5V
VDD = 2.2V
-50
-100
VCM = VDD
VDD = 5.5V
1,000
Input Bias Current
100
Input Offset Current
10
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
25
35
45
Output Voltage (V)
FIGURE 2-7:
Output Voltage.
55
65
75
85
95
105 115 125
Ambient Temperature (°C)
FIGURE 2-10:
Input Bias, Input Offset
Currents vs. Ambient Temperature.
Input Offset Voltage vs.
120
110
PSRRCMRR
90
110
PSRR, CMRR (dB)
CMRR, PSRR (dB)
100
PSRR+
80
70
60
50
40
CMRR
100
90
PSRR
VCM = VSS
80
70
30
20
60
1.E+00
1.E+01
1
1.E+02
10
100
1.E+03
1.E+04
1k
1.E+05
10k
1.E+06
100k
-50
1M
-25
Frequency (Hz)
FIGURE 2-8:
Frequency.
FIGURE 2-11:
Temperature.
CMRR, PSRR vs.
2.5
45
Input Bias, Offset Currents
(nA)
Input Bias, Offset Currents
(pA)
55
Input Bias Current
35
25
15
5
Input Offset Current
-5
TA = +85°C
VDD = 5.5V
-15
0
25
50
75
100
125
Ambient Temperature (°C)
2.0
CMRR, PSRR vs. Ambient
TA = +125°C
VDD = 5.5V
1.5
Input Bias Current
1.0
0.5
0.0
Input Offset Current
-0.5
-1.0
-25
0.0
0.5
1.0
1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +85°C.
DS21811D-page 6
0.0
0.5 1.0
1.5
2.0
2.5 3.0
3.5
4.0
4.5 5.0
5.5
Common Mode Input Voltage (V)
FIGURE 2-12:
Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +125°C.
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
1000
500
400
300
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
10
VOL - VSS
VDD - VOH
1
0.01
0.1
Power Supply Voltage (V)
120
0
100
-30
FIGURE 2-16:
Output Voltage Headroom
vs. Output Current Magnitude.
60
-90
Phase
0
-180
90
VDD = 5.5V
5
85
VDD = 2.2V
Gain Bandwidth Product
4
3
2
70
VDD = 2.2V
Phase Margin
1
65
1.E+08
-50
-25
0
25
50
75
100
60
125
Ambient Temperature (°C)
Open-Loop Gain, Phase vs.
FIGURE 2-17:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
10
4.5
4.0
VDD = 5.5V
Slew Rate (V/µs)
Maximum Output Voltage
Swing (VP-P)
75
VDD = 5.5V
Frequency (Hz)
FIGURE 2-14:
Frequency.
80
0
-210
10k 100k 1M 10M 100M
1.E+07
1k
1.E+06
100
1.E+05
10
1.E+04
1
1.E+03
-150
1.E+02
20
1.E+01
-120
1.E+00
40
Gain Bandwidth Product
(MHz)
-60
Open-Loop Phase (°)
Gain
0.1
10
6
80
1.E-01
Open-Loop Gain (dB)
FIGURE 2-13:
Quiescent Current vs.
Power Supply Voltage.
-20
1
Output Current Magnitude (mA)
Phase Margin (°)
200
Ouput Voltage Headroom (mV)
Quiescent Current
(µA/amplifier)
600
VDD = 2.2V
1
3.5
Falling Edge, VDD = 2.2V
Falling Edge, VDD = 5.5V
3.0
2.5
2.0
1.5
Rising Edge, VDD = 5.5V
Rising Edge, VDD = 2.2V
1.0
0.5
1M
1.E+07
100k
1.E+06
10k
1.E+05
1k
1.E+04
1.E+03
0.0
0.1
10M
-50
-25
FIGURE 2-15:
Maximum Output Voltage
Swing vs. Frequency.
 2004 Microchip Technology Inc.
0
25
50
75
100
125
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-18:
Temperature.
Slew Rate vs. Ambient
DS21811D-page 7
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
30
Input Noise Voltage Density
(nV/¥Hz)
Input Noise Voltage Density
(nV/—Hz)
1,000
100
10
1.E-01
1.E+00
0.1
1
1.E+01
1.E+02
10
100
1.E+03
1.E+04
1k
10k
1.E+05
20
15
10
5
0
1.E+06
100k
f = 1 kHz
VDD = 5.0V
25
1M
0.0
0.5
Frequency (Hz)
FIGURE 2-19:
vs. Frequency.
Input Noise Voltage Density
30
25
20
15
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.5
4.0
4.5
5.0
3.0
3.5
4.0
4.5
5.0
130
120
110
100
5.5
1
10
100
Frequency (kHz)
FIGURE 2-20:
Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-23:
Channel-to-Channel
Separation vs. Frequency (MCP6282 and
MCP6284 only).
1000
Op-Amp shuts off here
450
900
Quiescent Current
(µA/Amplifier)
Op-Amp turns on here
400
350
300
250
Hysteresis
200
150
CS swept
high to low
100
CS swept
low to high
VDD = 5.5V
800
Hysteresis
700
500
400
300
200
100
VDD = 2.2V
0
CS swept
low to high
600
CS swept
high to low
500
Quiescent Current
(µA/Amplifier)
2.5
140
Power Supply Voltage (V)
50
2.0
FIGURE 2-22:
Input Noise Voltage Density
vs. Common Mode Input Voltage at 1 kHz.
Channel-to-Channel Separation
(dB)
Ouptut Short Circuit Current
(mA)
35
10
1.0
Common Mode Input Voltage (V)
Op Amp toggles On/Off here
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Chip Select Voltage (V)
FIGURE 2-21:
Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.2V
(MCP6283 and MCP6285 only).
DS21811D-page 8
2.2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Chip Select Voltage (V)
FIGURE 2-24:
Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 5.5V
(MCP6283 and MCP6285 only).
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
5.0
5.0
G = +1V/V
VDD = 5.0V
4.5
Output Voltage (V)
Output Voltage (V)
4.0
3.5
3.0
2.5
2.0
1.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
G = -1V/V
VDD = 5.0V
4.5
0.E+00
2.E-06
4.E -06
6.E-06
8.E-06
1.E-05
1.E-05
1.E-05
2.E-05
2.E-05
0.0
2.E -05
0.E+00
2.E-06
4.E-06
6.E-06
8.E-06
FIGURE 2-25:
Pulse Response.
Large-Signal, Non-inverting
FIGURE 2-28:
Pulse Response.
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)
G = +1V/V
Small-Signal, Non-inverting
FIGURE 2-29:
Pulse Response.
2.E-05
2.E-05
2.E-05
Large-Signal, Inverting
Small-Signal, Inverting
6.0
VDD = 2.2V
G = +1V/V
VIN = VSS
CS Voltage
2.0
Chip Select, Output Voltages
(V)
Chip Select, Output Voltages
(V)
1.E-05
Time (500 ns/div)
2.5
1.5
VOUT
Output On
1.0
0.5
Output High-Z
0.0
1.E-05
G = -1V/V
Time (500 ns/div)
FIGURE 2-26:
Pulse Response.
1.E-05
Time (2 µs/div)
Time (2 µs/div)
0.0E+00
5.0E-06
1.0E-05
1.5E-05
2.0E-05
2.5E-05
3.5E-05
4.0E-05
4.5E-05
4.5
4.0
3.5
VOUT
3.0
2.5
2.0
1.5
1.0
Output High-Z
Output On
0.5
0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
5.0E-05
Time (5 µs/div)
FIGURE 2-27:
Chip Select (CS) to
Amplifier Output Response Time at VDD = 2.2V
(MCP6283 and MCP6285 only).
 2004 Microchip Technology Inc.
CS Voltage
5.0
0.0
3.0E-05
VDD = 5.5V
G = +1V/V
VIN = VSS
5.5
Time (5 µs/div)
FIGURE 2-30:
Chip Select (CS) to
Amplifier Output Response Time at VDD = 5.5V
(MCP6283 and MCP6285 only).
DS21811D-page 9
MCP6281/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6281
MCP6281 MCP6271R
(PDIP, SOIC,
(SOT-23-5) (SOT-23-5)
MSOP)
1
6
1
VOUT
Analog Output
2
4
4
2
4
VIN–
Inverting Input
3
3
3
3
3
VIN+
Non-inverting Input
7
5
2
7
6
VDD
Positive Power Supply
Negative Power Supply
4
2
5
4
2
VSS
—
—
—
8
5
CS
Chip Select
1,5,8
—
—
1,5
—
NC
No Internal Connection
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
Symbol
Description
1
1
—
VOUTA
Analog Output (op amp A)
2
2
2
VINA–
Inverting Input (op amp A)
3
3
3
VINA+
Non-inverting Input (op amp A)
8
4
8
VDD
5
5
—
VINB+
Non-inverting Input (op amp B)
6
6
6
VINB–
Inverting Input (op amp B)
7
7
7
VOUTB
Analog Output (op amp B)
—
8
—
VOUTC
Analog Output (op amp C)
—
9
—
VINC–
Inverting Input (op amp C)
—
10
—
VINC+
Non-inverting Input (op amp C)
4
11
4
VSS
—
12
—
VIND+
Non-inverting Input (op amp D)
—
13
—
VIND–
Inverting Input (op amp D)
—
14
—
VOUTD
Analog Output (op amp D)
—
—
1
VOUTA/VINB+
—
—
5
CS
Positive Power Supply
Negative Power Supply
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
Analog Outputs
The output pins are low-impedance voltage sources.
Analog Inputs
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Description
1
MCP6282 MCP6284 MCP6285
3.2
MCP6283
Symbol
(SOT-23-6)
6
TABLE 3-2:
3.1
MCP6283
(PDIP, SOIC,
MSOP)
MCP6285’s VOUTA/VINB+ Pin
For the MCP6285 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pin. This connection
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
DS21811D-page 10
3.4
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.5
Power Supply (VSS and VDD)
The positive power supply (VDD) is 2.2V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
4.0
APPLICATION INFORMATION
The MCP6281/2/3/4/5 family of op amps is manufactured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for lowcost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/2/3/4/5 ideal for
battery-powered applications.
4.1
RIN
VDD = 5.0V
G = +2 V/V
5
VOUT
VIN
2
4.3
1
0
-1
FIGURE 4-2:
Resistor (RIN).
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
Input Current Limiting
Rail-to-Rail Output
The output voltage range of the MCP6281/2/3/4/5 op
amp is VDD – 15 mV (min.) and VSS + 15 mV (max.)
when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-16 for more information.
4
3
+
( Maximum expected VIN ) – V DD
R IN ≥ ---------------------------------------------------------------------------------2 mA
V SS – ( Minimum expected V IN )
R IN ≥ -----------------------------------------------------------------------------2 mA
4.2
6
VOUT
MCP628X
VIN
Rail-to-Rail Inputs
The MCP6281/2/3/4/5 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
Input, Output Voltage (V)
–
-5
Time (1 ms/div)
FIGURE 4-1:
The MCP6281/2/3/4/5 Show
No Phase Reversal.
The input stage of the MCP6281/2/3/4/5 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. With this
topology, the device operates with VCM up to 0.3V
above VDD and 0.3V below VSS. The Input Offset Voltage (VOS) is measured at VCM = VSS – 0.3V and
VDD + 0.3V to ensure proper operation.
Input voltages that exceed the absolute maximum
voltage (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-2.
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
–
RISO
MCP628X
VIN
+
VOUT
CL
FIGURE 4-3:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
 2004 Microchip Technology Inc.
DS21811D-page 11
MCP6281/2/3/4/5
Recommended RISO (Ω )
1
VINA–
100
VINA+
GN = 1 V/V
GN = 2 V/V
GN ≥ 4 V/V
B
3
7
VOUTB
A
MCP6285
5
10
100
1,000
10,000
CS
Normalized Load Capacitance; CL/GN (pF)
FIGURE 4-4:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and simulations with the MCP6281/2/3/4/5 SPICE macro model
are helpful.
MCP628X Chip Select (CS)
The MCP6283 and MCP6285 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ) and
flows through the CS pin to VSS. When this happens,
the amplifier output is put into a high-impedance state.
By pulling CS low, the amplifier is enabled. If the CS pin
is left floating, the amplifier may not operate properly.
Figure 1-1 shows the output voltage and supply current
response to a CS pulse.
4.5
6
2
10
4.4
VINB–
VOUTA/VINB+
1,000
Cascaded Dual Op Amps
(MCP6285)
The MCP6285 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP6283/5 Chip Select (CS)”.
FIGURE 4-5:
Cascaded Gain Amplifier.
The output of op amp A is loaded by the input impedance of op amp B, which is typically 1013Ω||6 pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD – 20 mV.
4.6
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other analog parts.
4.7
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6281/2/3/4/5 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
DS21811D-page 12
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
VIN–
VIN+
4.8
VSS
Application Circuits
4.8.1
SALLEN-KEY HIGH-PASS FILTER
The MCP6281/2/3/4/5 op amps can be used in activefilter applications. Figure 4-7 shows a second-order
Sallen-Key high-pass filter with a gain of 1. The output
bias voltage is set by the VDD/2 reference, which can
be changed to any voltage within the output voltage
range.
Guard Ring
FIGURE 4-6:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
R1
VIN
+
C1
C2
MCP6281
R2
–
VOUT
VDD/2
FIGURE 4-7:
Sallen-Key High-Pass Filter.
This filter, and others, can be designed using
Microchip’s FilterLab® software, which is available on
our web site (www.microchip.com).
4.8.2
INVERTING MILLER INTEGRATOR
Analog integrators are used in filters, control loops and
measurement circuits. Figure 4-8 shows the most
common implementation, the inverting Miller integrator.
The non-inverting input is at VDD/2 so that the op amp
properly biases up. The switch (SW) is used to zero the
output in some applications. Other applications use a
feedback loop to keep the output within its linear range
of operation.
SW
R
C
VOUT
VIN
+
MCP6281
VDD/2
–
VOUT
1
=
sRC
VIN
FIGURE 4-8:
 2004 Microchip Technology Inc.
Miller Integrator.
DS21811D-page 13
MCP6281/2/3/4/5
4.8.3
CASCADED OP AMP
APPLICATIONS
R4
The MCP6285 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6285 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Chip Select lines or a 10-pin device with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
4.8.3.1
Load Isolation
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistance loads in the feedback loop (such as an integrator
circuit or filter circuit), the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
R3
R2
B
A
VIN
VOUTB
A
MCP6285
CS
FIGURE 4-10:
Configuration.
4.8.3.3
Cascaded Gain Circuit
Difference Amplifier
Figure 4-11 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended to use well-matched resistors (e.g.,
0.1%) to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
VIN2
Load
VIN1
CS
FIGURE 4-9:
Buffer.
4.8.3.2
R2
R1
R2
A
R1
Isolating the Load with a
Cascaded Gain
VOUT
MCP6285
R4
B
R1
R3
B
VOUT
MCP6285
CS
FIGURE 4-11:
Difference Amplifier Circuit.
Figure 4-10 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of
op amp A and B, as shown below:
V OUT = V IN G A G B + V OSA G A G B + V OSB G B
Where:
GA = op amp A gain
GB = op amp B gain
VOSA = op amp A input offset voltage
VOSB = op amp B input offset voltage
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).
DS21811D-page 14
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
4.8.3.4
Buffered Non-inverting Integrator
Figure 4-12 shows a lossy non-inverting integrator that
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this configuration, matching the impedance at each input is
recommended. RF is used to provide a feedback loop
at frequencies << 1/(2πR1C1) and makes this a lossy
integrator (it has a finite gain at DC). Op amp B is used
to isolate the load from the integrator.
4.8.3.6
Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
Figure 4-14 is a second-order multiple feedback lowpass filter with Chip Select. Use the FilterLab® software
from Microchip to determine the R and C values for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3, R6 and R7.
R6
R1
R2
C2
C1
R3
RF
VIN
R1
C3
VOUT
B
A
R7
R2
VIN
R5
C2
VOUT
MCP6285
R4
MCP6285
B
A
C1
CS
R1 C 1 = ( R 2 || R F )C 2
CS
FIGURE 4-12:
Buffered Non-inverting
Integrator with Chip Select.
4.8.3.5
Inverting Integrator with Active
Compensation and Chip Select
Figure 4-13 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity-gain buffer to isolate the integration
capacitor C1 from op amp A and drives the capacitor
with low-impedance source. Since both op amps are
matched very well, they provide a higher quality
integrator.
VIN
R1
FIGURE 4-14:
Second-Order Multiple
Feedback Low-Pass Filter with an Extra
Pole-Zero Pair.
4.8.3.7
Figure 4-15 is a second-order Sallen-Key low-pass
filter with Chip Select. Use the FilterLab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3, R5 and R6.
R2
R4
C1
Second-Order Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
R3
VIN
R1
C3
R6
B
A
VOUT
MCP6285
C1
B
R5
C2
CS
VOUT
A
MCP6285
FIGURE 4-15:
Second-Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
CS
FIGURE 4-13:
Compensation.
Integrator Circuit with Active
 2004 Microchip Technology Inc.
DS21811D-page 15
MCP6281/2/3/4/5
4.8.3.8
Capacitorless Second-Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three external resistors; the op amp's GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and
process. However, this configuration provides a lowcost solution for applications with high bandwidth
requirements.
VIN
R1
R2
R3
B
VREF
VOUT
MCP6285
CS
FIGURE 4-16:
Capacitorless Second-Order
Low-Pass Filter with Chip Select.
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6281/2/3/4/5 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP6281/2/3/4/5 op amps is available on our web site
at www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
macro model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
A
DS21811D-page 16
5.0
FilterLab® Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab design tool provides
full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE
format, which can be used with the macro model to
simulate actual filter performance.
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP6281 and MCP6281R)
Device
XXNN
Code
MCP6281
CHNN
MCP6281R
EUNN
CH25
Note: Applies to 5-Lead SOT-23.
6-Lead SOT-23 (MCP6283)
XXNN
CL25
8-Lead MSOP
Example:
XXXXXX
6281E
YWWNNN
437256
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
MCP6281
E/P256
0437
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6281
E/SN0437
256
Legend:
Note:
*
Example:
XX...X
YY
WW
NNN
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
 2004 Microchip Technology Inc.
DS21811D-page 17
MCP6281/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6284)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (150 mil) (MCP6284)
Example:
MCP6284-E/P
0437256
Example:
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6284)
XXXXXX
YYWW
NNN
DS21811D-page 18
MCP6284ESL
0437256
Example:
6284EST
0437
256
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
p
B
p1
n
D
1
α
c
A
L
β
Units
Dimension Limits
n
p
MIN
φ
A2
A1
INCHES*
NOM
5
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
.006
.017
5
5
MAX
MIN
MILLIMETERS
NOM
5
0.95
1.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
0.15
0.43
5
5
Number of Pins
Pitch
p1
Outside lead pitch (basic)
Overall Height
A
.035
.057
0.90
Molded Package Thickness
A2
.035
.051
0.90
Standoff
A1
.000
.006
0.00
Overall Width
E
.102
.118
2.60
Molded Package Width
E1
.059
.069
1.50
Overall Length
D
.110
.122
2.80
Foot Length
L
.014
.022
0.35
φ
Foot Angle
0
10
0
c
Lead Thickness
.004
.008
0.09
Lead Width
B
.014
.020
0.35
α
Mold Draft Angle Top
0
10
0
β
Mold Draft Angle Bottom
0
10
0
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
EIAJ Equivalent: SC-74A
Drawing No. C04-091
 2004 Microchip Technology Inc.
DS21811D-page 19
MCP6281/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
E
E1
B
p1
n
D
1
α
c
A
A2
φ
L
β
Units
Dimension Limits
n
p
MIN
A1
INCHES*
NOM
6
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
.006
.017
5
5
MAX
MILLIMETERS
NOM
6
0.95
1.90
0.90
1.18
0.90
1.10
0.00
0.08
2.60
2.80
1.50
1.63
2.80
2.95
0.35
0.45
0
5
0.09
0.15
0.35
0.43
0
5
0
5
MIN
Number of Pins
Pitch
p1
Outside lead pitch (basic)
Overall Height
A
.035
.057
Molded Package Thickness
.035
.051
A2
Standoff
.000
.006
A1
Overall Width
E
.102
.118
Molded Package Width
.059
.069
E1
Overall Length
D
.110
.122
Foot Length
L
.014
.022
φ
Foot Angle
0
10
c
Lead Thickness
.004
.008
Lead Width
B
.014
.020
α
Mold Draft Angle Top
0
10
β
Mold Draft Angle Bottom
0
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21811D-page 20
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
.026 BSC
Pitch
A
.043
Overall Height
A2
.037
.030
.033
Molded Package Thickness
.000
.006
A1
Standoff
E
.193 TYP.
Overall Width
E1
.118 BSC
Molded Package Width
.118 BSC
D
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
Foot Angle
0°
8°
c
Lead Thickness
.003
.006
.009
.009
.012
.016
Lead Width
B
α
Mold Draft Angle Top
5°5°
15°
β
5°5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
 2004 Microchip Technology Inc.
DS21811D-page 21
MCP6281/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
§
A
A2
A1
E
E1
D
L
c
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21811D-page 22
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
 2004 Microchip Technology Inc.
DS21811D-page 23
MCP6281/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
.240
.250
.260
E1
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21811D-page 24
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
 2004 Microchip Technology Inc.
DS21811D-page 25
MCP6281/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B1
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS21811D-page 26
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
APPENDIX A:
REVISION HISTORY
Revision A (June 2003)
Original data sheet release.
Revision B (October 2003)
Revision C (June 2004)
Revision D (December 2004)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added SOT-23-5 packages for the MCP6281
and MCP6281R single op amps.
Added SOT-23-6 package for the MCP6283
single op amp.
Added Section 3.0 “Pin Descriptions”.
Corrected application circuits
(Section 4.8 “Application Circuits”).
Added SOT-23-5 and SOT-23-6 packages and
corrected
package
marking
information
(Section 6.0 “Packaging Information”).
Added Appendix A: Revision History.
 2004 Microchip Technology Inc.
DS21811D-page 27
MCP6281/2/3/4/5
NOTES:
DS21811D-page 28
 2004 Microchip Technology Inc.
MCP6281/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
–
X
/XX
Temperature
Range
Package
Device:
MCP6281:
MCP6281T:
MCP6281RT:
MCP6282:
MCP6282T:
MCP6283:
MCP6283T:
MCP6284:
MCP6284T:
MCP6285:
MCP6285T:
Single Op Amp
Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
Single Op Amp
(Tape and Reel) (SOT-23-5)
Dual Op Amp
Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
Single Op Amp with Chip Select
Single Op Amp with Chip Select
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
Quad Op Amp
Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
Dual Op Amp with Chip Select
Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
Examples:
a)
MCP6281-E/SN:
b)
MCP6281-E/MS:
c)
MCP6281-E/P:
d)
MCP6281T-E/OT:
a)
MCP6282-E/SN:
b)
c)
d)
a)
b)
c)
d)
Temperature Range:
E
= -40°C to +125°C
Package:
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6281, MCP6281R only)
CH = Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6283 only)
MS = Plastic MSOP, 8-lead
P
= Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD PDIP package.
Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
Extended Temperature,
8LD SOIC package.
MCP6282-E/MS: Extended Temperature,
8LD MSOP package.
MCP6282-E/P:
Extended Temperature,
8LD PDIP package.
MCP6282T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
MCP6283-E/SN:
Extended Temperature,
8LD SOIC package.
MCP6283-E/MS: Extended Temperature,
8LD MSOP package.
MCP6283-E/P:
Extended Temperature,
8LD PDIP package.
MCP6283T-E/CH: Tape and Reel,
Extended Temperature,
6LD SOT-23 package.
a)
MCP6284-E/P:
b)
MCP6284T-E/SL:
c)
MCP6284-E/SL:
d)
MCP6284-E/ST:
a)
MCP6285-E/SN:
b)
MCP6285-E/MS:
c)
MCP6285-E/P:
d)
MCP6285T-E/SN:
Extended Temperature,
14LD PDIP package.
Tape and Reel,
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD SOIC package.
Extended Temperature,
14LD TSSOP package.
Extended Temperature,
8LD SOIC package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD PDIP package.
Tape and Reel,
Extended Temperature,
8LD SOIC package.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
Your local Microchip sales office
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com) to receive the most current information on our products.
 2004 Microchip Technology Inc.
DS21811D-page 29
MCP6281/2/3/4/5
NOTES:
DS21811D-page 30
 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2004 Microchip Technology Inc.
DS21811D-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS21811D-page 32
 2004 Microchip Technology Inc.
Similar pages