Cypress CY7C341B-25RC/RI 192-macrocell max epld Datasheet

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CY7C341B
192-Macrocell MAX® EPLD
Features
• 192 macrocells in 12 logic array blocks (LABs)
• Eight dedicated inputs, 64 bidirectional I/O pins
• Advanced 0.65-micron CMOS technology to increase
performance
• Programmable interconnect array
• 384 expander product terms
• Available in 84-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C341B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the devices to accommodate a variety of independent logic functions.
The 192 macrocells in the CY7C341B are divided into 12 Logic
Array Blocks (LABs), 16 per LAB. There are 384 expander
product terms, 32 per LAB, to be used and shared by the
macrocells within each LAB. Each LAB is interconnected with
a programmable interconnect array, allowing all signals to be
routed throughout the chip.
The speed and density of the CY7C341B allows it to be used
in a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 37 times the functionality
of 20-pin PLDs, the CY7C341B allows the replacement of over
75 TTL devices. By replacing large amounts of logic, the
CY7C341B reduces board space, part count, and increases
system reliability.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8
macrocells are connected to I/O pins and eight are buried,
while for LABs B, C, D, E, H, I, J, and K, four macrocells are
connected to I/O pins and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there are 32 single product
term logic expanders in each LAB. Their use greatly enhances
the capability of the macrocells without increasing the number
of product terms in each macrocell.
Selection Guide
7C341B-25
7C341B-35
Unit
Maximum Access Time
25
35
ns
Cypress Semiconductor Corporation
Document #: 38-03016 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
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Logic Block Diagram
CY7C341B
1 (A6)
INPUT/CLK
INPUT
(C6) 84
2 (A5)
INPUT
INPUT
(C7) 83
41 (K6)
INPUT
INPUT
(L7) 44
42 (J6)
INPUT
INPUT
(J7) 43
SYSTEMCLOCK
4
(C5)
5
(A4)
6
(B4)
7
(A3)
8
(A2)
9
(B3)
10 (A1)
11 (B2)
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
LAB G
MACROCELL 97
MACROCELL 98
MACROCELL 99
MACROCELL 100
MACROCELL 101
MACROCELL 102
MACROCELL 103
MACROCELL 104
MACROCELL 9–16
(C2)
(B1)
(C1)
(D2)
22 (G3)
23 (G1)
25 (F1)
26 (H1)
27 (H2)
28 (J1)
29 (K1)
30 (J2)
31
32
33
34
35
36
37
38
(L1)
(K2)
(K3)
(L2)
(L3)
(K4)
(L4)
(J5)
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 113
MACROCELL 114
MACROCELL 115
MACROCELL 116
P
I
A
LAB I
MACROCELL 129
MACROCELL 130
MACROCELL 131
MACROCELL 132
MACROCELL 133–144
LAB D
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
LAB J
MACROCELL 145
MACROCELL 146
MACROCELL 147
MACROCELL 148
MACROCELL 53–64
MACROCELL 149–160
LAB E
MACROCELL 65
MACROCELL 66
MACROCELL 67
MACROCELL 68
LAB K
MACROCELL 161
MACROCELL 162
MACROCELL 163
MACROCELL 164
MACROCELL 69–80
MACROCELL 165–176
LAB F
MACROCELL 81
MACROCELL 82
MACROCELL 83
MACROCELL 84
MACROCELL 85
MACROCELL 86
MACROCELL 87
MACROCELL 88
LAB L
MACROCELL 177
MACROCELL 178
MACROCELL 179
MACROCELL 180
MACROCELL 181
MACROCELL 182
MACROCELL 183
MACROCELL 184
58
59
62
63
(H11)
(F10)
(G9)
(F9)
64
65
67
68
(F11)
(E11)
(E9)
(D11)
69
70
71
72
(D10)
(C11)
(B11)
(C10)
73
74
75
76
77
78
79
80
(A11)
(B10)
(B9)
(A10)
(A9)
(B8)
(A8)
(B6)
MACROCELL 185–192
MACROCELL 89–96
Document #: 38-03016 Rev. *C
(J10)
(K11)
(J11)
(H10)
MACROCELL 117–128
MACROCELL 37–48
3, 24, 45, 66 (B5, G2, K7, E10)
18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
54
55
56
57
LAB H
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21–32
16 (D1)
17 (E3)
20 (F2)
21 (F3)
(L6)
(L8)
(K8)
(L9)
(L10)
(K9)
(L11)
(K10)
MACROCELL 105–112
LAB B
12
13
14
15
46
47
48
49
50
51
52
53
VCC
GND
() – PERTAIN TO 84-PIN PGA PACKAGE
Page 2 of 12
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CY7C341B
Pin Configurations
PGA
Bottom View
L
I/O
I/O
I/O
I/O
GND
I/O
INPUT
I/O
I/O
I/O
I/O
K
I/O
I/O
I/O
I/O
GND
INPUT
VCC
I/O
I/O
I/O
I/O
J
I/O
I/O
I/O
I/O
H
I/O
I/O
I/O
I/O
G
I/O
VCC
I/O
I/O
GND
GND
F
I/O
I/O
I/O
I/O
I/O
I/O
E
GND
GND
I/O
I/O
VCC
I/O
D
I/O
I/O
I/O
I/O
C
I/O
I/O
I/O
I/O
B
I/O
I/O
I/O
I/O
A
I/O
I/O
I/O
I/O
1
2
3
4
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
INPUT
INPUT/CLK
INPUT
INPUT
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
PLCC/HLCC
Top View
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
VCC
I/O
I/O
I/O
I/O
GND
GND
I/O
74
12
73
13
72
14
71
15
70
16
69
17
68
18
67
19
66
20
65
21
64
7C341B
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EXPANDER
DELAY
tEXP
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY
CONTROL DELAY
tLAC
LOGIC ARRAY
DELAY
tLAD
I/O
INPUT INPUT
7C341B
I/O
INPUT INPUT
GND
I/O
I/O
I/O
I/O
INPUT/
INPUT CLK
GND
I/O
I/O
I/O
I/O
8
9
10
11
VCC
5
I/O
6
7
REGISTER
OUTPUT
DELAY
tCLR
tPRE
tRSU
tRH
tRD
tCOMB
tLATCH
INPUT/
OUTPUT
tOD
tXZ
tZX
SYSTEM CLOCK DELAY tICS
PIA
DELAY
tPIA
CLOCK
DELAY
tIC
LOGIC ARRAY
DELAY
tFD
I/O DELAY
tIO
Figure 1. CY7C341B Internal Timing Model
Document #: 38-03016 Rev. *C
Page 3 of 12
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CY7C341B
Logic Array Blocks
logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
There are 12 logic array blocks in the CY7C341B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in
which they are situated.
Design Recommendations
Externally, the CY7C341B provides eight dedicated inputs,
one of which may be used as a system clock. There are 64 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
300
VCC = 5.0V
Room Temp.
200
The CY7C341B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
100
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Typical ICC vs. fMAX
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal
skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal
Document #: 38-03016 Rev. *C
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsulated in non-windowed packages.
IO OUTPUT CURRENT (mA) TYPICAL
I CC ACTIVE (mA) Typ.
Design Security
The CY7C341B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the device.
400
0
100 Hz
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC.
Unused inputs must always be tied to an appropriate logic
level (either VCC or GND). Each set of VCC and GND pins
must be connected together directly at the device. Power
supply decoupling capacitors of at least 0.2 mF must be
connected between VCC and GND. For the most effective
decoupling, each VCC pin should be separately decoupled to
GND, directly at the device. Decoupling capacitors should
have good frequency response, such as monolithic ceramic
types.
250
IOL
200
VCC = 5.0V
Room Temp.
150
100
IOH
50
0
1
2
3
4
5
VO OUTPUTVOLTAGE (V)
Output Drive Current
Page 4 of 12
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CY7C341B
Supply Voltage to Ground Potential[1].............. −2.0V to +7.0V
Maximum Ratings
DC Output Current, per Pin[1]..................... −25 mA to +25 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................-65°C to +135°C
DC Input Voltage[1]................................................−2.0V to +7.0V
Operating Range[3]
Ambient Temperature with
Power Applied............................................. –65°C to +135°C
Range
Ambient Temperature
0°C to +70°C
5V ± 5%
–40°C to +85°C
5V ± 10%
Commercial
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Industrial
VCC
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
4.75(4.5)
5.25(5.5)
V
VCC
Output HIGH Voltage
Maximum VCC rise time is 10 ms
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA[2]
2.4
V
mA[2]
VOL
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
−0.3
0.8
V
IIX
Input Current
GND ≤ VIN ≤ VCC
−10
+10
µA
IOZ
Output Leakage Current
VO = VCC or GND
−40
+40
µA
tR (Recommended)
Input Rise Time
100
ns
tF (Recommended)
Input Fall Time
100
ns
VCC = Min., IOL = 8
2.0
0.45
V
VCC+ 0.3
V
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V, f = 1.0 MHz
10
pF
COUT
Output Capacitance
VOUT = 0V, f = 1.0 MHz
20
pF
AC Test Loads and Waveforms
R1 464Ω
5V
OUTPUT
R1 464Ω
5V
OUTPUT
R2
250 Ω
50 pF
INCLUDING
JIG AND
SCOPE (a)
Equivalent to:
ALL INPUT PULSES
3.0V
R2
250 Ω
5 pF
90%
10%
GND
90%
10%
< 6 ns
< 6 ns
tR
tF
(b)
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-03016 Rev. *C
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CY7C341B
External Switching Characteristics Over the Operating Range
7C341B-25
Parameter
Description
Min.
[4]
Max.
7C341B-35
Min.
Max.
Unit
tPD1
Dedicated Input to Combinatorial Output Delay
Commercial
25
35
ns
tPD2
I/O Input to Combinatorial Output Delay[4]
Commercial
40
55
ns
tSU
Global Clock Set-up Time
Commercial
tCO1
Synchronous Clock Input to Output Delay[4]
Commercial
15
25
14
ns
20
ns
tH
Input Hold Time from Synchronous Clock Input
Commercial
0
0
ns
tWH
Synchronous Clock Input High Time
Commercial
8
12.5
ns
tWL
Synchronous Clock Input Low Time
Commercial
8
12.5
ns
fMAX
Maximum Register Toggle Frequency[5]
Commercial
62.5
40.0
MHz
tACO1
Dedicated Asynchronous Clock Input to Output Delay[4] Commercial
tAS1
Dedicated Input or Feedback Set-up Time to
Asynchronous Clock Input
Commercial
5
10
ns
tAH
Input Hold Time from Asynchronous Clock Input
10
ns
25
35
ns
Commercial
6
tAWH
Asynchronous Clock Input HIGH
Time[6]
Commercial
11
16
ns
tAWL
Asynchronous Clock Input LOW Time[6]
Commercial
9
14
ns
tCNT
Minimum Global Clock Period
Commercial
tODH
Output Data Hold Time After Clock
Commercial
2
fCNT
Maximum Internal Global Clock Frequency[7]
Commercial
50
tACNT
Minimum Internal Array Clock Frequency
Commercial
fACNT
Maximum Internal Array Clock
Frequency[7]
Commercial
20
30
2
33.3
20
50
ns
ns
MHz
30
33.3
ns
MHz
Internal Switching Characteristics Over the Operating Range
7C341B-25
Parameter
Description
Min.
tIN
Dedicated Input Pad and Buffer Delay
Commercial
tIO
I/O Input Pad and Buffer Delay
Commercial
tEXP
Expander Array Delay
Commercial
tLAD
Logic Array Data Delay
Commercial
tLAC
Logic Array Control Delay
Commercial
Delay[4]
Max
7C341B-35
Min.
Max
Unit
11
ns
6
11
ns
12
20
ns
12
14
ns
10
13
ns
5
tOD
Output Buffer and Pad
Commercial
5
6
ns
tZX
Output Buffer Enable Delay[4]
Commercial
10
13
ns
tXZ
[8]
Output Buffer Disable Delay
Commercial
13
ns
tRSU
Register Set-Up Time Relative to Clock
Signal at Register
Commercial
6
12
ns
tRH
Register Hold Time Relative to Clock
Signal at Register
Commercial
4
8
ns
tLATCH
Flow-Through Latch Delay
Commercial
3
4
ns
tRD
Register Delay
Commercial
1
2
ns
tCOMB
Transparent Mode Delay
Commercial
3
4
ns
tIC
Asynchronous Clock Logic Delay
Commercial
14
16
ns
tICS
Synchronous Clock Delay
Commercial
3
1
ns
10
Notes:
4. C1 = 35 pF.
5. The fMAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
7. This parameter is measured with a 16-bit counter programmed into each LAB.
8. C1 = 5 pF.
Document #: 38-03016 Rev. *C
Page 6 of 12
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CY7C341B
Internal Switching Characteristics Over the Operating Range (continued)
7C341B-25
Parameter
Description
Min.
Max
7C341B-35
Min.
Max
Unit
tFD
Feedback Delay
Commercial
1
2
ns
tPRE
Asynchronous Register Preset Time
Commercial
5
7
ns
tCLR
Asynchronous Register Clear Time
Commercial
5
7
ns
tPIA
Programmable Interconnect Array Delay Commercial
14
20
ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
tWH
External Synchronous
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tAS1
tAH
tAWH
tAWL
ASYNCHRONOUS
CLOCK INPUT
Document #: 38-03016 Rev. *C
Page 7 of 12
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CY7C341B
Switching Waveforms (continued)
Internal Combinatorial
tIN
INPUT PIN
t IO
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
tIC
CLOCK FROM
LOGIC ARRAY
tRSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
tFD
tCLR,tPRE
tFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tPIA
REGISTER OUTPUT
TO ANOTHER LAB
Internal Synchronous
SYSTEM CLOCK PIN
SYSTEM CLOCK
AT REGISTER
tIN
tICS
tRSU
tRH
DATA FROM
LOGIC ARRAY
Document #: 38-03016 Rev. *C
Page 8 of 12
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CY7C341B
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
tXZ
OUTPUT PIN
tZX
HIGH IMPEDANCE
STATE
Ordering Information
Speed
(ns)
25
35
Ordering Code
Package Name
Package Type
CY7C341B-25HC/HI
H84
84-lead Windowed Leaded Chip Carrier
CY7C341B-25JC/JI
J83
84-lead Plastic Leaded Chip Carrier
CY7C341B-25RC/RI
R84
84-lead Windowed Pin Grid Array
CY7C341B-35HC/HI
H84
84-lead Windowed Leaded Chip Carrier
CY7C341B-35JC/JI
J83
84-lead Plastic Leaded Chip Carrier
CY7C341B-35RC/RI
R84
84-lead Windowed Pin Grid Array
Document #: 38-03016 Rev. *C
Operating Range
Commercial/Industrial
Commercial/Industrial
Page 9 of 12
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CY7C341B
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081-**
Document #: 38-03016 Rev. *C
Page 10 of 12
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CY7C341B
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
84-Lead Windowed Pin Grid Array R84
51-80026-*B
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All product and company
names mentioned in this document are trademarks of their respective holders.
Document #: 38-03016 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
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CY7C341B
Document History Page
Document Title: CY7C341B 192-Macrocell MAX® EPLD
Document Number: 38-03016
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106316
05/17/01
SZV
Change from ecn #: 38-00137 to 38-03016
*A
113613
04/11/02
OOR
PGA package diagram dimensions were updated
*B
122227
12/28/02
RBI
Power-up requirements added to Operating Range Information
*C
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03016 Rev. *C
Page 12 of 12
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