MC14504B Hex Level Shifter for TTL to CMOS or CMOS to CMOS The MC14504B is a hex non−inverting level shifter using CMOS technology. The level shifter will shift a TTL signal to CMOS logic levels for any CMOS supply voltage between 5 and 15 volts. A control input also allows interface from CMOS to CMOS at one logic level to another logic level: Either up or down level translating is accomplished by selection of power supply levels VDD and VCC. The VCC level sets the input signal levels while VDD selects the output voltage levels. Features • UP Translates from a Low to a High Voltage or DOWN Translates • • • • • • • from a High to a Low Voltage Input Threshold Can Be Shifted for TTL Compatibility No Sequencing Required on Power Supplies or Inputs for Power Up or Power Down 3 to 18 Vdc Operation for VDD and VCC Diode Protected Inputs to VSS Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant http://onsemi.com Parameter Unit VCC DC Supply Voltage Range −0.5 to +18.0 V VDD DC Supply Voltage Range −0.5 to +18.0 V Vin Input Voltage Range (DC or Transient) −0.5 to +18.0 V Vout Output Voltage Range (DC or Transient) −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Iin, Iout VCC 1 16 VDD Aout 2 15 Fout Fin Ain 3 14 Bout 4 13 MODE Bin 5 12 Eout Cout 6 11 Ein Cin 7 10 Dout VSS 8 9 Din MARKING DIAGRAMS 16 16 14504BG AWLYWW Value TSSOP−16 DT SUFFIX CASE 948F PIN ASSIGNMENT MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol SOEIAJ−16 F SUFFIX CASE 966 SOIC−16 D SUFFIX CASE 751B MC14504B ALYWG 1 1 SOIC−16 SOEIAJ−16 16 14 504B ALYWG G 1 TSSOP−16 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator (Note: Microdot may be in either location) ORDERING INFORMATION Stresses exceeding those listed in the Maximum Ratings table may damage the See detailed ordering and shipping information in the package device. If any of these limits are exceeded, device functionality should not be dimensions section on page 2 of this data sheet. assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 9 1 Publication Order Number: MC14504B/D MC14504B LOGIC DIAGRAM VCC VDD LEVEL SHIFTER INPUT OUTPUT TTL/CMOS MODE SELECT MODE Mode Select Input Logic Levels Output Logic Levels 1 (VCC) TTL CMOS 0 (VSS) CMOS CMOS 1/6 of package shown. ORDERING INFORMATION Device MC14504BDG NLV14504BDG* MC14504BDR2G NLV14504BDR2G* MC14504BDTG NLV14504BDTG* MC14504BDTR2G NLV14504BDTR2G* MC14504BFELG Package Shipping† SOIC−16 (Pb−Free) 48 Units / Rail SOIC−16 (Pb−Free) 2500 Units / Tape & Reel TSSOP−16 (Pb−Free) 96 Units / Rail TSSOP−16 (Pb−Free) 2500 Units / Tape & Reel SOEIAJ−16 (Pb−Free) 2000 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14504B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C 125_C VCC Vdc VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit VOL − − − 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc VOH − − − 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc 5.0 5.0 5.0 5.0 10 10 15 10 15 15 − − − − − 0.8 0.8 1.5 1.5 3.0 − − − − − 1.3 1.3 2.25 2.25 4.5 0.8 0.8 1.5 1.5 3.0 − − − − − 0.8 0.8 1.4 1.5 2.9 5.0 5.0 5.0 5.0 10 10 15 10 15 15 2.0 2.0 3.6 3.6 7.1 − − − − − 2.0 2.0 3.5 3.5 7.0 1.5 1.5 2.75 2.75 5.5 − − − − − 2.0 2.0 3.5 3.5 7.0 − − − − − − − − − 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 − − − − – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 − − − − – 1.7 – 0.36 – 0.9 – 2.4 − − − − IOL − − − 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin − 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − − 5.0 7.5 − − pF IDD or ICC − − − 5.0 10 15 − − − 0.05 0.10 0.20 − − − 0.0005 0.0010 0.0015 0.05 0.10 0.20 − − − 1.5 3.0 6.0 mAdc Quiescent Current (Per Package) TTL−CMOS Mode IDD 5.0 5.0 5.0 5.0 10 15 − − − 0.5 1.0 2.0 − − − 0.0005 0.0010 0.0015 0.5 1.0 2.0 − − − 3.8 7.5 15 mAdc Quiescent Current (Per Package) TTL−CMOS Mode ICC 5.0 5.0 5.0 5.0 10 15 − − − 5.0 5.0 5.0 − − − 2.5 2.5 2.5 5.0 5.0 5.0 − − − 6.0 6.0 6.0 mAdc Characteristic Output Voltage Vin = 0 V Symbol “0” Level “1” Level Vin = VCC Input Voltage “0” Level (VOL = 1.0 Vdc) TTL−CMOS (VOL = 1.5 Vdc) TTL−CMOS (VOL = 1.0 Vdc) CMOS−CMOS (VOL = 1.5 Vdc) CMOS−CMOS (VOL = 1.5 Vdc) CMOS−CMOS VIL Input Voltage “1” Level (VOH = 9.0 Vdc) TTL−CMOS (VOH = 13.5 Vdc) TTL−CMOS (VOH = 9.0 Vdc) CMOS−CMOS (VOH = 13.5 Vdc) CMOS−CMOS (VOH = 13.5 Vdc) CMOS−CMOS VIH Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) IOH (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Quiescent Current (Per Package) CMOS−CMOS Mode Source Sink Vdc Vdc mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 3 MC14504B SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Propagation Delay, High to Low Symbol Shifting Mode VCC Vdc VDD Vdc Min Limits Typ (Note 3) Max Unit tPHL TTL – CMOS VDD > VCC 5.0 5.0 10 15 − − 140 140 280 280 ns CMOS – CMOS VDD > VCC 5.0 5.0 10 10 15 15 5.0 5.0 10 15 15 5.0 5.0 10 10 15 − − − − − − − − 120 120 70 185 185 175 170 160 240 240 140 370 370 350 340 320 5.0 5.0 10 10 15 15 − − − 10 15 15 5.0 5.0 10 5.0 10 15 − − − − − − − − − 170 170 100 275 275 145 100 50 40 340 340 200 550 550 290 200 100 80 CMOS – CMOS VCC > VDD Propagation Delay, Low to High tPLH TTL – CMOS VDD > VCC CMOS – CMOS VDD > VCC CMOS – CMOS VCC > VDD Output Rise and Fall Time tTLH, tTHL ALL ns ns 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 7 VSp , INPUT SWITCHPOINT VOLTAGE (Vdc) VSp , INPUT SWITCHPOINT VOLTAGE (Vdc) 7 6 VCC = 10 V 5 4 3 VCC = 5 V 2 1 6 5 4 3 2 1 0 0 0 5 10 15 VDD, SUPPLY VOLTAGE (Vdc) 20 0 Figure 1. Input Switchpoint CMOS to CMOS Mode 20 20 ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ 15 10 5 5 10 15 VDD, SUPPLY VOLTAGE (Vdc) 20 Figure 2. Input Switchpoint TTL to CMOS Mode VDD, SUPPLY VOLTAGE (Vdc) VDD, SUPPLY VOLTAGE (Vdc) VCC = 5 V ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 15 10 0 5 0 0 5 10 15 VCC, SUPPLY VOLTAGE (Vdc) 20 0 Figure 3. Operating Boundary CMOS to CMOS Mode 5 10 15 VCC, SUPPLY VOLTAGE (Vdc) 20 Figure 4. Operating Boundary TTL to CMOS Mode http://onsemi.com 4 MC14504B PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ S K K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 5 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC14504B PACKAGE DIMENSIONS SOIC−16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 6 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC14504B PACKAGE DIMENSIONS SOEIAJ−16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966 ISSUE A 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M_ E HE 1 L 8 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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