Maxim MAX1147 Multichannel, true-differential, serial, 14-bit adc Datasheet

19-3488; Rev 1; 1/05
KIT
ATION
EVALU
BLE
A
IL
A
V
A
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Features
♦ 8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1148/MAX1149)
♦ 4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1146/MAX1147)
♦ Internal Multiplexer and T/H
♦ Single-Supply Operation
4.75V to 5.25V Supply (MAX1146/MAX1148)
2.7V to 3.6V Supply (MAX1147/MAX1149)
♦ Internal Reference
+4.096V (MAX1146/MAX1148)
+2.500V (MAX1147/MAX1149)
♦ 116ksps Sampling Rate
♦ Low Power
1.1mA (116ksps)
120µA (10ksps)
12µA (1ksps)
300nA (Power-Down Mode)
♦ SPI-/QSPI-/MICROWIRE Compatible
♦ 20-Pin TSSOP
Applications
Portable Data Logging
Data Acquisition
Pin Configurations appear at end of data sheet.
Medical Instruments
Battery-Powered Instruments
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Process Control
Ordering Information/Selector Guide
PART
TEMP
RANGE
PINPACKAGE
INL
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
MAX1146BCUP
0°C to +70°C
20 TSSOP
±2
4
+4.096
MAX1146BEUP
-40°C to +85°C
20 TSSOP
±2
4
+4.096
MAX1147BCUP
0°C to +70°C
20 TSSOP
±2
4
+2.500
MAX1147BEUP
-40°C to +85°C
20 TSSOP
±2
4
+2.500
MAX1148BCUP
0°C to +70°C
20 TSSOP
±2
8
+4.096
MAX1148BEUP
-40°C to +85°C
20 TSSOP
±2
8
+4.096
MAX1149BCUP
0°C to +70°C
20 TSSOP
±2
8
+2.500
MAX1149BEUP
-40°C to +85°C
20 TSSOP
±2
8
+2.500
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1146–MAX1149
General Description
The MAX1146–MAX1149 low-power, 14-bit, multichannel, analog-to-digital converters (ADCs) feature an
internal track/hold (T/H), voltage reference, and clock.
The MAX1146/MAX1148 operate from a single +4.75V
to +5.25V supply, and the MAX1147/MAX1149 operate
from a single +2.7V to +3.6V supply. All analog inputs
are software configurable for unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The serial strobe output (SSTRB) allows convenient connection to digital signal processors. The
MAX1146–MAX1149 use an internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions.
The MAX1146/MAX1148 include an internal +4.096V
reference, while the MAX1147/MAX1149 include an
internal +2.500V reference. All devices accept an external reference from 1.5V to VDD.
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes. Using the software power-down modes allows the devices to be powered down between conversions. When powered down,
accessing the serial interface automatically powers up
the devices. The quick turn-on time allows power-down
between all conversions. This technique reduces supply current to under 120µA for quick turn-on.
The MAX1146–MAX1149 are available in a 20-pin
TSSOP package.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND..........................-0.3V to (VDD + 0.3V)
REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA = +70°C)
20 TSSOP (derate 10.9mW/°C above +70°C) .............879mW
Operating Temperature Ranges
MAX114_ BC_ _ ..................................................0°C to +70°C
MAX114_ BE_ _ ...............................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.7
±2
LSB
±0.5
+1.5
LSB
DC ACCURACY (Note 1)
Resolution
14
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
No missing codes over temperature
-1.0
Bits
Offset Error
±10
Offset Temperature Coefficient
0.3
Gain Error
(Note 3)
LSB
ppm/°C
±20
Gain Temperature Coefficient
LSB
±0.8
ppm/°C
Channel-to-Channel Offset
Matching
±1
LSB
Channel-to-Channel Gain
Matching
±1
LSB
DYNAMIC SPECIFICATIONS (1kHz sine-wave input, 2.5VP-P, full-scale analog input, 116ksps, 2.1MHz external clock)
Signal-to-Noise Plus Distortion
Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Channel-to-Channel Crosstalk
2
77
Up to the 5th harmonic
81
-96
84
dB
-88
dB
98
dB
(Note 4)
-85
dB
Small-Signal Bandwidth
SSBW
-3dB point
3.0
MHz
Full-Power Bandwidth
CONVERSION RATE
FPBW
SINAD > 68dB
2.0
MHz
Conversion Time (Note 5)
tCONV
External clock, 2.1MHz 15 SCLK cycles
Internal clock
7.2
6
_______________________________________________________________________________________
8
µs
Multichannel, True-Differential,
Serial, 14-Bit ADCs
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
Throughput Rate
SYMBOL
fSAMPLE
T/H Acquisition Time
Aperture Delay
tACQ
tAD
Aperture Jitter
tAJ
Serial Clock Frequency
fSCLK
CONDITIONS
Internal clock mode,
fSCLK = 2.1MHz
MIN
TYP
18 clocks/conversion
MAX
24 clocks/conversion
51.5
External clock mode, 18 clocks/conversion
fSCLK = 2.1MHz
24 clocks/conversion
116.66
µs
20
ns
<50
ps
External clock mode
0.1
2.1
Internal clock mode
0
2.1
Internal Clock Frequency
ANALOG INPUTS (CH0–CH7, COM)
2.1
Unipolar, COM = 0
Bipolar, COM = VREF / 2, single-ended
Multiplexer Leakage Current
On/off-leakage current, VCH_ = 0 to VDD
ksps
87.50
1.4
Input Voltage Range, SingleEnded and Differential (Note 6)
UNITS
60.3
0
MHz
VREF
±VREF / 2
±0.01
Input Capacitance
MHz
±1
18
V
µA
pF
INTERNAL REFERENCE (CREF = 2.2µF, CREFADJ = 0.01µF)
REF Output Voltage
VREF
REF Short-Circuit Current
VREF Tempco (Note 7)
Load Regulation
IREFSC
MAX1147/MAX1149, TA = +25°C
2.480
2.500
2.520
MAX1146/MAX1148, TA = +25°C
4.076
4.096
4.116
MAX114_ BC _ _
±30
±50
MAX114_ BE _ _
±40
±60
REF = DGND
20
0 to 0.2mA output load (Note 8)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
2.0
Reference Buffer Voltage Gain
ppm/°C
mV
µF
0.01
µF
REFADJ Input Range
Pull REFADJ high to disable the internal
bandgap reference and reference buffer
mA
2
REFADJ Output Voltage
REFADJ Logic High
V
1.250
V
±18
mV
VDD 0.25V
V
MAX1147/MAX1149
2.000
MAX1146/MAX1148
3.277
V/V
_______________________________________________________________________________________
3
MAX1146–MAX1149
ELECTRICAL CHARACTERISTICS (continued)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD +
50mV
V
EXTERNAL REFERENCE AT REF
REF Input Voltage Range
VREF
REF Input Current
IREF
1.5
Shutdown
REF Input Resistance
6
125
450
0.01
10
8
µA
kΩ
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
VIH
VDD < 3.6V
2.0
VDD > 3.6V
3.0
V
VIL
VHYST
Input Leakage
IIN
Input Capacitance
CIN
0.8
V
±1
µA
0.2
V
10
pF
DIGITAL OUTPUT (DOUT, SSTRB)
Output-Voltage Low
VOL
ISINK = 2mA
Output-Voltage High
VOH
ISOURCE = 2mA
Tri-State Leakage Current
Tri-State Output Capacitance
IL
CS = VDD
COUT
CS = VDD
0.4
V
±10
µA
VDD - 0.5
V
10
pF
POWER REQUIREMENTS
Positive Supply Voltage
Supply Current (Note 8)
VDD
IDD
MAX1147/MAX1149
2.7
3.6
MAX1146/MAX1148
4.75
5.25
Normal
operation, fullscale input
Fast power-down
Shutdown Supply Current
(Note 8)
Power-Supply Rejection (Note 9)
4
PSR
External
reference
116ksps
10ksps
1ksps
Internal reference at
116ksps
1.1
0.12
0.012
1.5
1.9
2.4
mA
mA
120
Full power-down
0.3
SHDN = DGND
0.3
External reference
V
±0.2
_______________________________________________________________________________________
µA
10
mV
Multichannel, True-Differential,
Serial, 14-Bit ADCs
(VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.) (Figures 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIN to SCLK Setup Time
tDS
50
ns
DIN to SCLK Hold Time
tDH
0
ns
SCLK Fall to Output Data Valid
tDOV
CLOAD = 50pF
80
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 50pF
10
120
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 50pF
120
ns
SHDN Rise CS Fall to SCLK Rise
Time
tCSS
50
ns
SHDN Rise CS Fall to SCLK Rise
Hold Time
tCSH
50
ns
SCLK Clock Frequency
fSCLK
SCLK Pulse-Width High
SCLK Pulse-Width Low
External clock mode
0.1
2.1
Internal clock mode
0
2.1
tCH
Internal clock mode
100
tCL
Internal clock mode
100
CS Fall to SSTRB Output Enable
tSTE
External clock mode only
120
CS Rise to SSTRB Output Disable
tSTD
External clock mode only
120
SSTRB Rise to SCLK Rise
tSCK
Internal clock mode only
SCLK Fall to SSTRB Edge
tSCST
CS Pulse Width
tCSW
ns
ns
0
ns
ns
ns
80
100
MHz
ns
ns
Note 1: Tested at VDD = 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled. Measured with external reference.
Note 4: “On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Digital inputs equal VDD or DGND.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the
MAX1146/MAX1148. VDD = 3.6V to 2.7V for MAX1147/MAX1149 and VDD = 5.25V to 4.75V for the MAX1146/MAX1148.
_______________________________________________________________________________________
5
MAX1146–MAX1149
TIMING CHARACTERISTICS
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
VDD
VDD
6kΩ
6kΩ
DOUT
DOUT
CLOAD
50pF
6kΩ
DGND
DGND
a) HIGH-Z TO VOH AND VOL TO VOH
DOUT
DOUT
CLOAD
50pF
6kΩ
DGND
DGND
b) HIGH-Z TO VOL AND VOH TO VOL
CLOAD
50pF
CLOAD
50pF
DGND
DGND
a) VOH TO HIGH-Z
Figure 1. Load Circuits for Enable Time
b) VOL TO HIGH-Z
Figure 2. Load Circuits for Disable Time
CS
tCH
tCSS
tCSW
tCL
tCSH
SCLK
1
1
8
START
SEL2
SEL1
SEL0 SGL/DIF UNI/BIP
tDOE
DOUT
HIGH-Z
SSTRB
(EXTERNAL CLOCK MODE)
HIGH-Z
24
tDH
tDS
DIN
9
tSCK
fSCLK
PD1
PD0
tACQ
tDOD
tDOV
D13
D12
D11
D10
D2
D1
D0
tSCST
tSTE
tSTD
HIGH-Z
tSCST
SSTRB
(INTERNAL CLOCK MODE)
Figure 3. Detailed Operating Characteristics
6
HIGH-Z
_______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
0.5
DNL (LSB)
0.5
0
0
-0.5
-0.5
-1.0
-1.0
-1.5
-1.5
1.8
MAX1146 toc03
1.0
INTERNAL REFERENCE
1.6
SUPPLY CURRENT (mA)
1.0
2.0
MAX1146 toc02
1.5
MAX1146 toc01
1.5
INL (LSB)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
DNL vs. OUTPUT CODE
INL vs. OUTPUT CODE
1.4
1.2
EXTERNAL REFERENCE
1.0
0.8
0.6
0.4
0.2
0
4096
8192
12288
8192
12288
16384
2.7
3.0
3.6
3.3
OUTPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
1.2
EXTERNAL REFERENCE
1.0
0.8
0.6
0.4
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.2
0
0
0.45
MAX1146 toc06
1.6
SHUTDOWN SUPPLY CURRENT (µA)
1.4
MAX1146 toc05
INTERNAL REFERENCE
1.6
1.8
SHUTDOWN SUPPLY CURRENT (µA)
MAX1146 toc04
1.8
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
4.75
4.85
4.95
5.05
5.15
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. CONVERSION RATE
SUPPLY CURRENT vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
800
600
FAST POWER-DOWN
400
MAX1146/MAX1148 INTERNAL REFERENCE
MAX1147/MAX1149 INTERNAL REFERENCE
1.5
MAX1146/MAX1148 EXTERNAL REFERENCE
1.0
MAX1147/MAX1149 EXTERNAL REFERENCE
0.5
200
FULL
POWER-DOWN
0
0.1
1
10
CONVERSION RATE (ksps)
100
1000
4.0
3.5
3.0
MAX1146/MAX1148
2.5
2.0
1.5
1.0
MAX1147/MAX1149
0.5
0
0
0.01
5.25
MAX1146 toc09
2.0
SUPPLY CURRENT (mA)
1000
4.5
SHUTDOWN SUPPLY CURRENT (µA)
2.5
MAX1146 toc07
1200
MAX1146 toc08
SUPPLY CURRENT (mA)
4096
OUTPUT CODE
2.0
SUPPLY CURRENT (µA)
0
0
16384
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1146–MAX1149
Typical Operating Characteristics
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
2.5015
4.0970
4.0965
4.0960
4.0955
4.0950
2.5010
4.099
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
4.0975
4.100
MAX1146 toc11
2.5020
MAX1146 toc10
4.0980
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1146/MAX1148)
2.5005
2.5000
2.4995
2.4990
MAX1146 toc12
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
REFERENCE VOLTAGE (V)
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.0945
2.4985
4.0940
2.4980
4.95
5.05
4.090
2.7
5.25
5.15
3.0
3.6
3.3
10
2.502
2500
CREF = 4.7µF
CREFADJ = 0.01µF
2000
DELAY (µs)
2.501
2.500
35
REFERENCE BUFFER POWER-UP DELAY
vs. TIME IN SHUTDOWN
MAX1146 toc13
2.503
REFERENCE VOLTAGE (V)
-15
TEMPERATURE (°C)
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1147/MAX1149)
1500
1000
2.499
500
2.498
0
0.001
2.497
10
35
60
85
0.01
0.1
10
1
TEMPERATURE (°C)
TIME IN SHUTDOWN (s)
FFT PLOT
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
fIN = 1kHz
fSAMPLE = 116ksps
VDD = 5V/3V
13.0
12.9
EFFECTIVE NUMBER OF BITS
-15
MAX1146 toc15
-40
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12.0
0
1000
2000
3000
4000
FREQUENCY (Hz)
8
-40
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX1146 toc14
4.85
4.091
MAX1146 toc16
4.75
AMPLITUDE (dB)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
5000
1
10
19
28
37
46
FREQUENCY (kHz)
_______________________________________________________________________________________
55
60
85
Multichannel, True-Differential,
Serial, 14-Bit ADCs
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
2
0
-2
MAX1146 toc18
-1
OFFSET ERROR (LSB)
4
OFFSET ERROR (LSB)
0
MAX1146 toc17
6
-2
-3
-4
-5
-6
-4
-7
-8
-6
3.0
3.3
4.95
5.05
5.15
SUPPLY VOLTAGE (V)
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
6
MAX1146 toc19
4
GAIN ERROR (LSB)
4
2
0
-2
-4
5.25
2
0
-2
-4
-6
-6
2.7
3.0
3.3
3.6
4.75
4.85
4.95
5.05
5.15
5.25
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
6
6
4
GAIN MATCHING (LSB)
2
0
-2
-4
XMAX1146 toc22
SUPPLY VOLTAGE (V)
MAX1146 toc21
SUPPLY VOLTAGE (V)
4
GAIN MATCHING (LSB)
4.85
SUPPLY VOLTAGE (V)
6
GAIN ERROR (LSB)
4.75
3.6
MAX1146 toc20
2.7
2
0
-2
-4
-6
-6
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
MAX1146–MAX1149
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
2
0
-2
2
0
-2
-4
-4
-6
-6
-40
-15
10
35
60
2.7
85
3.0
SUPPLY VOLTAGE (V)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
4
OFFSET MATCHING (LSB)
2
0
-2
MAX1146 toc26
6
MAX1146 toc25
4
2
0
-2
-4
-4
-6
-6
4.75
4.85
4.95
5.05
5.15
-40
5.25
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
GAIN ERROR vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
4
OFFSET ERROR (LSB)
4
2
0
-2
-4
MAX1146 toc28
6
MAX1146 toc27
6
2
0
-2
-4
-6
-6
-40
-15
10
35
TEMPERATURE (°C)
10
3.6
3.3
TEMPERATURE (°C)
6
OFFSET MATCHING (LSB)
MAX1146 toc24
4
OFFSET MATCHING (LSB)
4
GAIN MATCHING (LSB)
6
MAX1146 toc23
6
GAIN ERROR (LSB)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
______________________________________________________________________________________
85
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1148 MAX1146
MAX1149 MAX1147
NAME
FUNCTION
1
1
CH0
2
2
CH1
3
3
CH2
4
4
CH3
5
—
CH4
6
—
CH5
7
—
CH6
8
—
CH7
9
9
COM
Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.
10
10
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current
to 0.2µA. Driving shutdown high enables the devices.
11
11
REF
12
12
REFADJ
13
13
AGND
14
14
DGND
Digital Ground
Analog Inputs
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01µF
capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and referencebuffer amplifier.
Analog Ground
15
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.
16
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).
17
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.
18
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19
19
SCLK
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed
in external clock mode. (Duty cycle must be 40% to 60%.)
20
20
VDD
Positive Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
—
5–8
N.C.
No Connection. Not internally connected.
______________________________________________________________________________________
11
MAX1146–MAX1149
Pin Description
PIN
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Detailed Description
The MAX1146–MAX1149 ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 4 shows the typical application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
True-Differential Analog Input and
Track/Hold
The MAX1146–MAX1149 analog input architecture contains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
VDD
10Ω
VDD
CH0
CH1
CH2
ANALOG
INPUTS
2.2µF
VDD
0.1µF
MAX1148
MAX1149
CH3
4.7µF
SHDN
I/O
CH4
SCLK
SCK
CH5
CS
I/O
CH6
DIN
MOSI
CH7
SSTRB
REF
DOUT
COM
AGND
µP
I/O
MISO
REFADJ
DGND
VSS
0.01µF
Figure 4. Typical Application Circuit
CS
SCLK
DIN
INPUT
SHIFT
REGISTER
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ANALOG
INPUT
MUX
INTERNAL
CLOCK
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
T/H
IN
DOUT
SSTRB
CLOCK
SAR
OUT
ADC
REF
VDD
COM
+1.250V
BANDGAP
REFERENCE
20kΩ
REFADJ
REF
MAX1149
DGND
AGND
AV = 2.0V/V
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
CT/H+ and CT/H- track the analog input signal. At the
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retaining the charge on CT/H+ and CT/H- as a sample of the
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF × (VIN+ - VIN-) from
C T/H+ and C T/H- to the binary-weighted capacitive
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is complete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisition time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (tACQ) in which the T/H capacitance
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (RSOURCE) should be minimized to allow the T/H capacitance to charge within
this allotted time.
tACQ = 11.5 × (RSOURCE + RIN) × CIN
where RSOURCE is the analog input source impedance,
RIN is 2.6kΩ (which is the sum of the analog input MUX
and T/H switch resistances), and CIN is 18pF (which is
the sum of CT/H+, CT/H-, and input stray capacitance).
To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
Figure 5. Functional Diagram
12
______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
ANALOG INPUT MUX
CH0
MAX1148
MAX1149
CH1
REF
CH2
CT/H+
IN+
14-BIT
CAPACITIVE
DAC
CH3
TRACK
CH4
HOLD
HOLD
HOLD
CH5
TRACK
TRACK
14-BIT
CAPACITIVE
DAC
IN-
CH6
CT/HCH7
REF
COM
Figure 6. Equivalent Input Circuit
Input Bandwidth
Quick Look
The MAX1146–MAX1149 feature input tracking circuitry
with a 3.0MHz small-signal bandwidth. The 3.0MHz
input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Use the circuit of Figure 7 to quickly evaluate the
MAX1148/MAX1149. The MAX1148/MAX1149 require a
control byte to be written to DIN using SCLK before
each conversion. Connecting DIN to VDD and clocking
SCLK feeds in a control byte of $FF HEX (see Table 1).
Trigger single-ended unipolar conversions on CH7 in
external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for two clock periods before the MSB of the
14-bit conversion result is shifted out of DOUT. Varying
the analog input to CH7 alters the sequence of bits
from DOUT. A total of 18 clock cycles are required per
conversion (Figure 10). All transitions of the SSTRB and
DOUT outputs occur on the falling edge of SCLK.
Analog Input Protection
Internal protection diodes clamp the analog input to
VDD and AGND. These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (VDD + 0.3V) without
causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below
AGND or above VDD.
Note: If the analog input exceeds 50mV beyond the supply rails, limit the current to 2mA.
______________________________________________________________________________________
13
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
VDD
10Ω
OSCILLOSCOPE
10Ω
AIN
CH7
0.01µF
MAX1148
MAX1149
VDD
DIN
0.1µF
4.7µF
SHDN
SCLK
EXTERNAL CLOCK
SCLK
REFADJ
DOUT
SSTRB
0.01µF
DOUT*
SSTRB
REF
VREF
COM
2.2µF
CS
CH1
DGND
AGND
MAX1149 VREF = +2.500V
MAX1148 VREF = +4.096V
VCOM ≤ AIN ≤ VREF
CH2
CH3
CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF HEX
Figure 7. Quick-Look Circuit
Table 1. Control Byte Format
BIT
NAME
7 (MSB)
START
DESCRIPTION
6
SEL2
5
SEL1
4
SEL0
3
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode,
input signal voltages are referred to COM. In differential mode, the voltage difference between two channels
is measured.
2
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, connect COM to
AGND to perform conversion from 0 to VREF. In bipolar mode, connect COM to VREF/2 to perform conversion
from 0 to VREF. See Table 7.
1
PD1
0 (LSB)
PD0
Start bit. The first logic 1 bit after CS goes low defines the beginning of the control byte.
Channel-select bits. The channel-select bits select which of the eight channels are used for the conversion
(Tables 2, 3, 4, and 5).
Selects clock and power-down modes.
PD1 = 0 and PD0 = 0 selects full power-down mode*.
PD1 = 0 and PD0 = 1 selects fast power-down mode*.
PD1 = 1 and PD0 = 0 selects internal clock mode.
PD1 = 1 and PD0 = 1 selects external clock mode.
*The start bit resets power-down modes.
14
______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
SEL2
SEL1
SEL0
CH0
0
0
0
+
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
-
+
+
+
+
+
+
+
-
Table 3. MAX1148/MAX1149 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
0
+
-
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
SEL1
SEL0
CH0
0
0
0
+
1
0
0
0
0
1
1
0
1
CH3
+
-
CH4
CH5
+
-
-
CH7
+
-
-
+
+
-
CH1
CH6
+
Table 4. MAX1146/MAX1147 Channel
Selection in Single-Ended Mode
(SGL/DIF = 1)
SEL2
CH2
CH2
CH3
+
+
+
+
Table 5. MAX1146/MAX1147 Channel
Selection in Differential Mode
(SGL/DIF = 0)
COM
SEL2
SEL1
SEL0
CH0
CH1
-
0
0
0
+
-
-
+
-
0
0
1
-
1
0
0
-
1
0
1
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1146–MAX1149 in internal
clock mode, making the MAX1146–MAX1149 ready to
convert with SSTRB high. No conversions should be
performed until the power supply is stable. The first logical 1 on DIN with CS low is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, a rising edge on SCLK latches a bit from
DIN into the MAX1146–MAX1149 internal shift register.
After CS falls, the first logic 1 bit defines the control
CH2
CH3
+
-
-
+
byte’s MSB. Until this start bit arrives, any number of
logic 0 bits can be clocked into DIN with no effect.
Table 1 shows the control-byte format.
The MAX1146–MAX1149 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control registers. Set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI transmit a byte and receive a byte at the same
time. Using the Typical Application Circuit (Figure 4), the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the 14-bit conversion result).
______________________________________________________________________________________
15
MAX1146–MAX1149
Table 2. MAX1148/MAX1149 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Digital Output
In unipolar input mode, the digital output is straight
binary (Figure 14). For bipolar input mode, the digital
output is two’s complement binary (Figure 15). Data is
clocked out on the falling edge of SCLK in MSB-first
format.
Use internal clock mode if the serial clock frequency is
less than 100kHz or if serial clock interruptions could
cause the conversion interval to exceed 140µs. The
conversion must complete in 140µs, or droop on the
T/H capacitors can degrade conversion results.
Internal Clock
When configured for internal clock mode, the
MAX1146–MAX1149 generate an internal conversion
clock. This frees the µP from the burden of running the
SAR conversion clock and allows the conversion results
to be read back at the processor’s convenience, at any
clock rate up to 2.1MHz. SSTRB goes low at the start of
the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 8.0µs,
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is in
progress. SCLK clocks the data out of this register at any
time after the conversion is complete. After SSTRB goes
high, the second falling SCLK clock edge produces the
MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figures 9 and 11).
For the most accurate conversion, the MAX1146–
MAX1149 digital I/O should remain inactive during the
internal clock conversion interval (tCONV). Do not pull
CS high during conversion. Pulling CS high aborts the
current conversion. To ensure that the next start bit is
recognized, clock in 18 zeros at DIN. When internal
clock mode is selected, SSTRB does not go into a highimpedance state when CS goes high. A rising edge on
SSTRB indicates that the MAX1146–MAX1149 have finished the conversion. The µP can then read the conversion results at its convenience.
Clock Modes
The MAX1146–MAX1149 can use either the external
serial clock or the internal clock to drive the successive-approximation conversion. The external clock
shifts data in and out of the MAX1146–MAX1149.
External clock mode allows the fastest throughput rate
(116ksps) and serial clock frequencies from 0.1MHz to
2.1MHz. Internal clock mode provides the best noise
performance because the digital interface can be idle
during conversion. The internal clock mode serial clock
frequency can range from 0 to 2.1MHz. Internal clock
mode allows the CPU to request a conversion and
clock back the results.
Bits PD1 and PD0 of the control byte program the clock
and power-down modes. The MAX1146–MAX1149 power
up in internal clock mode with all circuits activated.
Figures 8–11 illustrate the available clocking modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but it also drives the analog-todigital conversion. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successiveapproximation bit decisions are made and the results
appear at DOUT on each of the next 14 SCLK falling
edges (Figures 8 and10). SSTRB and DOUT go into a
high-impedance state when CS is high.
CS
SCLK
1
8
9
16
24
CB1
DIN
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
tACQ
SSTRB
HIGH-Z
DOUT
HIGH-Z
HIGH-Z
D13 D12 D11 D10
INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE
INPUT T/H
tCONV
SET TO CB1
D9
D8
D7
OPEN
TRACK
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
RESET TO CB1
HOLD
Figure 8. External Clock Mode—24 Clocks/Conversion Timing
16
______________________________________________________________________________________
TRACK
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
CS
SCLK
1
8
9
16
24
CB1
DIN
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
tCONV
tACQ
SSTRB
DOUT
HIGH-Z
D13 D12 D11 D10
INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE
INPUT T/H
SET TO CB1
OPEN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
RESET TO CB1
TRACK
HOLD
TRACK
Figure 9. Internal Clock Mode Timing—24 Clocks/Conversion Timing
CS
SCLK
1
8
1
4
10
11
18
CB1
DIN
START SEL2
1
4
10
11
15
CB2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
START SEL2
PD0
SEL1 SEL0 SGL/DIF UNI/BIP PD1
START SEL2
PD0
SEL1 SEL0 SGL/DIF UNI/BIP
tACQ
tCONV
tACQ
SSTRB
HIGH-Z
DOUT
D13 D12
D5
D4
D3
D2
D1
D13 D12
D0
D5
D4
D3
D2
D1
D0
SET ACCORDING TO PREVIOUS
CONTROL BYTE
INPUT T/H
SET TO CB2
SET TO CB1
INPUT MUX
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 10. External Clock Mode—18 Clocks/Conversion Timing
Applications Information
Idle Mode
The device is considered idle when all the bits have been
clocked out or 18 zeros have been clocked in on DIN.
Start Bit
The falling edge of CS alone does not start a conversion. The first logic high clocked into DIN with CS low is
interpreted as a start bit and defines the first bit of the
control byte. The device begins to track on the fifth
falling edge of SCLK after a start bit has been recognized. A conversion starts on the eighth falling edge of
SCLK as the last bit of the control byte is being clocked
in. The start bit is defined as follows:
1) The first high bit clocked into DIN with CS low any
time the converter is idle.
or
2) The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto DOUT
(Figures 10 and 11).
Toggling CS before the current conversion is complete
aborts the conversion and clears the output register.
The fastest the MAX1146–MAX1149 can run with CS held
low between conversions is 18 clocks per conversion.
Figures 10 and 11 show the serial-interface timing necessary to perform a conversion every 18 SCLK cycles.
______________________________________________________________________________________
17
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
CS
SCLK
1
8
1
4
10
11
18
CB1
DIN
1
4
10
11
CB2
START SEL2 SEL1 SEL0 SGL/DIFUNI/BIP PD1
START SEL2 SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
tACQ
tCONV
START SEL2
PD0
tACQ
tCONV
SSTRB
HIGH-Z
DOUT
D13 D12
D5
D4
D3
D2
D1
D0
D13
D12
D5
D4
SET ACCORDING TO PREVIOUS
CONTROL BYTE
INPUT MUX
SET TO CB1
INPUT T/H
OPEN
TRACK
SET TO CB2
RESET TO CB1
HOLD
TRACK
OPEN
HOLD
RESET TO CB2
TRACK
Figure 11. Internal Clock Mode—18 Clocks/Conversion Timing
Shutdown and Power-Down Modes
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes.
Pulling SHDN low places the converter in hardware
shutdown. The conversion is immediately terminated
and the supply current is reduced to 300nA. Allow 2ms
for the device to power-up when the internal reference
buffer is used with C REFADJ = 0.01µF and C REF =
2.2µF. Larger capacitors on C REFADJ and C REF
increase the power-up time (Table 6). No wake-up time
is needed for the device to power-up from fast powerdown when using an external reference.
Select a software power-down mode through the PD1
and PD0 bits of the control byte (Table 1). When the
conversion in progress is complete, software powerdown is initiated. The serial interface remains active
and the last conversion result can be clocked out. In
full power-down mode, only the serial interface remains
operational and the supply current is reduced to
300nA. In fast power-down mode, only the bandgap
reference and the serial interface remain operational,
and the supply current is reduced to 600µA.
Table 6. Internal Reference Buffer PowerUp Times vs. Bypass Capacitors
POWER-UP TIMES FROM AN
EXTENDED POWER-DOWN
CREFADJ*
CREF
0.01µF
4.7µF
2ms
0.1µF
10µF
25ms
*Power-up times are dominated by CREFADJ.
18
The MAX1146–MAX1149 automatically wake up from
software power-down when they receive the control
byte’s start bit (Table 1). Allow 2ms for the device to
power-up when the internal reference buffer is used
with C REFADJ = 0.01µF and C REF = 2.2µF. Larger
capacitors on CREFADJ and CREF increase the powerup time (Table 6). No wake-up time is needed for the
device to power-up from fast power-down when using
an external reference.
Reference Voltage
The MAX1146–MAX1149 can be used with an internal
or external reference voltage. The reference voltage
determines the ADC input range. The reference determines the full-scale output value (Table 7).
Internal Reference
The MAX1146–MAX1149 contain an internal 1.250V
bandgap reference. This bandgap reference is connected to REFADJ through a 20kΩ resistor. Bypass REFADJ
with a 0.01µF capacitor to AGND. The MAX1146/
MAX1148 reference buffer has a 3.277V/V gain to provide +4.096V at REF. The MAX1147/MAX1149 reference
buffer has a 2.000V/V gain to provide +2.500V at REF.
Bypass REF with a minimum 2.2µF capacitor to AGND
when using the internal reference.
External Reference
An external reference can be applied to the
MAX1146–MAX1149 in two ways:
1) Disable the internal reference buffer by connecting
REFADJ to VDD and apply the external reference to
REF (Figure 12).
2) Utilize the internal reference buffer by applying an
external reference to REFADJ (Figure 13).
______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
+3.3V
IN
24kΩ
SAR
ADC
MAX1146–
MAX1149
REF
REF
3.000V
OUT
MAX6163
MAX1146–
MAX1149
0.1µF
0.047µF
GND
REFADJ
+5V
VDD
Figure 13. Reference Adjust Circuit
0.1µF
1.250V
BANDGAP
REFERENCE
REFADJ
100kΩ
REFERENCE
BUFFER
DISABLED
20kΩ
510kΩ
DGND
with a 0.01µF capacitor and bypass REF with a 2.2µF
capacitor to AGND.
AGND
Transfer Function
Figure 12. External Reference Applied to REF
Method 1 allows the direct application of an external
reference from 1.5V to VDD + 50mV. The REF input
impedance is typically 10kΩ. During conversion, an
external reference at REF must deliver up to 210µA and
have an output impedance less than 10Ω. Bypass REF
with a 0.1µF capacitor to AGND to improve its output
impedance.
Method 2 utilizes the internal reference buffer to reduce
the external reference load. The REFADJ input impedance is typically 20kΩ. During a conversion, an external
reference at REFADJ must deliver at least 100µA and
have an output impedance less than 100Ω. The
MAX1146/MAX1148 reference buffer has a 3.277V/V
gain and the MAX1147/MAX1149 has a gain of
2.000V/V. The external reference voltage at REFADJ
multiplied by the reference buffer gain is the SAR ADC
reference voltage. This reference appears at REF and
must be from 1.5V to VDD + 50mV. Bypass REFADJ
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Output data coding for the MAX1146–MAX1149 is binary in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = (VREF/2N), where N is the
number of bits (14). Code transitions occur halfway
between successive-integer LSB values. Figure 14 and
Figure 15 show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively.
Serial Interfaces
The MAX1146–MAX1149 feature a serial interface that
is fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the
serial clock for the ADCs. Select a clock frequency up
to 2.1MHz.
SPI and MICROWIRE Interface
When using an SPI (Figure 16a) or MICROWIRE interface
(Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE
INPUT AND OUTPUT
MODES
ZERO SCALE
FULL SCALE
Single-Ended Mode
VCOM
VREF + VCOM
Differential Mode
VIN-
VREF + VIN-
BIPOLAR MODE
NEGATIVE FULL
SCALE
−V
REF + V
COM
2
−V
REF + V −
IN
2
ZERO SCALE
VCOM
VIN-
POSITIVE FULL
SCALE
+ VREF
2
+ VCOM
+ VREF
+ VIN −
2
Note: The common mode range for the analog inputs is from AGND to VDD.
______________________________________________________________________________________
19
MAX1146–MAX1149
+5V
1 LSB =
VREF
16384
1 LSB =
1
2
3
16381 16383
1...111
1...110
1...101
1...100
0...001
0...000
0...111
VREF
VREF
0...011
0...010
0...001
0...000
TWO'S COMPLEMENT BINARY OUTPUT CODE (LSB)
1...111
1...110
1...101
1...100
0
VREF
16384
VREF
VREF
BINARY OUTPUT CODE (LSB)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
0...011
0...010
0...001
0...000
0
1
2
3
INPUT VOLTAGE (LSB)
8191 8193
8192
INPUT VOLTAGE (LSB)
16381 16383
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function
edge and is clocked into the µP on SCLK’s rising edge.
The first 8-bit data stream contains the first 8-bits of
DOUT starting with the MSB. The second 8-bit data
stream contains the remaining 6 result bits.
munication, connect the controller as shown in Figure
18 and configure the PIC16/PIC17 as system master.
Initialize the synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 8 and 9.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings are necessary
to obtain the entire 14-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge and is
clocked into the µC on SCLK’s rising edge. The first 8bit data stream contains the first 8 data bits starting
with the MSB. The second data stream contains the
remaining bits, D5 through D0.
QSPI Interface
Using the high-speed QSPI interface (Figure 17) with
CPOL = 0 and CPHA = 0, the MAX1146–MAX1149 support a maximum fSCLK of 2.1MHz. One 16-bit reading is
necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µP on SCLK’s rising edge.
The first 14 bits are the data.
PIC16/PIC17 SSP Module Interface
The MAX1146–MAX1149 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchronous serial-port (SSP) module. To establish SPI com-
I/O
SCK
MISO
VDD
CS
I/O
CS
SCLK
SK
SCLK
DOUT
SI
DOUT
MICROWIRE
SPI
SS
Figure 16a. SPI Connections
20
MAX1146–
MAX1149
MAX1146–
MAX1149
Figure 16b. MICROWIRE Connections
______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
VDD
VDD
CS
CS
SCK
MISO
VDD
QSPI
SCLK
SCLK
SCK
DOUT
DOUT
SDI
CS
I/O
MAX1146–
MAX1149
SS
PIC16/PIC17
MAX1146–
MAX1149
Figure 17. QSPI Connections
GND
GND
Figure 18. SPI Interface Connection for a PIC16/PIC17
Controller
Table 8. Detailed SSPCON Register Content
PICI6/PICI7
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
Bit 7
X
Write collision detection bit.
SSPOV
Bit 6
X
Receive overflow detect bit.
SSPEN
Bit 5
1
Synchronous serial port enable bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial-port pins.
Clock polarity select bit. CKP = 0 for SPI master mode selection.
CKP
Bit 4
0
SSPM3
Bit 3
0
SSPM2
Bit 2
0
SSPM1
Bit 1
0
SSPM0
Bit 0
1
Synchronous serial port mode select bit. Sets SPI master mode and selects
FCLK = fOSC / 16.
Table 9. Detailed SSPSTAT Register Content
MAX1146–MAX1149
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP
Bit 7
0
SPI data input sample phase. Input data is sampled at the middle of the data
output time.
CKE
Bit 6
1
SPI clock edge select bit. Data is transmitted on the rising edge of the serial
clock.
D/A
Bit 5
X
Data address bit.
P
Bit 4
X
Stop bit.
Start bit.
S
Bit 3
X
R/W
Bit 2
X
Read/write bit information.
UA
Bit 1
X
Update address.
BF
Bit 0
X
Buffer full status bit.
______________________________________________________________________________________
21
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
TMS32OLC3x Interface
Figure 19 shows an application circuit to interface the
MAX1146–MAX1149 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 20. Use the following steps to initiate a
conversion in the MAX1146–MAX1149 and to read the
results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected together with the MAX1146–MAX1149
SCLK input.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
performance. Boards should have separate analog and
digital ground planes. Ensure that digital and analog
signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one
another, or digital lines underneath the device package.
Figure 4 shows the recommended system ground connections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground point to the analog ground point directly at the
device. For lowest noise operation, the ground return to
the star ground’s power supply should be low impedance and as short as possible.
2) Drive the CS of the MAX1146–MAX1149 low
through the XF_ I/O port of the TMS320 to clock
data into the MAX1146–MAX1149 DIN.
3) Write an 8-bit word (1XXXXX11) to the
MAX1146–MAX1149 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
XF
CS
TMS320LC3x
4) The MAX1146–MAX1149 SSTRB output is monitored by the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the conversion is in progress and data is ready to be
received from the MAX1146–MAX1149.
SCLK
CLKX
CLKR
MAX1146–
MAX1149
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits represent the 14-bit conversion result followed by 2
trailing bits, which should be ignored.
DX
DIN
DR
DOUT
6) Pull CS high to disable the MAX1146–MAX1149
until the next conversion is initiated.
FSR
SSTRB
Figure 19. MAX1146–MAX1149-to-TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
SGL/DIF
UNI/BIP
PD1
PD0
HIGH-Z
SSTRB
DOUT
MSB
B12
B1
LSB
Figure 20. TMS320 Serial-Interface Timing Diagram
22
______________________________________________________________________________________
HIGH-Z
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1146–MAX1149
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:

V 2 + V32 + V4 2 + V52
THD = 20 × log  2
V1






where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Chip Information
TRANSISTOR COUNT: 5589
PROCESS: BiCMOS
______________________________________________________________________________________
23
MAX1146–MAX1149
High-frequency noise in the VDD power supply degrades
the device’s high-speed performance. Bypass the supply to the digital ground with 0.1µF and 4.7µF capacitors.
Minimize capacitor lead lengths for best supply-noise
rejection. Connect a 10Ω resistor in series with the 0.1µF
capacitor to form a lowpass filter when the power supply
is noisy.
Multichannel, True-Differential,
Serial, 14-Bit ADCs
MAX1146–MAX1149
Pin Configurations
TOP VIEW
CH0 1
20 VDD
CH0 1
20 VDD
CH1 2
19 SCLK
CH1 2
19 SCLK
CH2 3
18 CS
CH2 3
18 CS
CH3 4
17 DIN
CH3 4
16 SSTRB
CH4 5
15 DOUT
CH5 6
N.C. 7
14 DGND
CH6 7
14 DGND
N.C. 8
13 AGND
CH7 8
13 AGND
COM 9
12 REFADJ
COM 9
12 REFADJ
N.C. 5
N.C. 6
MAX1146
MAX1147
SHDN 10
11 REF
TSSOP
24
17 DIN
MAX1148
MAX1149
SHDN 10
16 SSTRB
15 DOUT
11 REF
TSSOP
______________________________________________________________________________________
Multichannel, True-Differential,
Serial, 14-Bit ADCs
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1146–MAX1149
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)