LINER LTC1065 Dc accurate, clock-tunable linear phase 5th order bessel lowpass filter Datasheet

LTC1065
DC Accurate, Clock-Tunable
Linear Phase 5th Order Bessel
Lowpass Filter
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DESCRIPTIO
FEATURES
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The LTC1065 is the first monolithic filter providing both
clock-tunability with low DC output offset and over 12-bit
DC accuracy. The frequency response of the LTC1065
closely approximates a 5th order Bessel polynomial. With
appropriate PCB layout techniques the output DC offset is
typically 1mV and is constant over a wide range of clock
frequencies. With ±5V supplies and ±4V input voltage
range, the CMR of the device is typically 80dB.
Clock-Tunable Cutoff Frequency
1mV DC Offset (Typical)
80dB CMR (Typical)
Internal or External Clock
50µVRMS Clock Feedthrough
100:1 Clock-to-Cutoff Frequency Ratio
80µVRMS Total Wideband Noise
0.004% Noise + THD at 2VRMS Output Level
50kHz Maximum Cutoff Frequency
Cascadable for Faster Roll-Off
Operates from ±2.375 to ±8V Power Supplies
Self-Clocking with 1 RC
The filter cutoff frequency is controlled either by an internal or external clock. The clock-to-cutoff frequency ratio is
100 : 1. The on-board clock is nearly power supply independent and it is programmed via an external RC. The
50µVRMS clock feedthrough of the device is considerably
lower than other existing monolithic filters.
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APPLICATI
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Audio
Strain Gauge Amplifiers
Anti-Aliasing Filters
Low Level Filtering
Digital Voltmeters
Smoothing Filters
Reconstruction Filters
The LTC1065 wideband noise is 80µVRMS and it can
process large AC input signals with low distortion. With
± 7.5V supplies, for instance, the filter handles up to
4VRMS (94dB S/N ratio) while the standard 1kHz THD is
below 0.005%; 87dB dynamic range (S/N + THD) is obtained with input levels between 2VRMS and 2.5VRMS.
The LTC1065 is available in 8-pin miniDIP and 16-pin SOL.
For a Butterworth response, see LTC1063 data sheet. The
LTC1065 is pin compatible with the LTC1063.
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TYPICAL APPLICATI
Frequency Response
3.4kHz Single 5V Supply Bessel Lowpass Filter
10
5V
0
+
1µF
TANT
4.53k
VIN
8
–10
2
7
–20
0.1µF 3
LTC1065
5
4
VOUT
6
5V
0.1µF
GAIN (dB)
4.99k
1
–30
–40
–50
–60
13k*
200pF*
* SELF-CLOCKING SCHEME
1065 TA01
–70
–80
–90
1
10
FREQUENCY (kHz)
100
1065 TA02
1
LTC1065
W W
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AXI U
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ABSOLUTE
RATI GS
Total Supply Voltage (V + to V –) .......................... 16.5V
Power Dissipation............................................. 400mW
Voltage at Any Input .... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V)
Burn-In Voltage ...................................................... 16V
Storage Temperature Range ................ – 65°C to 150°C
Operating Temperature Range
LTC1065C.......................................... – 40°C to 85°C
LTC1065M ....................................... – 55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
VIN 1
8
GND 2
7
V– 3
6
V+
CLK OUT 4
5
CLK IN
VOS ADJ
VOUT
NC 1
16 VOS ADJ
VIN 2
15 NC
14 VOUT
GND 3
LTC1065CN8
LTC1065MJ8
J8 PACKAGE
8-LEAD CERAMIC DIP
N8 PACKAGE
8-LEAD PLASTIC DIP
ORDER PART
NUMBER
TOP VIEW
NC 4
13 NC
V–
5
12 V +
NC 6
11 NC
NC 7
10 NC
9
CLK OUT 8
LTC1065CS
CLK IN
S PACKAGE
16-LEAD PLASTIC SOL
TJMAX = 150°C, θJA = 100°C/W (J)
TJMAX = 100°C, θJA = 110°C/W (N)
TJMAX = 100°C, θJA = 85°C/W
ELECTRICAL CHARACTERISTICS
VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
PARAMETER
Clock-to-Cutoff Frequency Ratio (fCLK / fC)
Maximum Clock Frequency (Note 1)
Minimum Clock Frequency (Note 2)
Input Frequency Range
Filter Gain
2
CONDITIONS
±2.375V ≤ VS ≤ ±7.5V
VS = ±7.5V
VS = ±5V
VS = ±2.5V
±2.5V ≤ VS ≤ ±7.5V, TA < 85°C
MIN
TYP
100 ± 0.5
5
4
3
30
0
VS = ±5V, fCLK = 25kHz, fC = 250Hz
fIN = 250Hz
fIN = 1kHz
VS = ±5V, fCLK = 500kHz, fC = 5kHz
fIN = 100Hz
fIN = 1kHz = 0.2fC
fIN = 2.5kHz = 0.5fC
fIN = 4kHz = 0.8fC
fIN = 5kHz = fC
fIN = 10kHz = 2fC
fIN = 20kHz = 4fC
MAX
UNITS
MHz
MHz
MHz
Hz
0.9fCLK
●
●
– 3.5
– 43.0
– 3.1
– 41.0
– 2.7
– 39.0
dB
dB
●
– 0.215
– 1.1
– 2.35
– 3.35
– 14.63
– 43.0
0
– 0.175
– 0.972
– 2.13
– 3.1
– 14.15
– 41.15
– 0.135
– 0.84
– 1.9
– 2.83
– 13.7
– 39.0
dB
dB
dB
dB
dB
dB
dB
●
●
●
●
●
LTC1065
ELECTRICAL CHARACTERISTICS
VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C, unless otherwise specified.
PARAMETER
Filter Gain
Clock Feedthrough
Wideband Noise (Note 3)
THD + Wideband Noise (Note 4)
Filter Output ± DC Swing
CONDITIONS
VS = ±2.375V, fCLK = 500kHz, fC = 5kHz
fIN = 1kHz
fIN = 2.5kHz
fIN = 4kHz
fIN = 5kHz
fIN = 10kHz
±2.375V ≤ VS ≤ ±7.5V
±2.375V ≤ VS ≤ ±7.5V, 1Hz < f < fCLK
VS = ±7.5V, fC = 20kHz, fIN = 1kHz,
2VRMS ≤ VIN ≤ 2.5VRMS
VS = ±2.375V
●
●
●
●
●
●
VS = ±5V
●
VS = ±7.5V
●
Input Bias Current
Dynamic Input Impedance
Output DC Offset (Note 5)
Output DC Offset Drift
Self-Clocking Frequency (fOSC)
External CLK Pin Logic Thresholds
Power Supply Current
VS = ±2.375V
VS = ±5V
VS = ±7.5V
VS = ±2.375V
VS = ±5V
VS = ±7.5V
R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
VS = ±2.375V
LTC1065C
LTC1065M
VS = ±5V
LTC1065C
LTC1065M
VS = ±7.5V
LTC1065C
LTC1065M
VS = ±2.375V
Min Logical “1”
Max Logical “0”
VS = ±5V
Min Logical “1”
Max Logical “0”
VS = ±7.5V
Min Logical “1”
Max Logical “0”
VS = ±2.375V, fCLK = 500kHz
LTC1065C
LTC1065M
VS = ±5V, fCLK = 500kHz
LTC1065C
LTC1065M
VS = ±7.5V, fCLK = 500kHz
LTC1065C
LTC1065M
MIN
TYP
MAX
– 0.225
– 1.1
– 2.35
– 3.35
– 14.63
– 0.185
– 1.0
– 2.15
– 3.1
–14.1
50
80
– 87
– 0.145
– 0.83
– 1.9
– 2.83
–13.7
1.5/– 2.0
1.3/– 1.8
4.0/– 4.5
3.8/– 4.3
6.5/– 7.0
6.3/– 6.8
●
●
●
●
●
●
99
95
92
100
98
97
102
101
100
4.3/– 4.8
6.8/– 7.3
103
103
100
106
106
105
106
109
108
1.43
0.47
3
1
4.5
1.5
2.5
●
●
5.5
●
●
7.0
●
●
dB
dB
dB
dB
dB
µVRMS
µVRMS
dB
1.7/– 2.2
10
800
2
0
–4
10
20
25
UNITS
±5
112
112
112
112
114
114
114
116
116
4.0
5.5
6.0
9
11
12
12.0
14.5
16.0
V
V
V
V
V
V
nA
MΩ
mV
mV
mV
µV/°C
µV/°C
µV/°C
kHz
kHz
kHz
kHz
kHz
khz
kHz
kHz
kHz
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
3
LTC1065
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: The maximum clock frequency is arbitrarily defined as: the
frequency at which the filter AC response exhibits ≥ 1dB of gain peaking.
Note 2: At limited temperature ranges (i.e., TA ≤ 50°C) the minimum clock
frequency can be as low as 10Hz. The typical minimum clock frequency is
arbitrarily defined as: the clock frequency at which the output DC offset
changes by more than 1mV.
Note 3: The wideband noise specification does not include the clock
feedthrough.
Note 4: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended. An output buffer (although recommended)
is not necessarily needed when measuring output DC offset or wideband
noise (see Figure 3).
Note 5: The output DC offset is optimized for ±5V supply. The output DC
offset shifts when the power supplies change; however this phenomenon
is repeatable and predictable.
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TYPICAL PERFOR A CE CHARACTERISTICS
Output Offset vs Clock,
Low Clock Rates
Self-Clocking Frequency vs R
Output Offset vs Clock,
Medium Clock Rates
50
110
100
5
45
VS = ±5V
40
A. TA = 25°C
B. TA = 85°C
4
VS = ±7.5V
LTC1065
4
80
R
C = 200pF
fOSC ≅ 1/RC
70
C
60
50
40
35
30
25
20
15
30
10
20
5
0
10
100
300
FREQUENCY (kHz)
3
OUTPUT OFFSET (mV)
5
OUTPUT OFFSET (mV)
500
1
–1
–2
10
Gain vs Frequency; VS = ±2.5V
110
EXTERNAL CLOCK FREQUENCY (Hz)
–5
210
Gain vs Frequency; VS = ±5V
Gain vs Frequency; VS = ±7.5V
0
0
–10
–10
–10
–20
–20
–20
GAIN (dB)
–50
B
C
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
–60
–30
A
–40
B C
D
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
–50
VIN = 750mVRMS
TA = 25°C
10
INPUT FREQUENCY (kHz)
100 200
1065 G04
E
–30
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E.f CLK = 5MHz
–40
–50
VIN = 1.4VRMS
TA = 25°C
–80
–90
1
B C
–70
VIN = 1.4VRMS
TA = 25°C
–80
–90
A
–60
–70
–80
4
D
–60
–70
500
1000
EXTERNAL CLOCK FREQUENCY (kHz)
10
0
A
0
1065 G03
10
–40
VS = ±2.5V
1065 G02
10
–30
VS = ±5V
0
–4
A
1065 G01
GAIN (dB)
2
–3
B
GAIN (dB)
R PINS 4 TO 5 (kΩ)
90
–90
1
10
INPUT FREQUENCY (kHz)
100 200
1065 G05
1
10
INPUT FREQUENCY (kHz)
100 200
1065 G06
LTC1065
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TYPICAL PERFOR A CE CHARACTERISTICS
THD vs Frequency;
VS = Single 5V, AGND = 2V
THD + Noise vs Input Voltage;
VS = Single 5V, AGND = 2V
1
1
1
fIN = 1kHz, TA = 25°C
fIN = 1kHz, TA = 25°C
0.1
THD + NOISE (%)
VIN = 0.75VRMS, S/N = 80dB
fC = 5kHz, fCLK = 500kHz
TA = 25°C
0.1
THD (%)
THD + NOISE (%)
THD + Noise vs Input Voltage;
VS = ±5V
B
A
0.01
0.01
0.1
B
0.01
A
A. fC = 10kHz, fCLK = 1MHz
B. fC = 20kHz, fCLK = 2MHz
A. fC = 5kHz, fCLK = 0.5MHz
B. fC = 10kHz, fCLK = 1MHz
0.001
0.001
0.1
1
1
5
2
3
FREQUENCY (kHz)
INPUT (VRMS)
4
1065 G07
5
0.001
0.1
1
INPUT (VRMS)
1065 G09
1065 G08
THD + Noise vs Input Voltage;
VS = ±7.5V
THD vs Frequency; VS = ±5V
THD vs Frequency;
VS = ±7.5V
1
1
1
fIN = 1kHz
TA = 25°C
THD (%)
0.01
VIN = 2.5VRMS, S/N = 90dB
fC = 10kHz, fCLK = 1MHz
TA = 25°C
0.1
0.1
THD (%)
THD + NOISE (%)
VIN = 1.5VRMS
fC = 10kHz, fCLK = 1MHz
TA = 25°C
0.1
5
B
0.01
0.01
A
A. fC = 10kHz, fCLK = 1MHz
B. fC = 20kHz, fCLK = 2MHz
0.001
0.1
0.001
10
5
FREQUENCY (kHz)
1
0
PHASE
B
B
–80
PHASE
–120
–3
fC =1kHz
fCLK =100kHz
–5
–6
100
–160
fC =10kHz
fCLK =1MHz
–200
1k
10k
INPUT FREQUENCY (Hz)
–240
100k
1065 G13
PHASE MISMATCH (±DEG)
–40
–1
–4
0.5
PHASE (DEG)
PASSBAND GAIN (dB)
0
A
Power Supply Current vs
Power Supply Voltage
0.6
40
15
VS = ± 7.5V
VIN = 1VRMS
fC = 20kHz
fCLK = 2MHz
–40°C
0.4
0.3
0.2
0.1
0
10
5
FREQUENCY (kHz)
1065 G12
Typical Phase Matching
Device to Device
±2.5V ≤ VS ≤ ±7.5V, TA = 25°C
A
1
1065 G11
Passband Gain and Phase
vs Input Frequency
–2
0.001
INPUT (VRMS)
1065 G10
1
5
POWER SUPPLY CURRENT (mA)
1
0 2
4
6 8 10 12 14 16 18 20 22 24
INPUT FREQUENCY (kHz)
1065 G14
12
25°C
9
85°C
6
3
0
0
2 4 6 8 10 12 14 16 18 20
TOTAL POWER SUPPLY VOLTAGE (V)
1065 G15
5
LTC1065
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TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
Group Delay
45
40
GROUP DELAY (µs)
35
30
25
20
15
10
VS = ±5V
fC = 10kHz
5
0
0
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV
VS = ±5V, fC = 10kHz, VIN = 1kHz ±3VP
SQUARE WAVE
3
12
6
9
15
INPUT FREQUENCY (kHz)
18
21
1065 G17
1065 G16
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PI FU CTIO S
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tantalum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when
V – is applied before V + (if V+ is allowed to go below
ground) connect a signal diode between the positive
supply pin and ground to prevent latch-up (see Typical
Applications).
Ground Pin (Pin 2, N Package)
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The frequency of the ground current equals the frequency of the
clock. The average value of this current is approximately
55µA, 110µA, 170µA for ±2.5V, ±5V and ±7.5V supplies
respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
VOS Adjust Pin (Pin 8, N Package)
The VOS adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the VOS adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
If the VOS adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the VOS adjust
pin is typically 10pA.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
The VOS adjust pin should always be connected to an AC
ground; AC signals applied to this pin will degrade the filter
response.
6
LTC1065
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PI FU CTIO S
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor RIN in
series with the input pin will not alter the value of the filter’s
DC output offset (Figure 1). RIN should however, be limited
to a maximum value (Table 1), otherwise the filter’s passband will be affected. Refer to the Applications Information
section for more details.
RIN 1
8
2
7
V
– 3
LTC1065
VOUT
6
POWER SUPPLY
VS = ±2.5V
VS = ±5V
VS = ±7.5V
VS = ±8V
VS = 5V, 0V
VS = 12V, 0V
VS =15V, 0V
VHIGH
1.5V
3V
4.5V
4.8V
4V
9.6V
12V
VLOW
0.5V
1V
1.5V
1.6V
3V
7.2V
9V
Clock Output Pin (Pin 4, N Package)
V+
5 f
CLK
4
Table 2. Clock Pin Threshold Levels
1065 F01
Figure 1.
Table 1. RIN(MAX) vs Clock and Power Supply
RIN(MAX)
VS = ±7.5V
VS = ±5V
VS = ±2.5V
fCLK = 4MHz
1.82k
–
–
fCLK = 3MHz
3.01k
2.49k
–
fCLK = 2MHz
fCLK = 1MHz
fCLK = 500kHz
fCLK = 100kHz
4.32k
9.09k
17.8k
95.3k
3.65k
8.25k
16.9k
90.9k
2.37k
7.5k
16.9k
90.9k
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade. The maximum load the filter output can drive and
still maintain the distortion levels, shown in the Typical
Performance Characteristics, is 20k.
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1065s or other ICs. The
maximum capacitance, CL(MAX), the clock output pin can
drive is illustrated in Figure 2.
200
MAXIMUM LOAD CAPACITANCE (pF )
VIN
100:1. The high (VHIGH) and low (VLOW) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
180
VS = ±2.5V
TA = 25°C
160
140
120
VS = ±5V
100
VS = ±7.5V
80
60
40
20
0
1
3
2
4 5 6 7 8 9 10
CLOCK FREQUENCY (MHz)
1065 F02
Figure 2. Maximum Load Capacitance at the Clock Output Pin
7
LTC1065
TEST CIRCUIT
+
VOUT
LT1022
VIN
1
8
2
7
3
V–
LTC1065
4
–
50k
50k
6
V+
5
0.1µF
20pF
0.1µF
CLOCK IN
1065 TC01
Figure 3. Test Circuit for THD
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APPLICATI
S I FOR ATIO
Self-Clocking Operation
The LTC1065 features an internal oscillator which can be
tuned via an external RC. The LTC1065’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
fCLK = K/RC
For clock frequencies (fCLK) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the desired clock frequency (fCLK < 500kHz), then through Figure
4b pick the right value of K, set C = 200pF and solve for R.
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85°C.
For a limited temperature range, the internal oscillator of
the LTC1065 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency variation was ±1% (VS = ±5V), and ±1.25% for VS = ±2.5V.
fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V,
TA = 25°C, C = 10pF
from Figure 6, K = 0.575,
and,
R = (0.575)/(2MHz × 14pF) = 20.5k.
Example 2:
Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V,
TA = 25°C, K = 1.0, C = 200pF
then,
1.25
1.20
R = (1.0)/(200kHz × 204pF) = 24.5k.
1.15
fCLK = K/RC
C = 200pF
TA = 25°C
1.10
K
1.05
VIN
8
1
VS = ±7.5V
VS = ±5V
0.95
7
2
V–
1.00
3
LTC1065
6
VOUT
0.90
V+
0.85
0.80
5
4
0.75
R
VS = ±2.5V
C
400
100
300
500
200
INTERNAL CLOCK FREQUENCY (kHz)
1065 F04b
1065 F04a
Figure 4a.
8
Figure 4b. fCLK vs K
LTC1065
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4
C = 200pF
fCLK CHANGE NORMALIZED
TO ITS 25°C VALUE (%)
3
2
A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
from device to device can be expected. The 2MHz clock
frequency designed above will typically drift to 1.74MHz at
70°C (Figure 7).
TA = –40°C
VS = ±5V
VS = ±2.5V
1
VS = ±7.5V
0
TA = 85°C
–1
The internal clock of the LTC1065 can be overridden by an
external clock provided that the external clock source can
drive the timing capacitor C, which is connected from the
clock input pin to ground.
VS = ±7.5V
–2
VS = ±5V
VS = ±2.5V
–3
–4
0
100
300
400
200
CLOCK FREQUENCY (kHz)
500
Output Offset
1065 F05
The DC output offset of the LTC1065 is trimmed to
typically less than ±1mV. The trimming is done at VS =
±5V. To obtain optimum DC offset performance, appropriate PC layout techniques should be used and the filter IC
should be soldered to the PC board. A socket will degrade
the output DC offset by typically 1mV. The output DC offset
is sensitive to the coupling of the clock output pin 4 (N
package) to the negative power supply pin 3 (N package).
The negative supply pin should be well decoupled. When
the surface mount package is used, all NC pins should be
grounded. When the output DC voltage is measured with
a voltmeter, the filter output pin should be buffered. Long
test leads should be avoided.
Figure 5. fCLK vs Temperature
0.80
fCLK = K/RC
C = 10pF
TA = 25°C
0.75
0.70
K
0.65
VS = ±7.5V
0.60
VS = ±5V
0.55
0.50
VS = ±2.5V
0.45
0.40
0.5
1.0
2.0
2.5
1.5
CLOCK FREQUENCY (MHz)
3.0
1065 F06
Figure 6. fCLK vs K
0.80
fCLK = K/RC
C = 10pF
TA = 70°C
0.75
0.70
Common-Mode Rejection
The common-mode rejection is defined as the change of
the output DC offset with respect to the DC change of the
input voltage applied to the filter.
K
0.65
0.60
VS = ±7.5V
0.55
0.45
0.40
0.5
CMR = 20log (∆VOS OUT /∆VIN)(dB)
VS = ±5V
0.50
VS = ±2.5V
1.0
2.0
2.5
1.5
CLOCK FREQUENCY (MHz)
With fixed power supplies, the output DC offset should not
change by more than ±100µV over 10Hz to 1MHz clock
frequency variation. When the filter clock frequency is
fixed, the output DC offset will typically change by – 4mV
(2mV) when the power supply varies from ±5V to ±7.5V
(±2.5V). See Typical Performance Characteristics.
3.0
1065 F07
Table 3 illustrates the common-mode rejection for three
power supplies and three temperatures. The commonmode rejection improves if the output offset is adjusted to
approximately 0V. The output offset can be adjusted via
pin 8 (N package). See Typical Applications.
Figure 7. fCLK vs K
9
LTC1065
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APPLICATI
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∆VIN
– 40°C
25°C
85°C
25°C
(VOS Nulled)
±1.8V
84dB
83dB
80dB
83dB
±5V
±4V
82dB
78dB
77dB
78dB
±7.5V
±6V
80dB
77dB
76dB
80dB
POWER SUPPLY
±2.5V
5mV/DIV
Table 3. CMR Data, fCLK = 100kHz
The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for
VS = ±2.5V, ±5V, ±7.5V respectively.
Clock Feedthrough
2µs/DIV
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
Figure 8. LTC1065 Output Clock Feedthrough + Noise
2µs/DIV
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
Wideband Noise
The wideband noise data is used to determine the operating signal-to-noise ratio at a given distortion level. The
wideband noise (µVRMS) is nearly independent of the value
of the clock frequency and excludes the clock feedthrough.
The LTC1065’s typical wideband noise is 80µVRMS. Figure
9 shows the same scope photo as Figure 8 but with a more
sensitive vertical scale. The clock feedthrough is imbedded in the filter’s wideband noise. The peak-to-peak wideband noise of the filter can be clearly seen; it is approximately 420µVP-P. Note that 420µVP-P equals the 80µVRMS
wideband noise of the part multiplied by a crest factor
of 5.25.
10
1065F08
0.5mV/DIV
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics which are present at the
filter’s output pin. The clock feedthrough is tested with the
filter input grounded and it depends on the quality of the
PC board layout and power supply decoupling. Any parasitic switching transients during the rise and fall of the
incoming clock, are not part of the clock feedthrough
specifications; their amplitude strongly depends on scope
probing techniques as well as ground quality and power
supply bypassing. For a power supply VS = ±5V, the clock
feedthrough of the LTC1065 is 50µVRMS; for VS = ±7.5V,
the clock feedthrough approaches 75µVRMS. Figures 8
and 9 show a typical scope photo of the LTC1065 output
pin when the input pin is grounded. The filter cutoff
frequency was 1kHz, while scope bandwidth was chosen
to be 1MHz so that switching transients above the 100kHz
clock frequency would show.
1063 F09
Figure 9. LTC1065 Output Clock Feedthrough + Noise
Aliasing
Aliasing is an inherent phenomenon of sampled data
filters. It primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1065, an input signal whose frequency is in the range
of fCLK ±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
Example:
LTC1065, fCLK = 20kHz, fC = 200kHz,
fIN = (19.6kHz, 100mVRMS)
fALIAS = (400Hz, 3.16mVRMS)
LTC1065
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Table 4. Aliasing Data
INPUT FREQUENCY
OUTPUT FREQUENCY
0.9995 fCLK
0.995 fCLK
0.99 fCLK
0.9875 fCLK
0.985 fCLK
0.9825 fCLK
0.98 fCLK
0.975 fCLK
0.97 fCLK
0.965 fCLK
0.96 fCLK
0.955 fCLK
0.95 fCLK
0.94 fCLK
0.93 fCLK
0.9
fCLK
0.0005 fCLK
0.005 fCLK
0.01 fCLK
0.0125 fCLK
0.015 fCLK
0.0175 fCLK
0.02 fCLK
0.025 fCLK
0.03 fCLK
0.035 fCLK
0.04 fCLK
0.045 fCLK
0.05 fCLK
0.06 fCLK
0.07 fCLK
0.1
fCLK
OUTPUT AMPLITUDE
REFERENCED TO
INPUT SIGNAL
– 0.01
– 0.98
– 3.13
– 4.79
– 7.21
– 10.43
– 14.14
– 21.84
– 28.98
– 35.31
– 40.94
– 45.96
– 50.46
– 58.29
– 64.90
– 80.20
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
An input RC can be used to attenuate incoming signals
close to the filter clock frequency (Figure 10). A Bessel
passband response will be maintained if the value of the
input resistor follows Table 1.
R
8
1
VIN
7
2
C
LTC1065
3
V–
5
4
0.1µF
VOUT
6
V+
0.1µF
fCLK
fCLK
1
f
≤
≤ CLK
20
2πRC
10
1065 F10
Figure 10. Adding an Input Anti-Aliasing RC
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TYPICAL APPLICATI
S
Cascading Two LTC1065s for Steeper Roll-Off
VIN
8
1
3
0.1µF
VIN
LTC1065
6
5V
5
4
0.1µF
0.1µF
7
LTC1065
6
5
5V
0.1µF
3
–5V
0.1µF
0.1µF
C
8
1
7
2
VOUT
5V
5
4
VIN
VOUT
6
R
8
2
4
7
LTC1065
C
1
3
3
–5V
0.1µF
R
–5V
8
1
2
7
2
–5V
Sharing Clock for Multichannel Applications
LTC1065
4
6
5
VOUT
5V
0.1µF
1065 TA05
fC ≅ (1/RC)(1/100)
WIDEBAND NOISE = 110µVRMS
ATTENUATION AT f = 2fC = 60dB
1065 TA04
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1065
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TYPICAL APPLICATI
S
Adjusting VOS(OUT) for
±7.5 Supply Operation
Single 5V Supply Operation (fC = 3.4kHz)
7.5V
5V
10k
VIN
4.99k
+
1µF
TANT
4.53k
0.1µF
1
8
2
7
3
10k
LTC1065
LT1009
VOUT
6
5
4
VIN
5V
0.1µF
13k
200pF
1065 TA03
V–
–7.5V
1
8
2
7
LTC1065
3
1µF
TANT
VOUT
V+
7.5V
6
5
4
+
≅2.5mV
fCLK
0.1µF
0.1µF
*
* OPTIONAL, 1N4148
1065 TA06
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J8 Package, 8-Lead Ceramic DIP
0.200
(5.080)
MAX
CORNER LEADS OPTION
(4 PLCS)
0.290 – 0.320
(7.366 – 8.128)
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0° – 15°
0.008 – 0.018
(0.203 – 0.457)
0.045 – 0.068
(1.143 – 1.727)
0.014 – 0.026
(0.360 – 0.660)
0.385 ± 0.025
(9.779 ± 0.635)
0.015 – 0.060
(0.381 – 1.524)
0.405
(10.287)
MAX
0.005
(0.127)
MIN
8
6
7
5
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
0.125
3.175
0.100 ± 0.010 MIN
(2.540 ± 0.254)
1
2
3
4
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.
N8 Package, 8-Lead Plastic DIP
0.300 – 0.320
(7.620 – 8.128)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
8
6
5
+0.025
0.325 –0.015
+0.635
8.255
–0.381
0.250 ± 0.010
(6.350 ± 0.254)
0.125
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
)
0.100 ± 0.010
(2.540 ± 0.254)
0.020
(0.508)
MIN
1
16
0.093 – 0.104
(2.362 – 2.642)
4
3
0.398 – 0.413
(10.109 – 10.490)
S Package, 16-Lead SOL
0.010 – 0.029 × 45°
(0.254 – 0.737)
2
0.018 ± 0.003
(0.457 ± 0.076)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
7
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
(
0.400
(10.160)
MAX
15
14
13
12
11
10
9
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
SEE
NOTE
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
12
Linear Technology Corporation
0.394 – 0.419
(10.007 – 10.643)
0.004 – 0.012
(0.102 – 0.305)
1
2
3
4
5
6
7
8
LT/GP 1193 10K REV 0 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1993